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Questions tagged [softcore]

A soft core is a microprocessor core that can be wholly implemented using logic synthesis.

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Get Input Text from Console on MicroBlaze Softcore

My experience with writing embedded C is pretty limited so there will probably be a simple solution to this question. I am using a Microblaze softcore on a basys 3 FPGA development board and will have ...
David777's user avatar
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How to specify iCE40 package when using Arachne-PNR

I am trying to synthesise the picorv32 picosoc for an IceFun board. So far, I have cloned the HX8Kdemo files, and modified the Makefile and PCF files accordingly. When I try to run 'make icefun' I get ...
Rocketmagnet's user avatar
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hardware software co-simulation in HDL simulator

When we simulate (VHDL) RTL designs in a simulation tool like ModelSim or ActiveHDL e.t.c, we can have a complete visibility of all signals and variables in the design. This goes a great deal in ...
gyuunyuu's user avatar
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Softcore vs hardcore for power consumption

What is the difference between soft core and hard macro processors used in FPGAs in terms of power?
achen17's user avatar
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USB Softcore for FPGA : Extra resistor on FPGA transmitter pin

Have anyone used this USB softcore before ? Why do we need extra resistance on the tx pin ONLY ? Whichever pins you transmit on need to have resistors after them. The exact values will depend ...
kevin998x's user avatar
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Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
sherinkapotein's user avatar
9 votes
2 answers
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What are the typical uses for a soft-processor such as MicroBlaze?

I know that the FPGA-DSP combination is typically used for high-end power electronics/ultrasound/MRI/etc. Is it possible for the soft-processor to fully replace the DSP even on lower-end FPGAs such ...
user02222022's user avatar
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How do I get a chinese nRF51822 development kit running examples with an ST-link, Keil uVision?

I've been working at this for days with not much information out there to assist me in fixing my issues, so I figured I'd make a post here. I'm using a cheap chinese nRF51822 module and motherboard ...
Sensors's user avatar
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What are the advantages to a separate processor when there is an FPGA present?

Consider an embedded application with both a discrete processor(ARM, AVR, PIC, etc) and an FPGA to offload some of the work or interface with specific hardware. Assuming there are sufficient ...
user1547129's user avatar
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Designing a peripheral for soft core CPU

I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what ...
Dean's user avatar
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Soft core processors vs hard core processors

I am doing a study on FPGA interfacing with microprocessors such as ARM9. I found the concept of soft core processors and hard core processors in my study. May I know what is the comparison between ...
How Xing Quan's user avatar
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Data transfer from Cortex M1 to AHB slaves

I am working on ACTEL Fusion platform which provides Cortex M1 softcore. Is it possible for AHB-lite slaves to access Cortex M1 memory. For e.g If my main C file has an array of unsigned_int 's. Is it ...
Ganesh's user avatar
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Is there an FPGA implementation of Donald Knuth's MMIX?

Does anyone know of an FPGA soft-core implementation of Donald Knuth's MMIX? My google search only found old discussions of people who knew people who were working on an FPGA implementation.
Shannon Severance's user avatar
47 votes
11 answers
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Cheapest FPGAs? [closed]

How cheap do FPGAs get? I know they're more expensive than microprocessors of comparable capability, but I wonder if there exist FPGAs that could contain a Microblaze soft core running Linux, while ...
pingswept's user avatar
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7 answers
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Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, ...