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Questions tagged [spartan]

The Spartan series's are low-cost FPGAs from Xilinx. Specify which series and part you are using.

0
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1answer
70 views

GSM Modem Transmission Issue

I'm having a problem getting this GSM modem to work with an FPGA (Spartan 3). I've already implemented UART transmission on the FPGA side,the MAX232 to convert TTL->RS232, and 3.3V->5V logic level ...
2
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1answer
129 views

VHDL Delimiter Character

I'm trying to define a string in VHDL with a pair of double quotes in the string itself. However I am unable to do so because the IDE (Xilinx ISE 14.7) only recognizes what's in-between the first pair ...
-3
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2answers
83 views

What are some good tips for handling PCB design for a spartan-6 LX9 microprocessor implementation? [closed]

My team and i are working on a MIPS implementation using Xilinx spartan-6 LX9. We have a short deadline and we want to know what are some useful tips in terms of PCB design that would reduce the risk ...
0
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1answer
37 views

FPGA Atlys Spartan 6 output predefined image or string through HDMI

I need help with displaying a short text on a hdmi display connected to the board (2 characters), I have already experimented with xapp495 but I still don't know how to do this. I understand that it ...
1
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1answer
66 views

Lucid (Verilog) intermittent generated clock signal

I'm just starting out in the world of FPGAs. I've picked up a Mojo running a Spartan-6 from Xilinx and I'm attempting to create an arbitrary clock for use with a SENT peripheral. At this point I ...
2
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1answer
837 views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
0
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1answer
176 views

How to probe into the internal signals and registers in FPGA without using JTAG?

I am using a Xilinx Spartan 3E FPGA kit in my academic project to synthesize a design comprising of a couple of 32 bit internal registers (eg few counters, shifters and some configuration registers) . ...
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2answers
359 views

How to count pressed keys on FPGA spartan board

I`m using FPGA Spartan 2 board and want to count the keys pressed from Keyboard this is my VHDL code : ...
0
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3answers
578 views

How to cross clock domains efficiently?

I have a question regarding sending a short duration signal from a faster clock domain to a slower clock domain. I am trying to implement a dual frame buffer in a dual port (dual clock) RAM. Once ...
0
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1answer
87 views

Unknown problem with I2C on Spartan 3-E {VERILOG}

I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...
0
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2answers
615 views

Verilog Error: System task finish is always executed

I'm using a Mimas V2 with a Spartan 6 CSG324 LX9. Trying to teach myself to use Verilog and I've been using this tutorial. I've had no issues running VHDL modules and running just this code Verilog ...
0
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1answer
321 views

Repeated Patterns in VGA Display [duplicate]

I'm trying to read from ROM and display the data on VGA monitor. I have verified that the ROM is functional and it works fine. But what I get on the screen is a repeated patterns of RGB. Not that ...
0
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1answer
114 views

How do I reset my registers on Digital Clock Manager output?

I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here. ...
0
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1answer
429 views

Clock Implementation Design Warning on Spartan 3E

I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager. These are my UCF ...
1
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1answer
252 views

What is the full form of XC6SLX9?

what is meant by LX9 ? I know XC is xilinx corporation and 6S stands for spartan 6.
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1answer
249 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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1answer
220 views

Problem with implementation XAPP495 [closed]

I'm working on XAPP495 to show a signal which is throughput of a HDMI signal from my Laptop I do this steps: created a new ISE project added all of the .v files from XAPP495 added dvi_demo.ucf set ...
0
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1answer
518 views

Benefit of using RAM, or some form of internal memory on a FPGA

I am at moment trying to store an image onto an FPGA. I calculated the space required by it to be 19200 kb, and are therefor wondering whether i should store it some other way than a 2d array?.. Or ...
0
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1answer
1k views

How to give analog input from 3.5 mm jack to FPGA (Spartan 3e)

I am working on a voice transmission project by using Spartan 3e. My code works just fine. My problem is that I give analogue input to adc side by using a potentiometer and see the changes (as digital)...
0
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1answer
116 views

FIFO for spartan 3AN : no storage on board but ok in simulation

I made a FIFO using the Core Generator and I'm trying to implement a code that use it... 1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test) 2) By ...
0
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2answers
454 views

FPGA : program that doesn't work everytime

I'm making an ADC (in VHDL) for Spartan-3AN. Unfortunately I have to program my FPGA (program FPGA only) a random time before the programmable gain amplifier (Spartan 3AN User Guide page 73) works ...
1
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1answer
1k views

Clock Forwarding Won't Work

I am trying to forward a global clock signal to an output pin. I am using a Spartan SP601 evaluation board, LX16CSG324. Refer to the end of this segment of code. I am using a 2.5 V LVDS differential ...
1
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1answer
2k views

Spartan 6: How do I use my differential clock?

my SP601 Evaluation Board comes with one 2.5 V LVDS differential 200 MHz Oscillator. Until now, I have only been using the single-ended clock provided with the board. I am having trouble with how to ...
2
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1answer
1k views

VHDL 4-display counter on a Nexys 3 (0000 to 9999)

I'm triyng to implement a 4 display counter (0 to 9999) on a Nexys 3. However, when I load the bit file, all displays remain at 0. It seems like variables a,b,c,d; which control individual digits, ...
0
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1answer
332 views

PAR taking too long - Xilinx ISE

I am trying to compile a project and it takes a very long time to route. - ISE 14.3 In my main module, I am using a package where I have declared an array of constants. These constants use functions ...
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1answer
212 views

Why does iSim give a different result than hardware

I am working on a MIPS CPU for an FPGA - this is mostly a personal project to understand FPGA's. I have a 5 stage pipeline CPU implementation working correctly when run on iSim, however when I run it ...
0
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1answer
80 views

Map error in ISE caused by PLL

I'm working on a design using a Spartan6 FPGA, I recently made a change that added a PLL to the design to allow for faster clock speeds, however this caused a problem during the "map" command: ...
1
vote
1answer
678 views

How to remove the below error when doing FPGA implementation of program that use RAM using Xilinx block generator?

I wrote a code that use RAM (created by Xilinx block generator). It's size is 10X10 (total 100 data) . I used INSTANTIATION as below: ...
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0answers
85 views

Can't run 460800 baude rate on Nexys2

I have Nexys2 Spartan 3E board and I am running Ken Chapman's UART IP core, I need to transmit data to another device at a baude rate of 460800. I was successful in sending data at 115200 and 9600 ...
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1answer
322 views

interfacing spartan 3 fpga with arduino motor shield

I am doing a project on spartan 3 xc3s200 series. I have already programmed it to run a counter. I want to run a dc motor using the same fpga. And I have a motor driver -Ardiuno motor shield(L298P) ...
-1
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1answer
580 views

clocking on spartan6 FPGAs [duplicate]

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a divide-by-8 clock based on an ...
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2answers
7k views

Transmitting HDMI/DVI over an FPGA with no support for TMDS

I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS ...
1
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1answer
229 views

counter that MSB toggles every 2 seconds [duplicate]

I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that ...
2
votes
1answer
345 views

VHDL latch for Xilinx Spartan 3E

I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is ...
0
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1answer
1k views

Put a DAC at the output of FPGA

I have designed a circuit by System Generator to implement on FPGA. The output signal is a sinusoidal with changeable frequency. I need to read the output signal by oscilloscope. I should put a DAC at ...
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3answers
1k views

How to increase the number of inputs on Spartan 3E XCS5003, FG320 FPGA Kit [closed]

How can I interface extra switches or buttons for inputs to a Spartan 3E FPGA board? I am using a Spartan 3E XCS500E device in a FG320 package (speed -4). Original title and question: HOW TO ...
0
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1answer
342 views

defining base frequency, multiplier and divisor for dynamic clock manager

I am using a Spartan 6 xilinx FPGA, I managed to get it all working, changing the multiplier and divisor parameters at runtime. DCM_CLKGEN I use. My real oscillator is 66.6 MHz, but with PLL_BASE, I ...
2
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0answers
554 views

Spartan 6 configuration with Cypress FX2LP

I'm trying to load configuration to my FPGA board using Cypress FX2LP from USB. The basic implementation comes from Cypress's AN63620 application note, but instead Spartan 3 I use Spartan 6 (xc6slx4), ...
0
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1answer
305 views

Spartan 3AN FPGA DCM

While I use the internal clock for DCM clkin input I am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins. I changed from previous coding like this and ...
1
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2answers
456 views

Help needed with SPARTAN-3AN FPGA frequency doubler

Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked ...
3
votes
1answer
4k views

Why is my simple counter VHDL not working? Where did my signals go?

I'm a complete beginner with VHDL and an almost beginner with digital logic and I'm having a problem working through a book I'm reading. In particular, an exercise asks to build a counter with an ...
1
vote
2answers
976 views

FPGA Input Signal measurement

How to measure input pulse signal's frequency using xilinx toolkit on matlab? Since I'm bad at coding,I use System generator on matlab. I'm doing a project, In which I'll be using a Proximity sensor ...
10
votes
3answers
8k views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...
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votes
2answers
676 views

Trouble with expansion connector pins in spartan 3 fpga

I know how to turn on the fpga LEDS using push buttons and switches. I'm still having trouble figuring out how can I receive a signal from the buttons to the expansion connectors. Also, how should I ...
2
votes
1answer
1k views

Xilinx ISE Prevent Trimming For CPU

I am creating a custom CPU and would like it to be programmable on the fly instead of hard coded in VHDL. The issue I am having is that without initial code for the CPU to run, ISE will trim large ...
5
votes
3answers
8k views

What is the meaning of speed grade marking on Xilinx FPGAs?

According to Xilinx FPGA product datasheets, the numbers on the 5th line as 4C or 5I stand for speed grade and temperature.I have a XC3S400 with 4C speed grade (4= standard speed, 5= High performance)....
2
votes
2answers
1k views

Why my FPGA programs does not work?

I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work. EDITION1: ...
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0answers
567 views

What is Xilinx FPGA XC3S2000 gate count and speed?

I am trying to start learning FPGA programming and want to start with XC3S2000 (Spartan III). In table 1 , I see 2M gate count which is much higher than more advanced Spartans and could not find its ...
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1answer
2k views

Problem with warnings in Xilinx tools [closed]

I am interfacing a VGA monitor with Spartan 3e kit. I have a problem in the code and I'm getting many warnings, as shown below. Could anyone explain the warnings? ...
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3answers
2k views

Does spartan 6 XC6SLX9 FPGA have an internal oscillator ? .If so how to access that?

I am new to this FPGA. can any one help with the following : Does Spartan 6 XC6SLX9 have an internal oscillator ?. If so what are its specifications ? , how can i access that ? . Please share any ...