Questions tagged [spartan-3]
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50 views
Why the resource overhead of a design with new functionality (extra logic) is different on different xilinx fpga devices?
I have designed two circuits with VHDL and synthesized them with Xilinx ISE design suite. The first circuit is a controller (autopilot) and the second circuit is the same controller with extra ...
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2answers
67 views
NOT Gate implementation BASYS Spartan 3E [closed]
this is my first post here. I am new to FPGAs. I would like to implement a NOT gate on the BASYS (Spartan3E-100) FPGA. I've been looking at the tutorial HERE to work my way towards a synthesis. I wish ...
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1answer
87 views
Unknown problem with I2C on Spartan 3-E {VERILOG}
I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...
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1answer
460 views
VHDL: signal doesnt keep a value
hi first of all english is not my languaje.
im using a SPARTAN 3E as develop board
i tried to make a FSM that changes
the state with a counter called "T" (somethig like a pseudo-processor) and use ...
0
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1answer
114 views
How do I reset my registers on Digital Clock Manager output?
I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT.
The reset logic I'm using is shown here.
...
0
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1answer
429 views
Clock Implementation Design Warning on Spartan 3E
I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager.
These are my UCF ...
0
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1answer
265 views
Video Display Buffer-VGA Port Interfacing
I am trying to get a basic understanding of how VGA port interfacing works.I have started reading SPARTAN 3 VGA Port Interface. I get the function of horizontal and vertical syncs, and the subsequent ...
0
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2answers
829 views
BASYS2 - Verilog: how to properly edit ucf file?
I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some
trouble with FPGA. Actually, not with FPGA ...
2
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1answer
72 views
Trouble running picoblaze code
I am running a simple picoblaze code where I am using two addresses and sending a high strobe on both the addresses, the assembly code has no loop, so technically my code should run ONLY once but the ...
2
votes
1answer
1k views
Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?
I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...
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0answers
739 views
Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?
I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
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1answer
2k views
VHDL SPI xilinx spartan 3E
I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher.
I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...
