Newest 'spartan-3' Questions

-5

votes

1answer

40 views

Spartan 3E FPGA Counting Problem [duplicate]

I am using Spartan 3E FPGA where the clock rate is 50MHz. I tried to make 1-sec blinking LED program but LED is in a constantly turned-off state. As the counter1 is increasing on every positive clock ...

digital-logic verilog spartan-3

asked 10 hours ago

Dipnarayan Das

295 bronze badges

-2

votes

1answer

97 views

Counter in FPGA not counting properly how expected [closed]

I am using Spartan 3E FPGA where the clock rate is 50MHz. I tried to make 1-sec blinking LED program but LED is in a constantly turned off state. ...

digital-logic fpga verilog spartan-3

asked yesterday

Dipnarayan Das

295 bronze badges

-2

votes

1answer

61 views

How to change status of pin in Spartan 3E FPGA

Verilog Code: ...

fpga verilog xilinx spartan-3

asked May 15 at 12:07

Dipnarayan Das

295 bronze badges

-1

votes

2answers

73 views

NOT Gate implementation BASYS Spartan 3E [closed]

this is my first post here. I am new to FPGAs. I would like to implement a NOT gate on the BASYS (Spartan3E-100) FPGA. I've been looking at the tutorial HERE to work my way towards a synthesis. I wish ...

digital-logic fpga verilog spartan-3

asked Apr 8 '17 at 0:34

Antillar Maximus

992 bronze badges

0

votes

1answer

132 views

Unknown problem with I2C on Spartan 3-E {VERILOG}

I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...

verilog i2c xilinx spartan spartan-3

asked Mar 5 '17 at 15:50

Ahmed Ali Abbasi

276 bronze badges

0

votes

1answer

710 views

VHDL: signal doesnt keep a value

hi first of all english is not my languaje. im using a SPARTAN 3E as develop board i tried to make a FSM that changes the state with a counter called "T" (somethig like a pseudo-processor) and use ...

fpga vhdl xilinx spartan-3

asked Dec 10 '16 at 20:36

menymp

1

vote

1answer

171 views

How do I reset my registers on Digital Clock Manager output?

I am using a SPARTAN 3E and have used the DCM core to generate a 50 Mhz to 25 Mhz clock to drive the VGA PORT. The reset logic I'm using is shown here. ...

fpga xilinx spartan spartan-3

asked Nov 19 '16 at 16:31

Ahmed Ali Abbasi

276 bronze badges

0

votes

1answer

506 views

Clock Implementation Design Warning on Spartan 3E

I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager. These are my UCF ...

fpga clock xilinx spartan spartan-3

asked Nov 6 '16 at 12:59

Ahmed Ali Abbasi

276 bronze badges

0

votes

1answer

352 views

Video Display Buffer-VGA Port Interfacing

I am trying to get a basic understanding of how VGA port interfacing works.I have started reading SPARTAN 3 VGA Port Interface. I get the function of horizontal and vertical syncs, and the subsequent ...

fpga verilog vga spartan-3

asked Oct 16 '16 at 5:55

FechP

11

0

votes

2answers

976 views

BASYS2 - Verilog: how to properly edit ucf file?

I am a newbie at FPGA. I bought BASYS2 digilent board(Spartan3E). I have background on microcontrollers. C/C++ is no problem for me. But I am having some trouble with FPGA. Actually, not with FPGA ...

fpga verilog xilinx spartan-3

asked Dec 25 '15 at 10:13

Alper91

1,15017 silver badges40 bronze badges

2

votes

1answer

77 views

Trouble running picoblaze code

I am running a simple picoblaze code where I am using two addresses and sending a high strobe on both the addresses, the assembly code has no loop, so technically my code should run ONLY once but the ...

fpga vhdl picoblaze spartan-3

asked Aug 15 '15 at 7:12

alexhilton

5191 gold badge8 silver badges16 bronze badges

2

votes

1answer

2k views

Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...

fpga xilinx timing-analysis spartan-3

asked Jul 12 '15 at 23:47

nanofarad

6,7882 gold badges22 silver badges44 bronze badges

1

vote

0answers

813 views

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...

fpga clock xilinx spartan-3

asked Jul 9 '15 at 13:58

nanofarad

6,7882 gold badges22 silver badges44 bronze badges

1

vote

1answer

2k views

VHDL SPI xilinx spartan 3E

I have nearly non previous experience with VHDL and the most of the code here is given to me by the teacher. I'm trying to communicate with a ADXL362 accelerometer using SPI on a Xilinx Sparten 3E. ...

fpga vhdl spi xilinx spartan-3

asked May 22 '15 at 9:32

Runsiv

112 bronze badges

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Questions tagged [spartan-3]

Spartan 3E FPGA Counting Problem [duplicate]

Counter in FPGA not counting properly how expected [closed]

How to change status of pin in Spartan 3E FPGA

NOT Gate implementation BASYS Spartan 3E [closed]

Unknown problem with I2C on Spartan 3-E {VERILOG}

VHDL: signal doesnt keep a value

How do I reset my registers on Digital Clock Manager output?

Clock Implementation Design Warning on Spartan 3E

Video Display Buffer-VGA Port Interfacing

BASYS2 - Verilog: how to properly edit ucf file?

Trouble running picoblaze code

Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

VHDL SPI xilinx spartan 3E

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