Questions tagged [spartan-6]

Spartan-6 FPGA Family by Xilinx

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VHDL code works in simulation but not in hardware

I have a SAKURA-G board, I'm trying to program the main FPGA which is a SPARTAN-6 XC6SLX75 CSG484BIV1841, I'm using Xilinx ISE 14.7. My project files all compile fine and when I simulate the ...
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How to use clock on Spartan-6

I have a SAKURA-G board, I'm trying to program the main FPGA which is a SPARTAN-6 XC6SLX75 CSG484BIV1841. I figured out the issue is that I'm not getting clock so I'm trying to get something simple to ...
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2answers
79 views

Driving a wire from a 1-bit reg from one bit of 8-bit reg (verilog)

I have wasted far too much time on this. So here goes. Started off coding up a basic SPI slave device, to work with a Raspberry Pi as SPI master. Using a Xilinx XC6SLX16 as the slave. Using a logic ...
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1answer
101 views

Xilinx Spartan 6 speed sabotage? [closed]

I'm trying to use Spartan 6 fpgas at the speeds they purport to support in their datasheets. However, when I try to make a bit file, I get a message saying my design is "not supported". It compiles ...
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1answer
143 views

PIO communication in PCIE

I want to communicate with SPARTAN 6 FPGA through PCIE for data transfer using Programmed IO (PIO) method.I am confused with following questions. 1)What is the role of BAR reg in PIO design(while ...
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1answer
133 views

Verilog Case Statement evaluating all combinations of a 10-bit ADC sample

I have a (hopefully) pretty easy question on case statements. If I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a ...
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2answers
564 views

Unable to figure out VGA [Verilog]

After doing plenty of research on how to generate VGA signals and looking at a few code examples, I attempted to write my a simple VGA signal generator that just displays a single solid color on the ...
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1answer
156 views

Assigning specific bits of vector to outputs in verilog ucf

When I set up my module, I have code like input signed [7:0] SIGNAL but in the UCF I want to assign each bit individually. Currently my code in the UCF looks ...
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2answers
771 views

What is the relationship between a 10:5 Gearbox and a 5:1 OSERDES2?

I'm trying to understand the HDMI implementation in Xilinx application note XAPP495. In especially, I don't understand the diagram below where there are connections between gearboxes and oserdes2. ...
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1answer
570 views

different approaches to implementing program counter

I want to implement the following 32 bit program counter circuit: and this is my current verilog code: ...
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2answers
425 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
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2answers
349 views

Spartan-6 input data: Use data pins or GCLK?

I am designing a PCB which connects to a Spartan-6 via a connector (Opal Kelly XEM board). The PCB hosts some analog components which will communicate with the FPGA (ADCs, DACs). The FPGA board itself ...
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1answer
186 views

Spartan 6 and flash memory data transferring

I have an spartan 6 board. I need a flash memory with USB interface(like transcend, Silicon power,... ) to save some data to my board user. I haven't any idea about transfer speed. I need about 13 ...
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1answer
1k views

Spartan 6 bidirectional pins how to use

Is it possible to use pins of Spartan-6 bidirectional. (switch between input/output) The following is the situation: I have a high speed ADC and DAC, but this do not have to opperate at the same time....
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3answers
1k views

Xilinx XST won't infer block ram

I'm having trouble getting the design of my FPGA 80's computer to fit on a Papilio Duo board which is a Spartan 6 - xcs6slx9. The problem stems from RAM being inferred as distributed instead of block....
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1answer
379 views

Spartan 6 Internal Memory [closed]

I am referring to below datasheet of IC XC6SLX45-L1FGG484C-ND. As per Digikey portal, it has Total RAM Bits = 2138112 If I want use internal RAM memory is there any specific pins associated with ...
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1answer
489 views

Erratic behaviour in FPGA based I2s loopback (Verilog + Spartan6)

I am working on a personal project involving a Xilinx Spartan6 FPGA that I program in Verilog. I am not an advanced user, it's my 3rd reasonably sized project and I don't really rub shoulder with FPGA ...
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1answer
242 views

Xilinx PCIe Integrated Endpoint - Using the other transceiver on the tile

This question is specifically about the Spartan 6-75LXT (FG676) but can be applied to any Spartan 6 (and possibly other Xilinx parts as well). When using the GTP wizard by itself, there are 2 pairs ...
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1answer
240 views

Safe I/O voltage levels for Xilinx SP605

Context I recently got an SP605 Evaluation board from Xilinx, that sports a Spartan-6 FPGA. (check out this link). This board has a bunch of User I/O and the two I'm most interested right are the ...
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1answer
464 views

18bit Serdes - Xilinx Spartan6

In a project with FPGA stereo vision I use two MT9V032 cameras. The cameras are connected as in the application example in the data sheet. In stereo output mode the data length is 18bits long. There ...
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1answer
272 views

HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7

I'm working on XAPP495 on Digilent Atlys board with ISE 14.7 I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
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1answer
241 views

Problem with implementation XAPP495 [closed]

I'm working on XAPP495 to show a signal which is throughput of a HDMI signal from my Laptop I do this steps: created a new ISE project added all of the .v files from XAPP495 added dvi_demo.ucf set ...
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1answer
70 views

Help with multiple receiver channels and single storage architecture

I want to build a datalogger that has multiple receiver channels that run on serial communication protocol RS232 and then collect the information from the channels in a single storage that would be ...
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1answer
1k views

Xilinx clocking wizard - How to connect clkfb_in and clkfb_out

I created a VHDL design which needs a 50 MHz clock input. The Spartan-6 I'm working on gives me a 100 MHz clock signal, so I used the Xilinx Clocking Wizard to get a 50 MHz clock. When I choose "No ...
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1answer
191 views

Slow clk output (Spartan-6)

I have a design which looks like this: ...
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1answer
1k views

IP Core Generator fails with Error

I'm working on a project using a Spartan-6. I created a FIFO with the IP Core Generator (New Source -> IP Core -> FIFO -> Generate). The LOG looks like this ...
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2answers
665 views

Problem with connecting clock divider generated by CORE Generator to I2S design for Spartan 6

I'm trying to connect clock divider generated by CORE Generator to I2S receiver and I2S transmitter on Spartan 6. The PLL_BASE is connected via ODDR2 module, as adviced. Both receiver and transmitter ...
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2answers
1k views

Can not keep pin LOW during FPGA configuration

I would like to have a control signal that stays low all the time and goes hi only when I tell it to. Initializing the pin in the entity does not seem to set the value to zero (xc6slx25-3ftg256): <...
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3answers
431 views

Power supply for FPGA

I have a Spartan 6 FPGA (XC6SLX9-2TQG144) and I'm designing a power supply for it. Let's assume that I will utilize all of its logic (very possible) and I want to clock it as fast as possible (around ...
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2answers
851 views

Spartan-6 LVCMOS33 input pin: can it take 5V without damage?

My Spartan-6 device has an input pin with IOSTANDARD = LVCOMS33 as constraint. If I accidentally or otherwise connect it to a 5 V signal, will the FPGA get damaged? ...
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2answers
3k views

FPGA - Data transfer via Ethernet

I have a Verilog module that is able to make my FPGA blink its LEDs at frequencies according to certain variables/constants I've set within the code. However, I would like to change these variables ...
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3answers
587 views

Having trouble implementing a 1Hz blinking light on a Spartan 6 FPGA

I currently have a Spartan-6 FPGA in a Digilent Nexus 3 board. I am using Xilinx 14.6 Project Navigator to write the code and program the FPGA. My code for the top (and only) module is the following: ...
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1answer
118 views

PlanAhead 14.7 multiple runs issues

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic ...
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1answer
177 views

What could be the usage of material declaration datasheet for Spartan-6 package?

I'm starting to work with FPGAs and CPLDs. like other professional EEs when I bought a Spartan-6 board, started to search in the website of manufacture (that was Xilinx) to find everything about my ...
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1answer
349 views

Poor clock output from Spartan6 FPGA

I am using the LX9 Microboard from AVNET with the Spartan 6 PFPGA. I implement SPI to read from an ADC (ADS7822). I was getting wrong sampled values. When I ched the signals with an oscilloscope, it ...
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1answer
703 views

Xilinx bitgen warning

I am getting a warning in bitgen like: This design is using one or more 9k block RAMs(RAMB8BWER). 9k block RAM data, both user defined and default requires a special bit format. Is it a critical ...
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2answers
2k views

VHDL Block RAM Inference

I am storing a 16k constant sine table of 14 bit signed vectors in a package. I use this package in my module to read out the array in a clocked process But I get this warning during synthesis and ...
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3answers
77 views

VHDL synthesis doubt

Does the synthesis tool consider an initial value of a signal given before begin of the architecture. What happens when this value is not a constant but another signal. is it better to provide initial ...
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1answer
124 views

Pressure Sensor Calibration

Here's the situation: I need to verify the pressure sensor accuracy of a control board. I have a software to verify the pressure and I am using Ethernet Communication to communicate between my control ...
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1answer
720 views

frequency doubler on fpga

is it in general possible to implement a frequency doubler completely on FPGA? I saw some implementations on google by delaying the input and XORing it with the original. But they also say that this ...
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3answers
2k views

Spartan 6 DCM unstable clock output

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input ...
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2answers
1k views

Text File tranfer between PC and Atlys board (FPGA)

I am new to FPGA. While doing calculations I found that I can not input number in real time to FPGA. My instructor told me to write my numbers (or data) in a text file on PC and tranfer it to FPGA in ...