Questions tagged [sram]
Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.
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Designing a 4-bit SRAM using rising edge D-flip flop [closed]
From what I understood about the SRAM, D latches can be used as an memory cell since it behaves like a shift register. From there I thought about using D latch to read/write into the memory. Even ...
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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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9T SRAM Circuit Supporting 1-bit Multiplication
I was reading a paper that added a 3T NAND gate, consisting of two NMOS and one PMOS, to the regular 6T SRAM, achieving 1-bit multiplication. However, I'm struggling to understand how the NAND part of ...
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How do I fix UUU output from modelsim testbench?
I am designing static Ram to be used with an add/sub on Quartus. I have created a block diagram and generated VHDL code. My schematic is correct but modelsim keeps giving me UUU for the output of my ...
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ATmega8515 - odd results when auto-detecting external SRAM
I'm using an ATmega8515 microcontroller for a one-off hobby project. This chip has an external memory interface which can directly address 64 kilobytes of external SRAM.
ATmega8515 datasheet.
For my ...
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Why do STM32 MCUs divide RAM into SRAM1 and SRAM2?
Why do STM32 MCUs divide RAM into SRAM1 and SRAM2? They seem contiguous, so that I could simply configure my linker to treat both as just one chunk of RAM.
Should I do that? If not, how do I tell the ...
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STM32 - update firmware from data stored in SRAM
I would like to remotely update the firmware of my STM32WLE5 device. I can transfer the new binary file from the server to the STM's SRAM using my custom link only, which means I cannot utilize other ...
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Is it possible to reset SRAM in one cycle?
If you have some SRAM in an ASIC and you want to reset it to 0 quickly, rather than looping over the entire memory can you just write to all words in parallel by asserting all word lines at once (this ...
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Why are the challenges in using SRAM over DRAM for main memory?
Historically, when compared to DRAM (dynamic ram), SRAM (static ram) is more expensive with a lower density, but it's much faster and more efficient. As a result, SRAM is reserved for devices, such as ...
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Given a conventional 6t sram in cadence, how do I measure the power and delay parameters?
I am required to simulate and analyze the 6t SRAM using Cadence
Virtuoso software. However, I am confused about how the measurements will be taken. For calculating SNM, I would have to consider the ...
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How to calculate ADDSET and DATAST according to SRAM timing graph?
I use FSMC in STM32F407 to access external SRAM IS62WV51216. I read RM0090 and AN2784, gives me two fomula
tSU and tV mean
here is the SRAM reading timing graph
here is write timing graph
1.why WE ...
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E-Ink with Atmega and avr-libc
I am trying to understand how to drive an E-Ink display like the Adafruit 4196 with i.e. an Atmega328 with avr-libc.
From what I could learn so far, I would write the image/text to a frame buffer and ...
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Bitline is not working correctly (6t cell sram with sense amp and precharge)
After simulating 6t ram with sense amplifier and precharge, bit line value is fixed to 1.5v. How can i avoid this? Using pspice to simulate.
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Atmel Studio: Compiler error when adding external SRAM
I have board wired up to use ATMega1281's Eternal Memory Interface with a BSI, BS62LV4006STIP55, 512Kx8 SDRAM connected. I am trying to do something similar to this (ATMega128), except my memory is ...
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Is there any reference to design a 4*4 bit ram only using transistors
I'm currently doing a project and would like some help. I need to create a 4-bit 4-word RAM using PSPICE. (I'm both new to the PSPICE program and new to the topic of RAM)
I currently have successfully ...
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Clarification about Memory Address
I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, ...
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Problem with writing to 16-bit external SRAM from STM32 MCU
I have an STM32H743 Nucleo board, accessing an external 16-bit SRAM memory chip using the Flexible Memory Controller (FMC).
8 and 16-bit writes return the same values when reading them back. However, ...
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IC power supply backup
I'm using this ic
The datasheet for the 23LVC1024 SRAM specifies a minimum supply voltage of 2.5V. I want to use a power supply set at 2.5V, but with tolerance that could be less than that, say down ...
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How to write to a Hitachi HM628128A SRAM?
I'm working with a Hitachi HM628128A SRAM chip.
According with the datasheet, the function table is
How do I write data in the chip? Must I execute "write cycle (1)" and then "write ...
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How is a bistable element formed with two inverters and two transistors in a 6T SRAM cell?
I'm trying to figure out how a charge can be stored between two CMOS inverters and two more transistors.
I understand how the inverter works, just with a NMOS and PMOS base connected to a common ...
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Microcontroller, Flash EPROM and RAM combination questions
I have chosen a specific microcontroller (MCU) for a project, based on price, package size, and speed. It's the NXP LPC1768FBD100, a 100 MHz ARM-based MCU with 512 KB program memory and 64 KB SRAM.
My ...
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Should I tie unused I/O of static RAM CY62256N to ground?
I'm designing a 4-bit TTL computer and I want to use the CY62256N for system RAM.
As you see, the computer is a 4-bit computer which means the main data bus is only 4 bits wide. The CY62256N is an 8 ...
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Giving write enable signal externally by DIP switch to FPGA memory
I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches.
Verilog input wire has been declared in the simple memory read write which connects to ...
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Replacing CMOS SRAM with NV SRAM
I have an electronic board from a professional video device containing a 256K 8bit CMOS SRAM 28 pin DIP. I wish to replace this memory with a Nonvolatile 256K 8bit RAM 28 pin DIP, so that I can read ...
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Why does this SRAM chip have more physical bits than declared by the manufacturer?
I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.)
The manufacturer clearly identifies this chip as 256Kbit.
Reading through the datasheet it clearly ...
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Voltage on battery-backed SRAM somehow higher than both battery and regulated supply
I'm using an AS6C1008 SRAM chip, and I'm having an odd issue with it. The voltage supply going to this chip is created from a stiff 5V supply (VDD) and a 3V backup battery (CR2032), diode or-ed ...
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Can I replace an SRAM chip with a faster one?
I need to replace an SRAM chip with an access time of 25ns (AS7C256-25JC). How important is the access time? Can I replace it with one with a lower access time, such as the AS7C256A-20JC at 20ns, or ...
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Can I repair CY62256 with UT62256
The CY62256-55PC(SRAM) in my old computer is broken and I need a replacement for it but I can't find the same chip. The only one similar enough in my local store is UT62256CPC-70LL, HM62256ALP-12 and ...
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STM32 Swap Flash Banks. Purpose
I was casually reading STM32 documentation and other materials out of self-education and self-development purposes and ran into bank swapping in system configuration (in referencep and/or programming ...
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6T SRAM cell write operation not working as expected in virtuoso
I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and ...
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Externally triggered high impedance toggle for large number of parallel lines
First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.
I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
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Testing 16K SRAM in TL866 II Plus?
I have a GoldStar GM76C28A-10 16K (2048 x 8) SRAM DIP chip that I want to test in my TL866 II Plus. I don't see this chip in the list of known chips in the Xgpro v11.60 software and none of the "...
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Question about linker script for STM32L4R5ZI with 3 RAM partitions
For my application I need 305Kbytes of RAM for the variables.
According to Reference manual for the chip I am using - STM32L4R5ZI:
"The STM32L4Rxxx and STM32L4Sxxx devices feature up to 640 ...
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What is a post decoder?
I have heard a bit about pre decoders and post decoders recently in circuit design. When I saw the circuits, the pre decoder is same as the normal decoder in every textbook or website. But I haven't ...
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DIP alternative to dual-port SRAM that doesn't require obsolete chips?
I have a microcontroller "A" and 8-bit game console "B" that I'd like to be able to share a 2Kx8 SRAM address space. "A" will only write to RAM, and "B" will ...
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Is it possible to use "DDR Xccella Mode" when connecting an external RAM to the STM32?
MCU: STM32H7A3ZIT6
RAM: APS12808L-3OBMx
This ram supports "DDR Xccela mode", where it transfers data on the rising and falling edge of the clock.
I'm fairly sure my MCU supports the standard ...
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How much memory does the 23LC1024 have?
The Microchip 23LC1024 chip is said to have 1Mbit of memory. Looking at Wikipedia, it says that a Mbit is 10^6 bits. Is that so? I mean, is this decimal Mbit? It doesn't seem reasonable to me..
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RT 1020 board uses 64K "SRAM_DTC" to store .bss data, my application requires more
I am trying to port my application to an NXP (RT 1020) board.
I understand that this board doesn't have internal flash, and therefore runs from SRAM. It uses "SRAM_DTC" (tightly coupled data)...
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SRAM output voltage with 74HC chips
I am attempting to connect a CMOS parallel SRAM chip to a few different 74HC chips, but mostly 74HC377 octal flip-flops.
I'm having inconsistent results with values being loaded sometimes not being ...
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Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
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STM32H743 FMC with ST7789 doesn't work without delay
I have an STM32H743 connected to a screen that uses ST7789 via FMC (i.e. parallel connection) using 8-bit bandwidth and A18 to select between command and data.
The current code has an issue that the ...
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Using a binary counter with ic sram
I am using the as6c62256 ic sram, this is the datasheet: datasheet
I am trying to write 1000 words of 8 bit, and then read them from the sram
is it possible to connect a binary counter to the adress ...
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How dense is SRAM compared to random logic?
Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit.
That having been said, the ...
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Replacing Dallas NVRAM with larger capacity variant?
This DS1225AB-200 (8k x 8 = 64kB NVSRAM) is from 1995 and is probably dead (cannot measure from the outside.) The only close replacement in stock is a DS1230AB-100 (32k x 8 = 256kB.)
Looking at the ...
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Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
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Write ADC data to memory and back to DAC (without MCU)
Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller?
The application is to implement the audio loop of some sort,...
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Finding NM by writing formula in HSPICE
I want to calculate write, hold, and read the static noise margin of an SRAM block (WSNM, HSNM, and RSNM).
In order to do so, I want to write a command to do it, so I need to find the input voltage ...
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16-bit Byte-Addressable RAM Interface
I am a beginner to computer engineering and electrical engineering, and I have watched the entirety of Ben Eater's 8 bit breadboard computer series so I decided that because I understood that well, ...
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Fastest possible memory copy between 2 12ns SRAM DIP chips
Electronics newbie here...
I'm trying to build a retrocomputer, and learn digital electronics along the way. I decided to begin with the video generation part, with a fast memory copier, independent ...
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Are there tips and tricks for SOM for place power pin and reduce PCB layers?
I'm developing a SOM with microcontroller, SDRAM and flash.
Following the documentation that I found on the web and that made available by the component manufacturers (such as this: STM32MP1 Series ...
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