Questions tagged [sram]

Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.

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Why does this SRAM chip have more physical bits than declared by the manufacturer?

I noticed while scanning the datasheet for a 23K256 SRAM chip that it has 32768 bytes (+262Kbit.) The manufacturer clearly identifies this chip as 256Kbit. Reading through the datasheet it clearly ...
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5 votes
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Voltage on battery-backed SRAM somehow higher than both battery and regulated supply

I'm using an AS6C1008 SRAM chip, and I'm having an odd issue with it. The voltage supply going to this chip is created from a stiff 5V supply (VDD) and a 3V backup battery (CR2032), diode or-ed ...
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Can I replace an SRAM chip with a faster one?

I need to replace an SRAM chip with an access time of 25ns (AS7C256-25JC). How important is the access time? Can I replace it with one with a lower access time, such as the AS7C256A-20JC at 20ns, or ...
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1 vote
1 answer
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Can I repair CY62256 with UT62256

The CY62256-55PC(SRAM) in my old computer is broken and I need a replacement for it but I can't find the same chip. The only one similar enough in my local store is UT62256CPC-70LL, HM62256ALP-12 and ...
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0 votes
1 answer
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STM32 Swap Flash Banks. Purpose

I was casually reading STM32 documentation and other materials out of self-education and self-development purposes and ran into bank swapping in system configuration (in referencep and/or programming ...
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6T SRAM cell write operation not working as expected in virtuoso

I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and ...
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Externally triggered high impedance toggle for large number of parallel lines

First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty. I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
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Testing 16K SRAM in TL866 II Plus?

I have a GoldStar GM76C28A-10 16K (2048 x 8) SRAM DIP chip that I want to test in my TL866 II Plus. I don't see this chip in the list of known chips in the Xgpro v11.60 software and none of the "...
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2 votes
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Question about linker script for STM32L4R5ZI with 3 RAM partitions

For my application I need 305Kbytes of RAM for the variables. According to Reference manual for the chip I am using - STM32L4R5ZI: "The STM32L4Rxxx and STM32L4Sxxx devices feature up to 640 ...
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What is a post decoder?

I have heard a bit about pre decoders and post decoders recently in circuit design. When I saw the circuits, the pre decoder is same as the normal decoder in every textbook or website. But I haven't ...
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1 vote
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DIP alternative to dual-port SRAM that doesn't require obsolete chips?

I have a microcontroller "A" and 8-bit game console "B" that I'd like to be able to share a 2Kx8 SRAM address space. "A" will only write to RAM, and "B" will ...
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1 vote
1 answer
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Is it possible to use "DDR Xccella Mode" when connecting an external RAM to the STM32?

MCU: STM32H7A3ZIT6 RAM: APS12808L-3OBMx This ram supports "DDR Xccela mode", where it transfers data on the rising and falling edge of the clock. I'm fairly sure my MCU supports the standard ...
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NXP RT 1020 - How to take full advantage of ITC, DTC, OC SRAM?

I am trying to wrap my head around the nxp rt 1020 SRAM memory configuration, but having a hard time understanding it. What I have understood so far, is the their imx RT 4 digit chips all use the same ...
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How much memory does the 23LC1024 have?

The Microchip 23LC1024 chip is said to have 1Mbit of memory. Looking at Wikipedia, it says that a Mbit is 10^6 bits. Is that so? I mean, is this decimal Mbit? It doesn't seem reasonable to me..
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RT 1020 board uses 64K "SRAM_DTC" to store .bss data, my application requires more

I am trying to port my application to an NXP (RT 1020) board. I understand that this board doesn't have internal flash, and therefore runs from SRAM. It uses "SRAM_DTC" (tightly coupled data)...
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Label information of SRAM chips

I have purchased an SRAM chip for my project (part-number: IDT71V416L15PH) and found a code string on the chip label (see the attached image). Now, I am a little curious about this code. Does this ...
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SRAM output voltage with 74HC chips

I am attempting to connect a CMOS parallel SRAM chip to a few different 74HC chips, but mostly 74HC377 octal flip-flops. I'm having inconsistent results with values being loaded sometimes not being ...
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Do SRAM Macros register the inputs?

In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file). My question is this: SRAMs ...
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STM32H743 FMC with ST7789 doesn't work without delay

I have an STM32H743 connected to a screen that uses ST7789 via FMC (i.e. parallel connection) using 8-bit bandwidth and A18 to select between command and data. The current code has an issue that the ...
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Using a binary counter with ic sram

I am using the as6c62256 ic sram, this is the datasheet: datasheet I am trying to write 1000 words of 8 bit, and then read them from the sram is it possible to connect a binary counter to the adress ...
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How dense is SRAM compared to random logic?

Modern CPUs always have some on-chip cache, typically more than one level. This takes a lot of die area; static RAM is generally reckoned at six transistors per bit. That having been said, the ...
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2 votes
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Replacing Dallas NVRAM with larger capacity variant?

This DS1225AB-200 (8k x 8 = 64kB NVSRAM) is from 1995 and is probably dead (cannot measure from the outside.) The only close replacement in stock is a DS1230AB-100 (32k x 8 = 256kB.) Looking at the ...
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pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
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Write ADC data to memory and back to DAC (without MCU)

Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller? The application is to implement the audio loop of some sort,...
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finding NM by writing formulla in hspice

I want to calculate Write, hold, and read static noise margin of an SRAM block(WSNM, HSNM, and RSNM). but in order to do so, I want to write a command to do it, so I need to find input voltage when ...
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3 votes
3 answers
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16-bit Byte-Addressable RAM Interface

I am a beginner to computer engineering and electrical engineering, and I have watched the entirety of Ben Eater's 8 bit breadboard computer series so I decided that because I understood that well, ...
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1 vote
2 answers
269 views

Fastest possible memory copy between 2 12ns SRAM DIP chips

Electronics newbie here... I'm trying to build a retrocomputer, and learn digital electronics along the way. I decided to begin with the video generation part, with a fast memory copier, independent ...
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1 answer
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Are there tips and tricks for SOM for place power pin and reduce PCB layers?

I'm developing a SOM with microcontroller, SDRAM and flash. Following the documentation that I found on the web and that made available by the component manufacturers (such as this: STM32MP1 Series ...
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Creating a memory mapping to peripheral memory on STM boards

I am trying to find a way to load/execute code that is stored on an external SRAM chip without having to load it to the microcontroller internal memory. I'm not 100% sure of the name for what I'm ...
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1 vote
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OV7670 camera, how to use external SPI SRAM?

I'm using OV7670 camera with no FIFO and Arduino Mega2560 and I want to send 76800 bytes to my laptop, because of Arduino RAM limitations, I'm planning to use Serial SRAM 23LC1024 (1Mbit) so I can ...
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1 vote
1 answer
214 views

dual-port parallel-to-serial SRAM?

I wanna interface an old Motorola 68000-based system with an ESP32, and I was thinking of doing that through SRAM. However I can't seem to find any SRAM that I could put between them. What other ...
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SRAM and D-flip flop instead of transistor

I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit. But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It ...
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0 votes
3 answers
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Buffer exceeding ramsize do not produce error in avr-gcc

In my source code I have tried to allocate a huge buffer exceeding the RAMSIZE value (RAM of my component (ATmega324PB) is 2k). ...
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Terminating bidirectional data lines and clock for memory-mapped devices

I am wiring up an STM32H743 to an SRAM or an FPGA to memory map it (i.e. I would like to be able to re-use the schematic). This SRAM operates at a maximum of 50MHz. The FPGA can operate at 50MHz all ...
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2 answers
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SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?

What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits? Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
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3 votes
3 answers
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Does SRAM need PCB track length/impedance matching

Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff. I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit ...
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4 votes
2 answers
326 views

How to get the memory state of SRAM on power up?

I am working on IoT authentication using a physically uncloneable function (PUF). I have read several articles which suggest that SRAM PUF can be used for that purpose. However, I want to know how can ...
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Why did they make the 74x170 (670) register file asychronous, no CLK input?

I am designing a retro computer as a project to learn digital electronics hands-on (not FPGA programming). I currently have an accumulator machine similar to the PDP-8 where the ALU has the ...
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0 votes
3 answers
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External Memory IC which increments data on a clock pin

I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following: Store 1MB of data of 16-bit data This data is stored at specific ...
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Looking for a display RAM for my VGA card [closed]

I´m designing a simple 800x600 pixel VGA card, based on this example (but I don´t reduce the image size). I also want to use a display RAM, so a microprocessor can write a new image. For this I need ...
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SRAM Chip. Entering the data either manually through DIP Swithces or from the bus

I'm building a 8-bit "computer" on the breadboard mostly following tutorials from different sources. The project is educational, so I want to be able to execute all the steps manually and see what is ...
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0 votes
3 answers
412 views

Async SRAM Chip. Write Cycle. Data inputs timings

I'm working on my home project of building the 8-bit computer and now I'm on the RAM building stage. I'm going to use this chip for as my RAM UTRON UT62256C (datasheet). This chip is to be connected ...
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1 vote
2 answers
232 views

Adapting an I2C FRAM chip to an SRAM-like parallel interface

I have a project that requires a parallel interface non-volatile RAM. I had hoped to use an FRAM, however the only parallel FRAMs seem to much larger in capacity (and more importantly, price) than I ...
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If the Sense Amplifiers structure is the same as an SRAM cell's, why the differential voltage on the bit line gets amplified?

source How you can see the structure with 6 transistors of a Sense Amplifier (SA) is the same as a SRAM cell, but this latter causes a little variation on the bitline voltage that the SA will amplify....
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1 answer
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External bus interfacing

This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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2 answers
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Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...
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1 answer
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How do I produce WE in this diagram?

I have designed a memory system that has 10KB ROM followed by 6KB of RAM. The ROM begins at 0000H. I had to use two 4K x 8bit ROMs and one 2K x 8 bit ROM. I also have to use one 2K x 8bit RAM and a 4K ...
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1 vote
1 answer
636 views

SRAM-Logic Block Diagram

I am a beginner and I am trying to understand the block diagram of a Static RAM. I want to draw a "256x4 bit SRAM" block diagram. According to some information I collected from the internet I managed ...
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2 answers
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Interfacing 16-bit SRAM/MRAM with Arduino Mega

I a looking to interface a MR2A16A 4Mb 16-bit MRAM with an Arduino Mega. I am new to interfacing with memory chips and would like some advice from someone more experienced than myself. I am not ...
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0 votes
1 answer
330 views

Writing and reading from and to SRAM memory [closed]

im just learning SRAM. I wanted to ask, consider the 4x4 memory cell array below If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
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