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Questions tagged [sram]

Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.

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Maximum cells in a row in a SRAM memory array

I was considering designing an SRAM memory array. For my design to be useful in a certain system, I need to have several cells in a row (e.g. 1024, 2048). In textbooks I have seen examples of arrays ...
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SRAM problem with reading the value I stored, “random” behavior

I've now spent quite a few hours of researching and trying to identify the error, but no luck for me. I'm making a very similar circuit to James Bates RAM video (schematic here: James Bates RAM ...
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35 views

Commercial SRAM with separate power supply for the core and peripheral?

Are there commercial SRAMs available with a separate power supply for the core transistors (6T) and a separate supply for the remaining circuitry such as the sense amps, write drivers, etc? I believe ...
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how to know how many Transistors are needed for column demultiplexing in different memory type arrays?

How many transistors are needed (if any) for the column demultiplexing in the following types of memory: NOR ROM Mask Programable (row x column = 2000 x 256 ) Dual Ported SRAM Reg File (1 read, 1 ...
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4answers
3k views

Why are SRAM based FPGA used more than NVM based FPGA?

SRAM based FPGAs need to load the bitstream again after power off. Meanwhile the Non-Volatile based one don't need that. I wonder, why are more experiments and security research done on the SRAM ...
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49 views

how to draw the transistor level schematic a 3-port SRAM

I have been trying to look up 3 port SRAM cell (2 reads and 1 write) everywhere, but I can't find anything about it. Does anyone know of any sources where I can look for how one might be implemented ...
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87 views

Z80 RD and WR to RD/WR?

This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
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52 views

use sram as logic analyzer?

So I was thinking of buying a logic analyzer and found that a lot of the cheap ones are good to only a few mhz, and the microcontroller based ones can't have big buffers. So I was wondering if I could ...
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52 views

Improving a SRAM-based memory cell by reducing number of transistors

I'm working on Emulated version of a memory cell. It is a volatile single-bit memory. It uses 4 NAND gates to store one bit. I want to connect several of those memory cells together to create one ...
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273 views

Why are the SRAM data and address pins numbered? [duplicate]

As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins. E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788....
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71 views

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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1answer
88 views

What makes Smartfusion2 FPGA clamed as highly secure to ensure secure booting?

Is the FPGA Smatfusion2 claimed to be highly secure by its manufacturer (Microsemi, now Mircochip) because it is a non volatile memory FPGA? Meanwhile the SRAM FPGA like the zynq 7000 are considered ...
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155 views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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1answer
72 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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1answer
62 views

SRAM Decoder Size [closed]

What is the typical area taken by address decoder logic in a SRAM? Could someone post area breakdown for each components in a SRAM?
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1answer
696 views

The purpose of FSMC

For a project, I need to have some external memory. I went for 1MB of SRAM. I am using an STM32 and I discovered the FSMC. I had a hard time understanding the purpose of this. What I read about it ...
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2answers
38 views

AS6C62256A SRAM Usage

I'm in the process of creating a RAM module for a breadboard computer I'm making. The RAM I've decided to use is the AS6C62256A SRAM chip, in 32K x 8. Here's the datasheet: https://www.alliancememory....
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1answer
36 views

transient noise plot in virtuoso

I was simulating a transient test on an SRAM cell, added a transient noise of 1-30MHZ frequency with 100 multiple simulations and calculated a VQ-QB graph(dots). I want to be able to only plot the ...
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2answers
78 views

Sram circuit design recommendations

I'm trying to design a simple SRAM board (using a cypress Cy7c1011cv33) to connect to my lattice machox3 starter kit's pin connectors. But I have some design questions, after reading their "SRAM Board ...
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1answer
15 views

For Intrinsic cap calculation what should be time interval for integration of current?

I am trying to get VDD cap of SRAM memory macro. I am ramping VDD by 50mv in a specific time interval and then integrating the I(VDD) for the same time interval. For different time intervals like 50n,...
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3answers
312 views

Sram battery backup

I don't have an option here in my country , No non-volatile sram and i need it for my project . i designed a circuit for that and need anyone's opinion if it's ok or need a correction .
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1answer
50 views

How to Improve my Computer Architecutre and Design skills? [closed]

Though my undergraduation was in Computer Science but I like to believe that I am more of an embedded systems enthusiast and I am comfortable in reading datasheets and timing diagrams. But this was ...
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1answer
540 views

Replacing Pseudo-SRAM with SRAM

This week I am repairing an old Game Gear, suffering from bad video memory. The original IC is a HM65256BLFP-10T: an asynchronous Pseudo-Static 8-bit 32k-word RAM with an access time of 100ns. I ...
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332 views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
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1answer
100 views

Unable to turn off / reset SRAM 23LC1024

I'm trying to reset an external SRAM 23LC1024 (turn it off and turn it on again) which connected to my Arduino Mega 2560. I need to do that because I want to profile the SRAM in an attempt to ...
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92 views

Is it possible to design sram without precharging?

I am new to sram design. Classical 6t topology uses precharge for read operation. However, I want to design a sram circuitry which does not use precharging, and is cmos compatible. What are the sram ...
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2answers
518 views

Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of data

I'm a beginner trying to understand the working of SRAM and DRAM. According to sources, DRAMs use a single transistor along with a capacitor(1T1C) to store a single bit, where the capacitor holds ...
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2answers
600 views

What is SNM(Static Noise Margin) in SRAM?

I have read multiple papers and articles about it but still, I am not able to understand fully. If you can explain me in layman terms I would be much happy. Thanks.
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1answer
393 views

4T SRAM read and write operation

Can anyone please tell me that how does a 4T SRAM works (4 MOS transistors+ 2 poly resistor)? How does the internal node pulls to a high value? Is it still static or dynamic?
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2answers
170 views

How does the Pre-charge and Equalizing circuit shown in the below figure work?

(from precharge circuit) Could you please explain the operation of the above circuit regarding how the transistors Q8 and Q9 are responsible for charging the Bit Lines with VDD/2 while Q7 equalizes ...
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0answers
58 views

Making a MT48LC8M16A2 SDRAM controller, can I do this with the command signals?

I have to make a very simple SDRAM controller for the MT48LC8M16A2 - 2 Meg x 14 x 4 Banks. My specific question is about the commands shown in the picture. For example for the read operation, Is it ...
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1answer
463 views

SRAM vs SDRAM as display buffer

I'm in a bit of a dilemma and I'm wondering if anybody here can help me. For a display application in need to use a framebuffer which is at least 2Mbytes.This framebuffer is used to drive a 800x480 ...
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2answers
91 views

Choosing SRAM for PIC project

I'm trying to design a guitar pedal effect, a looper to be precise. My idea is to use the PIC24FJ128GC010 which has a 16 bit ADC, in order to have a good audio quality. Since my idea is to convert, ...
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3answers
264 views

Using async SRAM in homebrew CPU

I am building a homebrew CPU and have now reached the point of designing the SRAM part. I plan of using a simple 32K x 8bit static RAM (such as the Cyprus CY62256N). My concern is that the part is ...
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170 views

1-bit SRAM circuit issues

I've been doing a lot of research on making a DIY SRAM circuit (1 bit for now). I've been primarily looking at http://codeitdown.com/diy-ram-memory/ and followed this circuit diagram and I've ...
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2answers
1k views

BIG SRAM with no parallel interface / SPI based?

I am designing a device that does not have an external bus interface and requires a modest ram size for binary data buffering. 16mb would be great, more would be awesome. It's quite easy to find SPI ...
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2answers
195 views

Does cache access time scale down with frequency in modern CPUs?

I have an application where I suspect the main overhead is accessing L3 cache. It is run on a modern Intel server-grade microprocessor with a huge L3 cache. There are many microprocessors available ...
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0answers
310 views

STM32F4: How to allocate all free memory in SRAM?

I need to allocate a huge array (~160kB) as a storage for SPI input (via DMA). Is there a way to ensure that the array will be allocated in SRAM, not FLASH? I couldn't find any Cortex-specific ...
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1answer
116 views

Why does 4T SRAM have very high pull-up resistors

I was just wondering why do 4T-SRAM cell designs always have extremely high resistance (~GΩ). Is it because of the constant static power consumption?
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1answer
521 views

Reading/Writing An SRAM Chip with an Arduino

The Background I want to be able to program an Atmel AT28C256 EEPROM via an Arduino Uno. I was having no luck in being able to write/read from it, so have fallen back to using an SRAM chip to ...
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1answer
106 views

SRAM HM6264 chip write cycle while output enabled (OE low fixed)

During SRAM write cycle, usually the !OE is disabled, while !WE and !CS are enabled. But for HM6264 SRAM chip (http://esd.cs.ucr.edu/webres/hm6264b.pdf), it allows the !OE to be enabled during write ...
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2answers
248 views

Designing a 6x64 Decoder

I am making a 64x32 bit SRAM, I need to use a 6x64 decoder as the Row address decoder. My question, is it possible to design a 6x64 Decoder using 3x8 Decoders?
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507 views

DS3232 over DS3231?

I am working on PIC controller and testing different RTC modules. Recently I came across DS3232 which is said to be an upgrade to DS3231. It says that DS3232 has an additional 236 bytes of SRAM. I ...
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1answer
118 views

SRAM output flickering

I am using the U62256A 32K x 8 bit static RAM. For testing purposes I connected all outputs to LEDs and since they are also inputs to a dip-switch so I'm able to write data. The write mode works ...
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1answer
151 views

SRAM works with short read cycles, fails with longer ones

I observe a rather weird behavior of an IS62WV51216BLL-55TLI SRAM chip connected to an FPGA. When I run it with the shortest read cycles possible, it works as expected: (here, I read the expected ...
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2answers
501 views

Interfacing 64Kx16 bit SRAM with Qsys

I have two 64Kx8 bit memory chips which I have connected to an FPGA configured using Qsys as a single 64Kx16 block. I have used a Generic Tri-state controller as interface, with both address width and ...
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1answer
190 views

AVR: why reading data have some delay from writing it in SRAM (Timing diagram)

In that timing diagram we see that the write command in the same time nearly with the data. Why we don't see that also in reading data and why there is that delay between data and read command? That ...
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1answer
47 views

Changing addresses faster than a parallel SRAM's response time

(Parallel) SRAM data sheets often list response times such as 70ns. If /CE and /RD are held low, and the address is changed every 35ns, what will be the output on the data pins? I am expecting ...
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1answer
100 views

Are source and drain terminals of Access Transistors in 6T SRAM interchangeable?

My textbook understanding is that the source terminals (S) of the access transistors in a 6T SRAM cell are to be connected to the bit lines (BL/BLB) while the drain terminals (D) to the storage nodes (...
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2answers
603 views

Rams and DQ lines

I'm studying DRams and SRams at university and on the slides the lines where a data is read or written is called DQ. But whats does it means? Maybe D is for Data, ...