Questions tagged [sram]

Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.

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25 views

Replacing Dallas NVRAM with larger capacity variant?

This DS1225AB-200 (8k x 8 = 64kB NVSRAM) is from 1995 and is probably dead (cannot measure from the outside.) The only close replacement in stock is a DS1230AB-100 (32k x 8 = 256kB.) Looking at the ...
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pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
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96 views

Write ADC data to memory and back to DAC (without MCU)

Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller? The application is to implement the audio loop of some sort,...
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30 views

finding NM by writing formulla in hspice

I want to calculate Write, hold, and read static noise margin of an SRAM block(WSNM, HSNM, and RSNM). but in order to do so, I want to write a command to do it, so I need to find input voltage when ...
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106 views

16-bit Byte-Addressable RAM Interface

I am a beginner to computer engineering and electrical engineering, and I have watched the entirety of Ben Eater's 8 bit breadboard computer series so I decided that because I understood that well, ...
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104 views

Fastest possible memory copy between 2 12ns SRAM DIP chips

Electronics newbie here... I'm trying to build a retrocomputer, and learn digital electronics along the way. I decided to begin with the video generation part, with a fast memory copier, independent ...
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21 views

Are there tips and tricks for SOM for place power pin and reduce PCB layers?

I'm developing a SOM with microcontroller, SDRAM and flash. Following the documentation that I found on the web and that made available by the component manufacturers (such as this: STM32MP1 Series ...
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343 views

Creating a memory mapping to peripheral memory on STM boards

I am trying to find a way to load/execute code that is stored on an external SRAM chip without having to load it to the microcontroller internal memory. I'm not 100% sure of the name for what I'm ...
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41 views

How to design 1T-1C DRAM circuit in spice design tools, such as LTSPICE?

I have been trying to design a DRAM cell using the LTSPICE MODEL tool. The DRAM that I want to design is of 2nd GENERATION, i.e, 1t-1c dram cell. But whenever I design digit line it states the line is ...
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OV7670 camera, how to use external SPI SRAM?

I'm using OV7670 camera with no FIFO and Arduino Mega2560 and I want to send 76800 bytes to my laptop, because of Arduino RAM limitations, I'm planning to use Serial SRAM 23LC1024 (1Mbit) so I can ...
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61 views

dual-port parallel-to-serial SRAM?

I wanna interface an old Motorola 68000-based system with an ESP32, and I was thinking of doing that through SRAM. However I can't seem to find any SRAM that I could put between them. What other ...
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121 views

SRAM and D-flip flop instead of transistor

I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit. But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It ...
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Buffer exceeding ramsize do not produce error in avr-gcc

In my source code I have tried to allocate a huge buffer exceeding the RAMSIZE value (RAM of my component (ATmega324PB) is 2k). ...
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84 views

Terminating bidirectional data lines and clock for memory-mapped devices

I am wiring up an STM32H743 to an SRAM or an FPGA to memory map it (i.e. I would like to be able to re-use the schematic). This SRAM operates at a maximum of 50MHz. The FPGA can operate at 50MHz all ...
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SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?

What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits? Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
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Does SRAM need PCB track length/impedance matching

Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff. I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit ...
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6T SRAM write operation calculations

C: Cut off , L: Linear , S : Saturation [keep in mind I am teaching this to myself ahead of time] I understand how to go about finding desired ratio (W/L) for read operation. In the image, M1 would ...
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How to get the memory state of SRAM on power up?

I am working on IoT authentication using a physically uncloneable function (PUF). I have read several articles which suggest that SRAM PUF can be used for that purpose. However, I want to know how can ...
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Why did they make the 74x170 (670) register file asychronous, no CLK input?

I am designing a retro computer as a project to learn digital electronics hands-on (not FPGA programming). I currently have an accumulator machine similar to the PDP-8 where the ALU has the ...
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97 views

External Memory IC which increments data on a clock pin

I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following: Store 1MB of data of 16-bit data This data is stored at specific ...
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84 views

Looking for a display RAM for my VGA card [closed]

I´m designing a simple 800x600 pixel VGA card, based on this example (but I don´t reduce the image size). I also want to use a display RAM, so a microprocessor can write a new image. For this I need ...
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67 views

SRAM Chip. Entering the data either manually through DIP Swithces or from the bus

I'm building a 8-bit "computer" on the breadboard mostly following tutorials from different sources. The project is educational, so I want to be able to execute all the steps manually and see what is ...
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142 views

Async SRAM Chip. Write Cycle. Data inputs timings

I'm working on my home project of building the 8-bit computer and now I'm on the RAM building stage. I'm going to use this chip for as my RAM UTRON UT62256C (datasheet). This chip is to be connected ...
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127 views

Adapting an I2C FRAM chip to an SRAM-like parallel interface

I have a project that requires a parallel interface non-volatile RAM. I had hoped to use an FRAM, however the only parallel FRAMs seem to much larger in capacity (and more importantly, price) than I ...
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If the Sense Amplifiers structure is the same as an SRAM cell's, why the differential voltage on the bit line gets amplified?

source How you can see the structure with 6 transistors of a Sense Amplifier (SA) is the same as a SRAM cell, but this latter causes a little variation on the bitline voltage that the SA will amplify....
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External bus interfacing

This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...
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61 views

How do I produce WE in this diagram?

I have designed a memory system that has 10KB ROM followed by 6KB of RAM. The ROM begins at 0000H. I had to use two 4K x 8bit ROMs and one 2K x 8 bit ROM. I also have to use one 2K x 8bit RAM and a 4K ...
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301 views

SRAM-Logic Block Diagram

I am a beginner and I am trying to understand the block diagram of a Static RAM. I want to draw a "256x4 bit SRAM" block diagram. According to some information I collected from the internet I managed ...
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150 views

Interfacing 16-bit SRAM/MRAM with Arduino Mega

I a looking to interface a MR2A16A 4Mb 16-bit MRAM with an Arduino Mega. I am new to interfacing with memory chips and would like some advice from someone more experienced than myself. I am not ...
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125 views

Writing and reading from and to SRAM memory [closed]

im just learning SRAM. I wanted to ask, consider the 4x4 memory cell array below If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
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RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
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What are the rr pins on an sram?

I've been using an IBM liberty (cell library) file for some SRAMs, dating back to 2007. [For copyright reasons, I can't post the content here]. I don't have the datasheet, and I've been trying to work ...
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On what inherent parameters does the speed of mosfet depend in a SRAM cell circuit?

I want to design 3D IC with 2 stages for a simple SRAM cell. Some of the MOSFETs will be on the top stage while some on the bottom stage. The MOSFETs on the top stage are supposed to be degraded in ...
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78 views

Value of resistor to protect against short circuit

I have a FPGA and a async-sram with OEn, WEn that I want to interface. To protect against short circuit I want to set resistors on the data lines. What is the value that would protect the FPGA and ...
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98 views

Maximum cells in a row in a SRAM memory array

I was considering designing an SRAM memory array. For my design to be useful in a certain system, I need to have several cells in a row (e.g. 1024, 2048). In textbooks I have seen examples of arrays ...
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73 views

Commercial SRAM with separate power supply for the core and peripheral?

Are there commercial SRAMs available with a separate power supply for the core transistors (6T) and a separate supply for the remaining circuitry such as the sense amps, write drivers, etc? I believe ...
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Why are SRAM based FPGA used more than NVM based FPGA?

SRAM based FPGAs need to load the bitstream again after power off. Meanwhile the Non-Volatile based one don't need that. I wonder, why are more experiments and security research done on the SRAM ...
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120 views

how to draw the transistor level schematic a 3-port SRAM

I have been trying to look up 3 port SRAM cell (2 reads and 1 write) everywhere, but I can't find anything about it. Does anyone know of any sources where I can look for how one might be implemented ...
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239 views

Z80 RD and WR to RD/WR?

This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
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97 views

use sram as logic analyzer?

So I was thinking of buying a logic analyzer and found that a lot of the cheap ones are good to only a few mhz, and the microcontroller based ones can't have big buffers. So I was wondering if I could ...
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Improving a SRAM-based memory cell by reducing number of transistors

I'm working on Emulated version of a memory cell. It is a volatile single-bit memory. It uses 4 NAND gates to store one bit. I want to connect several of those memory cells together to create one ...
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798 views

Why are the SRAM data and address pins numbered? [duplicate]

As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins. E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788....
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383 views

Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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105 views

What makes Smartfusion2 FPGA clamed as highly secure to ensure secure booting?

Is the FPGA Smatfusion2 claimed to be highly secure by its manufacturer (Microsemi, now Mircochip) because it is a non volatile memory FPGA? Meanwhile the SRAM FPGA like the zynq 7000 are considered ...
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883 views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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200 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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86 views

SRAM Decoder Size [closed]

What is the typical area taken by address decoder logic in a SRAM? Could someone post area breakdown for each components in a SRAM?
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3k views

The purpose of FSMC

For a project, I need to have some external memory. I went for 1MB of SRAM. I am using an STM32 and I discovered the FSMC. I had a hard time understanding the purpose of this. What I read about it ...
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AS6C62256A SRAM Usage

I'm in the process of creating a RAM module for a breadboard computer I'm making. The RAM I've decided to use is the AS6C62256A SRAM chip, in 32K x 8. Here's the datasheet: https://www.alliancememory....