Questions tagged [sram]

Static random-access memory (SRAM) if a form of memory that uses latches to store information. It is volatile and loses information when power is removed but unlike dynamic does not require refreshing to retain information. This comes at the cost of higher complexity and less density than DRAM, but allows static and low frequency / power use which is important in many systems.

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63 views

Buffer exceeding ramsize do not produce error in avr-gcc

In my source code I have tried to allocate a huge buffer exceeding the RAMSIZE value (RAM of my component (ATmega324PB) is 2k). ...
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35 views

Terminating bidirectional data lines and clock for memory-mapped devices

I am wiring up an STM32H743 to an SRAM or an FPGA to memory map it (i.e. I would like to be able to re-use the schematic). This SRAM operates at a maximum of 50MHz. The FPGA can operate at 50MHz all ...
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SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?

What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits? Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
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Does SRAM need PCB track length/impedance matching

Well, for educational purposes I've decided to make an FPGA-based board with PCIe, HDMI and other high-speed stuff. I've usually used relatively slow (35-45 ns) SRAM and having traces routed in 'hit ...
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6T SRAM write operation calculations

C: Cut off , L: Linear , S : Saturation [keep in mind I am teaching this to myself ahead of time] I understand how to go about finding desired ratio (W/L) for read operation. In the image, M1 would ...
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181 views

How to get the memory state of SRAM on power up?

I am working on IoT authentication using a physically uncloneable function (PUF). I have read several articles which suggest that SRAM PUF can be used for that purpose. However, I want to know how can ...
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Why did they make the 74x170 (670) register file asychronous, no CLK input?

I am designing a retro computer as a project to learn digital electronics hands-on (not FPGA programming). I currently have an accumulator machine similar to the PDP-8 where the ALU has the ...
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69 views

External Memory IC which increments data on a clock pin

I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following: Store 1MB of data of 16-bit data This data is stored at specific ...
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77 views

Looking for a display RAM for my VGA card [closed]

I´m designing a simple 800x600 pixel VGA card, based on this example (but I don´t reduce the image size). I also want to use a display RAM, so a microprocessor can write a new image. For this I need ...
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62 views

SRAM Chip. Entering the data either manually through DIP Swithces or from the bus

I'm building a 8-bit "computer" on the breadboard mostly following tutorials from different sources. The project is educational, so I want to be able to execute all the steps manually and see what is ...
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95 views

Async SRAM Chip. Write Cycle. Data inputs timings

I'm working on my home project of building the 8-bit computer and now I'm on the RAM building stage. I'm going to use this chip for as my RAM UTRON UT62256C (datasheet). This chip is to be connected ...
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101 views

Adapting an I2C FRAM chip to an SRAM-like parallel interface

I have a project that requires a parallel interface non-volatile RAM. I had hoped to use an FRAM, however the only parallel FRAMs seem to much larger in capacity (and more importantly, price) than I ...
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If the Sense Amplifiers structure is the same as an SRAM cell's, why the differential voltage on the bit line gets amplified?

source How you can see the structure with 6 transistors of a Sense Amplifier (SA) is the same as a SRAM cell, but this latter causes a little variation on the bitline voltage that the SA will amplify....
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43 views

External bus interfacing

This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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57 views

Running code from different storage

So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent. Question #1: As an example lets use linux ...
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How do I produce WE in this diagram?

I have designed a memory system that has 10KB ROM followed by 6KB of RAM. The ROM begins at 0000H. I had to use two 4K x 8bit ROMs and one 2K x 8 bit ROM. I also have to use one 2K x 8bit RAM and a 4K ...
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209 views

SRAM-Logic Block Diagram

I am a beginner and I am trying to understand the block diagram of a Static RAM. I want to draw a "256x4 bit SRAM" block diagram. According to some information I collected from the internet I managed ...
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1answer
120 views

Interfacing 16-bit SRAM/MRAM with Arduino Mega

I a looking to interface a MR2A16A 4Mb 16-bit MRAM with an Arduino Mega. I am new to interfacing with memory chips and would like some advice from someone more experienced than myself. I am not ...
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68 views

Writing and reading from and to SRAM memory [closed]

im just learning SRAM. I wanted to ask, consider the 4x4 memory cell array below If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
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1answer
475 views

RAM Row and Column Decoders

I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
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63 views

What are the rr pins on an sram?

I've been using an IBM liberty (cell library) file for some SRAMs, dating back to 2007. [For copyright reasons, I can't post the content here]. I don't have the datasheet, and I've been trying to work ...
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52 views

On what inherent parameters does the speed of mosfet depend in a SRAM cell circuit?

I want to design 3D IC with 2 stages for a simple SRAM cell. Some of the MOSFETs will be on the top stage while some on the bottom stage. The MOSFETs on the top stage are supposed to be degraded in ...
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64 views

Value of resistor to protect against short circuit

I have a FPGA and a async-sram with OEn, WEn that I want to interface. To protect against short circuit I want to set resistors on the data lines. What is the value that would protect the FPGA and ...
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83 views

Maximum cells in a row in a SRAM memory array

I was considering designing an SRAM memory array. For my design to be useful in a certain system, I need to have several cells in a row (e.g. 1024, 2048). In textbooks I have seen examples of arrays ...
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65 views

Commercial SRAM with separate power supply for the core and peripheral?

Are there commercial SRAMs available with a separate power supply for the core transistors (6T) and a separate supply for the remaining circuitry such as the sense amps, write drivers, etc? I believe ...
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Why are SRAM based FPGA used more than NVM based FPGA?

SRAM based FPGAs need to load the bitstream again after power off. Meanwhile the Non-Volatile based one don't need that. I wonder, why are more experiments and security research done on the SRAM ...
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102 views

how to draw the transistor level schematic a 3-port SRAM

I have been trying to look up 3 port SRAM cell (2 reads and 1 write) everywhere, but I can't find anything about it. Does anyone know of any sources where I can look for how one might be implemented ...
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186 views

Z80 RD and WR to RD/WR?

This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
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87 views

use sram as logic analyzer?

So I was thinking of buying a logic analyzer and found that a lot of the cheap ones are good to only a few mhz, and the microcontroller based ones can't have big buffers. So I was wondering if I could ...
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Improving a SRAM-based memory cell by reducing number of transistors

I'm working on Emulated version of a memory cell. It is a volatile single-bit memory. It uses 4 NAND gates to store one bit. I want to connect several of those memory cells together to create one ...
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625 views

Why are the SRAM data and address pins numbered? [duplicate]

As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins. E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788....
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Why is there a need for an eNVM and an eSRAM in the same SoC FPGA

SmartFusion2 SoC FPGA is distinguished by containing an embedded Non-Volatile-Memory (eNVM) that is used to store the code needed for the booting process of the FPGA after power up. So in the presence ...
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1answer
98 views

What makes Smartfusion2 FPGA clamed as highly secure to ensure secure booting?

Is the FPGA Smatfusion2 claimed to be highly secure by its manufacturer (Microsemi, now Mircochip) because it is a non volatile memory FPGA? Meanwhile the SRAM FPGA like the zynq 7000 are considered ...
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609 views

GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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1answer
173 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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80 views

SRAM Decoder Size [closed]

What is the typical area taken by address decoder logic in a SRAM? Could someone post area breakdown for each components in a SRAM?
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1answer
3k views

The purpose of FSMC

For a project, I need to have some external memory. I went for 1MB of SRAM. I am using an STM32 and I discovered the FSMC. I had a hard time understanding the purpose of this. What I read about it ...
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AS6C62256A SRAM Usage

I'm in the process of creating a RAM module for a breadboard computer I'm making. The RAM I've decided to use is the AS6C62256A SRAM chip, in 32K x 8. Here's the datasheet: https://www.alliancememory....
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59 views

transient noise plot in virtuoso

I was simulating a transient test on an SRAM cell, added a transient noise of 1-30MHZ frequency with 100 multiple simulations and calculated a VQ-QB graph(dots). I want to be able to only plot the ...
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238 views

Sram circuit design recommendations

I'm trying to design a simple SRAM board (using a cypress Cy7c1011cv33) to connect to my lattice machox3 starter kit's pin connectors. But I have some design questions, after reading their "SRAM Board ...
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1answer
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For Intrinsic cap calculation what should be time interval for integration of current?

I am trying to get VDD cap of SRAM memory macro. I am ramping VDD by 50mv in a specific time interval and then integrating the I(VDD) for the same time interval. For different time intervals like 50n,...
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770 views

Sram battery backup

I don't have an option here in my country , No non-volatile sram and i need it for my project . i designed a circuit for that and need anyone's opinion if it's ok or need a correction .
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58 views

How to Improve my Computer Architecutre and Design skills? [closed]

Though my undergraduation was in Computer Science but I like to believe that I am more of an embedded systems enthusiast and I am comfortable in reading datasheets and timing diagrams. But this was ...
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1answer
2k views

Replacing Pseudo-SRAM with SRAM

This week I am repairing an old Game Gear, suffering from bad video memory. The original IC is a HM65256BLFP-10T: an asynchronous Pseudo-Static 8-bit 32k-word RAM with an access time of 100ns. I ...
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520 views

CAS Latency and static RAM (SRAM)

Every time I read something about RAS e CAS there are mentions to the "DRAM" word. The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However ...
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1answer
150 views

Unable to turn off / reset SRAM 23LC1024

I'm trying to reset an external SRAM 23LC1024 (turn it off and turn it on again) which connected to my Arduino Mega 2560. I need to do that because I want to profile the SRAM in an attempt to ...
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2answers
935 views

Using a single transistor & capacitor (DRAM) vs a flip-flop(SRAM) to store a single bit of data

I'm a beginner trying to understand the working of SRAM and DRAM. According to sources, DRAMs use a single transistor along with a capacitor(1T1C) to store a single bit, where the capacitor holds ...
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2answers
2k views

What is SNM(Static Noise Margin) in SRAM?

I have read multiple papers and articles about it but still, I am not able to understand fully. If you can explain me in layman terms I would be much happy. Thanks.
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1k views

4T SRAM read and write operation

Can anyone please tell me that how does a 4T SRAM works (4 MOS transistors+ 2 poly resistor)? How does the internal node pulls to a high value? Is it still static or dynamic?
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2answers
419 views

How does the Pre-charge and Equalizing circuit shown in the below figure work?

(from precharge circuit) Could you please explain the operation of the above circuit regarding how the transistors Q8 and Q9 are responsible for charging the Bit Lines with VDD/2 while Q7 equalizes ...