Questions tagged [state-machines]

A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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37 views

Can FSMs be Timed and Recursive?

I am reading a textbook Circuit Design with VHDL, 3rd Edition by Volnei Pedroni. There, he claims that there exist 3 categories of finite-state machines - namely, regular, timed (where the output ...
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Designing a Combination Lock FSM: Converting State Diagram to Logic Gates

I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
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68 views

Converting momentary button presses to states

The goal is to implement a circuit in hardware with 2 inputs (A, B) and 2 outputs (A On, B On). An input (button press) toggles it's respective output, but also turns off the other output. State ...
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finite state machine explanation

Could someone explain this finite state machine? Also is this type of finite state machine Moore or Mealy? According to my understanding... The initial state is S0. If the input at this state for u=0 ...
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68 views

Potential risk of state machines [closed]

What are the potential risks when implementing a 12-states ?First of all I will need then 4 flip flops to draw my circuit giving a total of 16 states machines meaning that 4 states will be unused . ...
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Systematic ways to design a finite automaton whose input-output function or relation is a given one? [closed]

Given a function or relation, are there some systematic ways to design a finite automaton whose input-output function or relation is the given function or relation, assuming there is at least one such ...
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Should I use blocking or non-blocking assignments for the combinational block of an FSM?

In the book Finite State Machines in Hardware Theory and Design by Volnei A. Pedroni, MIT Press the following SystemVerilog template for FSM is found: The author has used non-blocking assignments in ...
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135 views

'1011' Overlapping (Moore) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog . The FSM that I am trying to implement is as shown below :- Verilog Module :- ...
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'1011' Overlapping (Mealy) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog. The FSM that I'm trying to implement is as shown below :- Verilog Module :- ...
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28 views

What would be the ASMD chart (or State Transistion diagram) for the UART transmitter?

Here is the diagram of the UART design. I am trying to write a SystemVerilog code from the ASMD chart of the UART transmitter. I have done the the UART receiver ASMD chart below. I know that the ...
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Verilog state machine not as expected

I have a simple problem, but not able to debug. I am not a novice in Verilog, but this problem seems surreal and weird. I have tried all I could to debug, but still cannot figure it out, so sking for ...
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HDL code for a wrapper or resizer between AMBA APB bus (32-bit) and the FPGA Fabric design (128-bit variable)

The design is implemented on a System On Chip (SoC) The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are ...
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4answers
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What is a “finite-state machine” and what are its use cases?

On Wikipedia, a finite state machine is defined as "any device storing the status of something at a given time." However, I don't see how other components, such as logic gates, flip flops, or ...
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Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...
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Having trouble with deriving the state diagram for an exam problem

The Problem: Derive the state diagram for a circuit that takes one input, A and gives out one output X, X is to be one, if and only if it detects a sequence "101" in A. Understanding The problem: if ...
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Designing a Moore sequence detector using three always blocks

Trying to implementing a Moore state machine using three always blocks. The Moore state machine has two inputs (ain[1:0]) and one output (yout). The output yout begins as 0 and remains a constant ...
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1answer
81 views

State Table & Karnaugh-map for Finite State Machine

I am trying to create a Finite State Machine that is able to check if a number string is valid. For example, it would accept 3, 4.65 or 8.93e-10. So far I have created a transition table for the ...
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Determining FSM states hint

I want to get the idea behind determining states of a FSM. I would appreciate a hint for the following problem as to where to look for the states. "A FSM should send out a signal to open a door. If ...
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140 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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Verilog code: how do I make the state transitions instantaneous?

I have the following Verilog code to implement ...
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Digital Circuits - clocked synchronous sequintal circuit ANALYSIS

i reached out to the final stage in solution . But i did not figure out what exactly wanted in homework “Assume that the machine is in state 00 and the output is also 0. Write the shortest ...
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Median Filter FSM Modelling

I'm trying to build a median filter in Verilog using a comparator to sort out the highest pixel value and erase it, then sort out the next highest etc. until I have only 5 pixels left (I'm treating ...
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1answer
106 views

What kind of FSM is it, if outputs depend on internally generated signals?

The classical definitions are that in a Moore machine the outputs depend only on the state, while in a Mealy machine they are also allowed to depend on inputs. But what if outputs and/or state ...
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Attach output to a state in Finite State Machine in VHDL

In my digital electronics class we are currently dealing with Finite-State-Machines and VHDL. I have written a VHDL-code for finite state machine and I've run into trouble. I want to attach the ...
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State Machine with D Flip Flops; how to deal with race conditions

Consider a state machine whose entire state is kept in a collection of edge-triggered D flip-flops. The outputs of these are fed into a combinatorial network which fully determines the next state, and ...
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1answer
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Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
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Implementing Moores or Mealys State Machine to display different numbers in 4-Digit 7-Segment Display using VHDL

Ok so i am here again, i posted this question some hours earlier and the answer was to use a state machine in order to achieve it. Now the the question is how do i implement it. I would like it to use ...
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1answer
120 views

Starting and stopping of a Mod N Counter for a FSM in Logisim

I'm working on a circuit for control logic. I'm using a 3 bit down counter. There is a control signal that when it goes high starts the counter by presetting it with a value of 5. The counter is ...
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1answer
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SystemVerilog FSM not working correctly

So, I was trying to create an FSM for my module which supposed to control five sensors. I thought I did it, but when I synthesized it, I saw that the code is synthesized as bunch of buffers and ...
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Finite State Machine and Reset Signal

let's consider a certain finite state machine, for instance a Mealy Machine: I was told that it cannot work properly in absence of a reset signal (for the State Register), since we would not know the ...
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1answer
55 views

Designing a counter

I want to design a counter which doesn't increments value every rising clock pulse(assuming positive edge triggered). Say I have a FSM which has 4 states . Only after traversing of the 4 states , I ...
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1answer
185 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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1answer
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Finite state machine inputs

if a finite state machine has 5 input signals A, B, C, D, E Does this mean there must be 2⁵ inputs along with the state built into the logic?
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Implementing Bellman-Ford algorithm on finite state machine [closed]

I wanted to ask whether it is even possible to implement the Bellman-Ford algorithm on a finite state machine. How can you determine whether a machine will have a finite number of states or not? ...
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1answer
219 views

Moore machine state diagram and state table

Is it me not understanding this table and diagram or something? If in a Moore machine, the output only depends on the current state Then why does the table for states F and H say the output is ...
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38 views

Identifying Moore machine from state diagram

i am just learning about state machines. I wanted to ask, if in a moore machine the output depends only on the current state, how can i identify this from a state diagram? $$\begin{array}{ccc|ccc} S0&...
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94 views

Moore machine for LED display

I want to know if my understanding of this state machine diagram is correct. The input is connected to a toggle: 0001,1 <- This 1 represent toggling the input Initially, when the circuit powers ...
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1answer
35 views

Mealy machine state transition

I'm currently learning about mealy machines and I'm slightly confused. If I am at state 00 and transition to state 01 indicated by the arrow. On the weighting on the arrow, the top refers to an input ...
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1answer
90 views

Boolean expressions from Bubble Diagram for D-flip flop entries

I am supposed to get boolean expressions for the two D-flip flops involved in this state diagram but I am stuck. I have come up with a truth table (except for output y which I don't understand) for ...
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2answers
587 views

FSM sequence detector in Verilog

I'm designing a finite state machine (FSM) to detect the sequence "10001" in Verilog. I'm having a similar problem to that described in this question in that my FSM does not tick when the sequence ...
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1answer
125 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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1answer
79 views

Can a finite state machine represent every possible discrete deterministic system?

Consider the two following definitions: Discrete Deterministic System: a system where inputs and outputs can have only a finite number of values, and is deterministic; Finite State Machine: an ...
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202 views

Finite State Machine Reset Signal FPGA

I've already done the datapath for my system using a synchronous reset and now I have to control everything using state machines. What I'm confused about right now is whether or not the reset signal ...
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1answer
91 views

outputs from Verilog finite state machine changing very late, possible reasons?

I am working on a finite state machine that is written in Verilog and being simulated in ModelSim. This FSM is for implementation of a SISC processor. In this implementation, we are using arithmetic ...
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251 views

Help with designing falling edge detector using a state machine

Using a state machine, I designed a circuit that detects the falling edge of a signal (working with positive edge clock), but my circuit has one more not gate than the circuit shown in this document: ...
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First encounter with State Diagrams

I'm a beginner to all this and have had a little bit of trouble understanding how exactly these tables work outside their base examples. I've made an attempt at drawing a diagram from a table that ...
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4answers
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Types of finites state machine in FPGA design

There are 2 types of FSM: 1- block of combinational logic + clocked block that hold only the current state 2- clocked block For example, if we take a look to how an SDRAM controller is made, most ...
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221 views

I have designed a Mealy FSM, that performs Divide by 5 operation on a binary number. How to implement control signal state for bitstream?

The FSM shown by both the table and state diagram perform Division by 5 on a binary input A. The individual states represent the remainders and the transition outputs are meant to be loaded into ...
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112 views

How would I finish out this mini project (emitting 1 whenever 101 is read)?

Design a Moore finite state machine that detects 1 0 1 in consecutive digits in the input stream of 0's and 1's received every clock cycle. The circuit should output a 1 when it detects 1 0 1 ...
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337 views

One-hot fsm in vhdl

I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state ...

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