Questions tagged [state-machines]

A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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FSM for carpark system with 2 sensors

Basically, I want to design a system where a vehicle goes through one of the sensors, then both, then leaves one, leaves both and finally counter goes up by 1. I've been able to draw the graph below. ...
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Multiplication 32x32 Mealy machine using 16x8 multiplier Verilog code

I am trying to implement a multiplication 32x32 Mealy machine using a 16x8 multiplicator in Verilog. I wrote the arithmetic part and the FSM part + a code to connect both and a test bench, but when I ...
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Why are Mealy's number of states less than Moore's number of states in finite state machines? [duplicate]

I was doing an assigment for my digital logic design course. One of the questions was to design a circuit using Moore's state machine and another one doing the same function using Mealy's state ...
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Could a CPU execute the fetch-execute cycle without a microsequencer/microcode?

VERY SPECIFIC QUESTION, PLEASE READ THROUGH ALL OF IT From wikipedia: "The sequence of operations that the control unit goes through to process an instruction is in itself like a short computer ...
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Is this a correct FSM graph?

This is question from H.ROOTH book Fundamentals of Logic Design. A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive inputs and produces an ...
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Design using 5x1 Mux, would this have any complications?

I am building a stopwatch with 5 counters. All are BCD counters with the exception of 1 modulo-6 counter (10ths, 1s, 10s, 1mins, 10mis.) I intend to pass these to the 7 segment displays on my board. ...
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Same behavior, different synthesis outputs, state machine coding style in VHDL

In an old course book on VHDL I've been revising, the author discussed the effect of coding style on the actual synthesis output of state machines. The example discussed in the book is a classic Mealy ...
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Using an SN74HC595 as a single-wire state machine

I have an SN74HC595 shift register, and I want to use it to replace a microcontroller to save space and cost, since a microcontroller isn't really needed in my application. The application is a system ...
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Issues with State Machine on FPGA

I've been tasked with making a state machine following the design requirements shown in the screenshot. I have everything mostly working and the simulation worked as expected. However, when I program ...
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Polling a button and delaying/switching based on the input. Millis? Delay and loop counter? [closed]

So this is the setup: I previously asked a question about this assignment. THIS IS A NEW QUESTION. THIS IS NEW CODE. ONLY THE IMAGES ARE THE SAME. I originally approached this using an interrupt on ...
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FSM state assignment techniques, which one should I use?

I'm currently studying finite-state machines at my university and the topic of state assignment optimization came up today. Apparently there are several technique for finding the correct state ...
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Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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Is a combinational logic circuit a Finite State Machine? [closed]

Is a combinational logic circuit a Finite State Machine? In other words, is the class of combinational circuits a subset of the class of Finite state machines?
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How to Setup the following Finite State Machine

The question goes as follows: Design a finite state machine (FSM) with two inputs (x and y) with an output z, which is asserted every time x and y change state to opposing values at the same time. A ...
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Access VHDL FSM state type in SystemVerilog testbench?

I have a VHDL block that implements a state machine, with states defined as a type and the current state as a signal of that ...
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Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
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block diagram model for elevator FSM

I have tried to design the block diagram for an elevator FSM as outlined by the steps provided by Mikef in this Stack Exchange post: SystemVerilog Elevator FSM issues with conceptual design and ...
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SystemVerilog Elevator FSM issues with conceptual design and translation to code

So I'm trying to create a FSM elevator system (single elevator 5 floors) in SystemVerilog and I'm having trouble mapping out how to write the code. In a traditional Moore or Mealy style FSM I can see ...
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What's importance of finite state machines (FSM) with respect to embedded systems implementation?

I was studying a project that involves implementation of a digitally controlled bridgeless power factor correction (BL PFC) converter. It uses PWM to drive the gate driver of the MOSFET switch and ...
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FSM vs Pipeline

I am new to the world of HDL. I am currently working on implementing AES in Verilog code. I manage the flow of my logic using varying FSMs. Given this approach I currently have to wait for the first ...
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Handling of complementary errors in embedded software

I've to design a firmware for an embedded device which may be in different error conditions at the same time. Each error condition requires to set the hardware components of the system into different ...
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How to turn this booth's algorithm state machine into a circuit?

I have a project of a booth's algorithm circuit, but I have problems with properly translating the FSM into a circuit. I've made the following FSM, and I can't turn it into a circuit that dictates the ...
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Quartus II - State Machine Viewer does't show all arrows/conditions?

As can be seen in the red circle, only arrows with condition a are shown, there is no !a condition at all. To replicate this ...
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What would be the flow chart for this simple state machine in VHDL

Here I have written a small program to clarify my question. I want to see how to draw flowchart for this piece of VHDL code. ...
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Why does Moore Finite State Machine need more states than Mealy Finite State Machine?

I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in ...
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Finite State Machine and Robotics [closed]

I have been wondering if I have for example to calculate one sum and a multiplication, I would have two different states, and if so, how would my truth table be, for example if I have a register tot ...
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how to implement several large state machines in hardware?

There are several ways to encode state machines. However, since a circuit is required to decode the next state and output, implementing a bigger state machine would possibly reduce fmax of a design ...
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Converting a Mealy machine to a Moore machine, conflicting states

I need to convert the following Mealy machine to a Moore machine. (see picture). The problem is state b. It has two conflicting states (1 pointing from a and c, 0 pointing from b itself). Since, when ...
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FSM binary number divisible by 5 truth table

I am having trouble seeing if my truth table based on the exercise's instructions is correct (mostly because the instructions are really confusing me and the TA's explanation really didn't help, this ...
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How does the JTAG TAP react to clock cycling, and why am I unable to get an instruction through?

I am writing a program for bit-banging a JTAG interface. As far as I understood the JTAG interface, it should act like this: On clock rise, the TDI and TMS inputs are sampled, if Shift-IR or Shift-DR ...
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State machine correct? 4b'1001 sequence detector

[![enter image description here][1]][1] Is this a correct state machine correct for detecting the 4 bit sequence 4b'1001? If any bit is out of sequence reset to the initial state. Once the last bit of ...
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2 votes
1 answer
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Long enumeration in VHDL to recognize a state machine

In order that Quartus II recognizes a state machine in a case / when statement the case must be applied on an enumerated type. In my code I am using a case on integer number going from 0 to 230. And ...
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6 votes
3 answers
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How can I convert a 4-digit BCD number to Binary in hardware? (using 74LS ICs and GAL22V10 ICs)

As the title suggests, I need to convert a 4-digit BCD number to binary. I am aware of the doubble-dabble algorithm (https://en.wikipedia.org/wiki/Double_dabble), and that if you use it backwards you ...
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2 votes
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Problem with designing finite state machine

I'm learning now finite state machines and I'm stuck with this exercise from a book "Digital Design and Computer Architecture" by David and Sarah Harris: First I tried to solve it without ...
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Why should we not change inputs to a sequential circuit (Moore machine) at the clock edge?

The code included here takes a bit stream of binary digits, Least Significant Bit (LSB) first, and outputs the two's complement of the complete stream, also LSB first. A Moore State diagram is ...
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Is state machine based sequence detector easier to verify than shift register based one?

Suppose I have two versions of sequence detectors: one is based on let's say Moore machine and the other one is based on simple shift register & comparator. Which one among these is easy to verify ...
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Can FSMs be Timed and Recursive?

I am reading a textbook Circuit Design with VHDL, 3rd Edition by Volnei Pedroni. There, he claims that there exist 3 categories of finite-state machines - namely, regular, timed (where the output ...
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Designing a Combination Lock FSM: Converting State Diagram to Logic Gates

I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
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Converting momentary button presses to states

The goal is to implement a circuit in hardware with 2 inputs (A, B) and 2 outputs (A On, B On). An input (button press) toggles it's respective output, but also turns off the other output. State ...
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Potential risk of state machines [closed]

What are the potential risks when implementing a 12-states ?First of all I will need then 4 flip flops to draw my circuit giving a total of 16 states machines meaning that 4 states will be unused . ...
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Systematic ways to design a finite automaton whose input-output function or relation is a given one? [closed]

Given a function or relation, are there some systematic ways to design a finite automaton whose input-output function or relation is the given function or relation, assuming there is at least one such ...
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3 votes
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'1011' Overlapping (Moore) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog . The FSM that I am trying to implement is as shown below :- Verilog Module :- ...
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5 votes
2 answers
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'1011' Overlapping (Mealy) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog. The FSM that I'm trying to implement is as shown below :- Verilog Module :- ...
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-1 votes
1 answer
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Verilog state machine not as expected

I have a simple problem, but not able to debug. I am not a novice in Verilog, but this problem seems surreal and weird. I have tried all I could to debug, but still cannot figure it out, so sking for ...
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What is a "finite-state machine" and what are its use cases?

On Wikipedia, a finite state machine is defined as "any device storing the status of something at a given time." However, I don't see how other components, such as logic gates, flip flops, or ...
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-1 votes
2 answers
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Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...
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Having trouble with deriving the state diagram for an exam problem

The Problem: Derive the state diagram for a circuit that takes one input, A and gives out one output X, X is to be one, if and only if it detects a sequence "101" in A. Understanding The problem: if ...
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Designing a Moore sequence detector using three always blocks

Trying to implementing a Moore state machine using three always blocks. The Moore state machine has two inputs (ain[1:0]) and one output (yout). The output yout begins as 0 and remains a constant ...
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State Table & Karnaugh-map for Finite State Machine

I am trying to create a Finite State Machine that is able to check if a number string is valid. For example, it would accept 3, 4.65 or 8.93e-10. So far I have created a transition table for the ...
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Determining FSM states hint

I want to get the idea behind determining states of a FSM. I would appreciate a hint for the following problem as to where to look for the states. "A FSM should send out a signal to open a door. If ...
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