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Questions tagged [state-machines]

State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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Deriving state table /equation confused

A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip- flop input equations and circuit output equation are JA = BX+B'Y' KA = B'xy' JB = A'x KB = A +...
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Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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41 views

Finite state machine inputs

if a finite state machine has 5 input signals A, B, C, D, E Does this mean there must be 2⁵ inputs along with the state built into the logic?
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52 views

Implementing Bellman-Ford algorithm on finite state machine [closed]

I wanted to ask whether it is even possible to implement the Bellman-Ford algorithm on a finite state machine. How can you determine whether a machine will have a finite number of states or not? ...
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Moore machine state diagram and state table

Is it me not understanding this table and diagram or something? If in a Moore machine, the output only depends on the current state Then why does the table for states F and H say the output is ...
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Identifying Moore machine from state diagram

i am just learning about state machines. I wanted to ask, if in a moore machine the output depends only on the current state, how can i identify this from a state diagram? $$\begin{array}{ccc|ccc} S0&...
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60 views

Moore machine for LED display

I want to know if my understanding of this state machine diagram is correct. The input is connected to a toggle: 0001,1 <- This 1 represent toggling the input Initially, when the circuit powers ...
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22 views

Mealy machine state transition

I'm currently learning about mealy machines and I'm slightly confused. If I am at state 00 and transition to state 01 indicated by the arrow. On the weighting on the arrow, the top refers to an input ...
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36 views

Boolean expressions from Bubble Diagram for D-flip flop entries

I am supposed to get boolean expressions for the two D-flip flops involved in this state diagram but I am stuck. I have come up with a truth table (except for output y which I don't understand) for ...
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1answer
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FSM sequence detector in Verilog

I'm designing a finite state machine (FSM) to detect the sequence "10001" in Verilog. I'm having a similar problem to that described in this question in that my FSM does not tick when the sequence ...
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23 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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71 views

Can a finite state machine represent every possible discrete deterministic system?

Consider the two following definitions: Discrete Deterministic System: a system where inputs and outputs can have only a finite number of values, and is deterministic; Finite State Machine: an ...
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Finite State Machine Reset Signal FPGA

I've already done the datapath for my system using a synchronous reset and now I have to control everything using state machines. What I'm confused about right now is whether or not the reset signal ...
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outputs from Verilog finite state machine changing very late, possible reasons?

I am working on a finite state machine that is written in Verilog and being simulated in ModelSim. This FSM is for implementation of a SISC processor. In this implementation, we are using arithmetic ...
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Help with designing falling edge detector using a state machine

Using a state machine, I designed a circuit that detects the falling edge of a signal (working with positive edge clock), but my circuit has one more not gate than the circuit shown in this document: ...
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First encounter with State Diagrams

I'm a beginner to all this and have had a little bit of trouble understanding how exactly these tables work outside their base examples. I've made an attempt at drawing a diagram from a table that ...
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4answers
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Types of finites state machine in FPGA design

There are 2 types of FSM: 1- block of combinational logic + clocked block that hold only the current state 2- clocked block For example, if we take a look to how an SDRAM controller is made, most ...
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I have designed a Mealy FSM, that performs Divide by 5 operation on a binary number. How to implement control signal state for bitstream?

The FSM shown by both the table and state diagram perform Division by 5 on a binary input A. The individual states represent the remainders and the transition outputs are meant to be loaded into ...
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How would I finish out this mini project (emitting 1 whenever 101 is read)?

Design a Moore finite state machine that detects 1 0 1 in consecutive digits in the input stream of 0's and 1's received every clock cycle. The circuit should output a 1 when it detects 1 0 1 ...
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One-hot fsm in vhdl

I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state ...
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220 views

How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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1answer
86 views

Digital Logic: What are “hamming code” and “Binary code” state machines?

I'm asked to draw the circuit for a state machine in one hot, hamming code and binary code models. I know what is one hot state machine, but i'm not sure what are the other 2. Google also didn't help. ...
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Finite State Machine FSM

I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit, but what is the function of ROM here ?
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How do I get the FSM table from the given diagram?

Given one is question and another solution. I cant come to this solution. can anyone help here
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173 views

Sequence Detector with multiple inputs

The question: Design an automaton that receives inputs X0, X1 and produces outputs Z0, Z1. Z0 is 1 If the last two bits of X0 are the complement of the last two received on X1. Z1 is 1 If in the ...
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Can we apply state reduction to a state table having more than 1 input?

Consider the following state diagram: I assigned states as follows: a=00 b=01 c=10 d=11 But when I attempted to reduce the table, I realized that: Some present states do have the same next state ...
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116 views

Finite State Machine Minimization

I can't understand how to eliminate the states. I draw this automa and after I create a table of the states (I must minimize it now and after create a minimal table of the states) Is someone who can ...
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1answer
64 views

Producing a VHDL design unit from a State Diagram

I need help understanding a stateflow diagram. I'm supposed to design it in VHDL as a beginner's exercise. I've gone through the VHDL tutorials on nandland.com, and could say I understand the basics ...
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128 views

Calculate number of states in edge triggered flip flops

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. simulate this circuit – Schematic created using CircuitLab The number ...
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2answers
367 views

State Machines - What happens to 'Don't Care's in the Output?

This is referencing the article about state machines on allaboutcircuits.com In their state table, they have a 'Don't Care' listed under the output for the state 11. However, in their k-map of the ...
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398 views

K-maps, do they completely simplify?

I've been told that K-maps produce a completely simplified boolean equation, and they can't or shouldnt be simplified anymore after that. However, on allaboutcircuits.com they were able to simplify an ...
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1answer
61 views

In practical FSM next state is function of current state and current inputs, what if next state is function of current and previous state?

A long time ago I came across an interesting FSM in which the next state was a function of current state and previous state, along with the current input values. Here previous state is not the state ...
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617 views

Warning!! Latch has unsafe behavior (vhdl)

will the warning affect the output result??? Why is this warning happen? This is my code ...
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1answer
89 views

Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however. Both flip-flops were ...
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336 views

State trasnsition diagram for a mealy machine

I created a state Transition diagram for the mealy machine below but I wasn't sure if this is correct. The part that confused me was that s1 has no edges.
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55 views

What's wrong with my taillight verilog design?

I'm working on a T-bird car taillight design code, here is my design: B means brake, all lights on at break, when turn left lights on sequence: 000000 -> 001000 ->011000->111000 turn right ...
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1answer
53 views

Implementing a Mealy Machine in Verilog

I have a piece of code that I don't understand: always_ff @(posedge CLK) state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate; ...
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1answer
114 views

Deign Finite State Machine - result doesn't look like what I want -vhdl

everyone. I design a Finite State Machine and try to implement it using VHDL, but the result confuses me. I take too much time on this but I still cannot solve this. Could you give me some advice ? ...
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2answers
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How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
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71 views

Getting overly complicated logic functions when designing a state machine, is there any way to simplify them?

I am having a bit of problem when trying to solve a state machine exercise. Basically I am supposed to design lock, when we get the right input in sequence etc it will open. The problem are the ...
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2answers
5k views

How many flip-flops are required for the implementation of this Mealy diagram?

I'm trying to create a circuit diagram that corresponds to the Mealy diagram I created for the following problem, but I'm not sure how many flip-flops I should use. Problem: A data stream receives ...
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2answers
127 views

Embedded system task scheduling for data aquisition on a CAN network

I'm struggling with the concept of how to schedule my tasks. My Setup: STM32F103 hooked up on CAN. Taking measurements with a Lidar V3 module comms via I2C, then distributing that measurement on the ...
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1answer
155 views

When and how to separate Control and Datapaths for hardware designs?

Must we always separate control and datapath during hardware programming? Are there any advantages? If yes then what is the basic methodology followed for this strategy? I am trying to interface an ...
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3answers
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Moore vs mealy, why the output is delayed in the former?

I am not an engineer (software developer myself) but would like to understand why moore machine output is delayed. I know that in Moore's machine, output depends only on the state, while in Mealy's ...
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VHDL interview question - detecting if a number can be divided by 5 without remainder

I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they ...
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3answers
906 views

How do I eliminate latches in FSM Verilog implementation?

I'm trying to create an FSM that left shifts a register until the MSB is 1 while counting the number of shifts completed. However, I have an issue with latches because I don't re-assign each register ...
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Create state transition diagram of a SSM that will output a “0” until the sequence 0, 1, 0 occurs.

As the title states, I'm trying to draw the state transition diagram of a sequential state machine that will output a "0" until the sequence 0, 1, 0 occurs. After the sequence occurs, the machine ...
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1answer
368 views

From a state transition table, how do I determine if I'm dealing with a Mealy or Moore machine?

From the state transition table below, how do I know if I'm constructing circuits for a Mealy or a Moore machine? Could someone explain the difference and what I should be looking for?
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206 views

Don't Understand the Notation on this State Diagram

This like a simple question, but I can't find a clear answer anywhere. Basically, I am used to seeing and implementing state diagrams that look like this: Where the output and input are in this ...
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2k views

Critical Races in Asynchronous Sequential Circuits

I have this flow table: I want to find out all the races in this, and whether they are critical races or not. My solution so far: x1=0, x2=1 and state as c, 2 changes are needed in the secondary ...