Questions tagged [state-machines]

A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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Is a state machine with a register for return state a good design choice?

I want to design a state machine for one module that has to communicate with another module via a protocol. Multiple states need might end up needing to communicate, State A, State B, State C. they ...
Weijie Chen's user avatar
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Moore Detector -1011, non-overlapping case

I am not able to figure out why the output goes low when I have done it properly. I used the similar logic for Mealy. It worked, but here it's not proper. ...
Ojas Kudari's user avatar
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UART Transmitter implementation using Verilog

I am trying to implement the UART transmitter FSM using Verilog, but the FSM is stuck at IDLE state. Can someone tell what mistakes am I making? The code is as ...
Kartikey's user avatar
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1 answer
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Mealy FSM using SR Flip Flops: pattern detector

I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern. It should detect if the pattern is either '1001' or '0110'. I was able to make the state diagram (I have attached the image), ...
Rach.1961's user avatar
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Verilog code for three-storey building

Ground, first and second floors and the inputs are r0 for ground, r1 for first floor, and r2 for second floor. The output will be d1, d2, up1, up2, and n (no action). Frequency is 215 Hz. State ...
had's user avatar
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Design of non-overlapping "1010" sequence detector

Assuming that A, B, C and D are the four states. When detecting the sequence "1010", in the D state, if overlapping is not allowed, we have the following state diagram: After detecting &...
Bruce Wayne's user avatar
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Why am I getting unknown states in output for Booth multiplier Verilog code?

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For a simple sequence detector, is there a problem with the FSM diagram for unused states?

This is the diagram, and the sequence we are detecting is 1011. The problem did not specify whether it is Mealy or Moore FSM, or whether it is overlapping or non-overlapping. When we get an input of ...
Obiick's user avatar
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Why I am getting one clock cycle delay in Verilog case statement?

I have a Verilog code here: ...
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Designing a sorting network with an FSM as opposed to combinational logic

During this semester I have been spending a bit of time learning how to use Verilog. I took on a project to develop a sorting network for 1024 32-bit numbers and tried to develop the circuit by ...
IdenticallyEulerian's user avatar
3 votes
2 answers
292 views

Why does the waveform simulation go wrong using structural D flip flop in Verilog?

I am designing a state machine in Verilog HDL to identify a specific number sequence. I must make it in structural. When I design the DFF with a behavioral style, everything is great, but with the ...
Thiên Lê's user avatar
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Verilog- Why is my state machine output arriving one clock cycle earlier?

I'm writing a Verilog code for a state machine with 4 states. state 0 is buffer time of 1 microsecond. state 1 is trig pulse for 10 microseconds. in state 2, the input is read. If the input is high ...
Milli_Wizard369's user avatar
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Is this Mealy FSM representation correct for 00111? [closed]

Is this Mealy FSM representation correct for a non-overlapping input bit sequence detector for the sequence 00111?
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Why is my testbench not driving any output?

In my testbench, I have connected the net z to the output of the seq_det module: ...
Killjoy's user avatar
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How should I proceed with implementing a multiple sequence detector FSM?

I was given the following question: Design a finite state machine (FSM), with not more than 4 states, that will detect more than one number of 1’s in the previous 3 samples. For example - ...
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How do I instantiate modules within case statements in Verilog HDL?

I am trying to make a sequence detector with 4 modes - Moore machine overlapping & non-overlapping and Mealy machine overlapping & non-overlapping. But writing my code like this gives me an ...
Killjoy's user avatar
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VHDL FSM not working as expected

I am not that experienced in VHDL. I am trying to implement a simple state machine that goes through 3 states - from idle, to DUT_run for 10 clock cycles, then remains at the done state. However the ...
David777's user avatar
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Clock Signal in Finite State Machines

I got this circuit from the book Introduction to Logic Circuits & Logic Design with Verilog, Second Edition. It's on page 248 for reference. It is supposed to be a circuit that opens or closes a ...
vigilante_fresh's user avatar
3 votes
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FSM to divider numbers in VHDL

I am trying to implement an FSM which divides two numbers which are assumed to be sane (no division over zero). In my specs, the machine is clocked, and at each clock edge, it checks the current state....
Ait-Gacem Nabil's user avatar
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How to fill in k-map with values from an finite state machine table?

I'm struggling to understand how I am supposed to fill in this k-map with the help of this finite state machine table? I understand that q1q0 shows the present state but I don't understand how I am ...
Dyson's user avatar
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2 votes
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Error: Iteration limit reached within 195 ns

This is an extension of the following post: Queue values are not being accessed As per the recommendation of the posts and using loops, I then tried to implement my problem using a Finite State ...
Rezef's user avatar
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FSM derivation for a digital Manchester encoder

I am looking at an FSM example in a digital design literature book where the idea is to create a simple FSM using a Moore machine for a Manchester encoder. The FSM takes two inputs. ...
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Sequence detector which detects sequences 100 and 111

I need to design a pattern detector that recognizes 100 and 111 bit patterns, even overlapping ones. I drew the state diagram as shown in the image and created the related table Could you tell me if ...
Vittorio Gatto's user avatar
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Trouble with FSM circuit using Schmitt trigger clock

I'm having some trouble with my circuit based on the design below, that I built for the lab. I'm using a Schmitt trigger clock. I built the circuit on a breadboard and connected it to the clock and ...
bittscoterie's user avatar
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1 answer
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Show that specific functions are correct for a race-free Moore machine

Context: The goal here is to create a Latch that holds a state. We have two inputs x1, x2 and two outputs f1, f2. When (x1, x2) = (0, 1) or (x1, x2) = (1, 0) the outputs should be the same. When the ...
contrapunctus's user avatar
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1 answer
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FSM for carpark system with 2 sensors

Basically, I want to design a system where a vehicle goes through one of the sensors, then both, then leaves one, leaves both and finally counter goes up by 1. I've been able to draw the graph below. ...
jamescodec's user avatar
1 vote
1 answer
453 views

Multiplication 32x32 Mealy machine using 16x8 multiplier Verilog code

I am trying to implement a multiplication 32x32 Mealy machine using a 16x8 multiplicator in Verilog. I wrote the arithmetic part and the FSM part + a code to connect both and a test bench, but when I ...
SpaceNugget's user avatar
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1 answer
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Why are Mealy's number of states less than Moore's number of states in finite state machines? [duplicate]

I was doing an assigment for my digital logic design course. One of the questions was to design a circuit using Moore's state machine and another one doing the same function using Mealy's state ...
skydiver4312's user avatar
1 vote
2 answers
322 views

Could a CPU execute the fetch-execute cycle without a microsequencer/microcode?

VERY SPECIFIC QUESTION, PLEASE READ THROUGH ALL OF IT From wikipedia: "The sequence of operations that the control unit goes through to process an instruction is in itself like a short computer ...
stackexchanger's user avatar
2 votes
1 answer
125 views

Is this a correct FSM graph?

This question is sourced from H. Roth's book 'Fundamentals of Logic Design.' It pertains to a sequential circuit featuring a single input (X) and one output (Z). The circuit's function entails ...
Nitish's user avatar
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Design using 5x1 Mux, would this have any complications?

I am building a stopwatch with 5 counters. All are BCD counters with the exception of 1 modulo-6 counter (10ths, 1s, 10s, 1mins, 10mis.) I intend to pass these to the 7 segment displays on my board. ...
Ryan Paye's user avatar
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1 answer
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Same behavior, different synthesis outputs, state machine coding style in VHDL

In an old course book on VHDL I've been revising, the author discussed the effect of coding style on the actual synthesis output of state machines. The example discussed in the book is a classic Mealy ...
Theo's user avatar
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2 votes
2 answers
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Using an SN74HC595 as a single-wire state machine

I have an SN74HC595 shift register, and I want to use it to replace a microcontroller to save space and cost, since a microcontroller isn't really needed in my application. The application is a system ...
TeD van Loon's user avatar
0 votes
1 answer
388 views

Issues with State Machine on FPGA

I've been tasked with making a state machine following the design requirements shown in the screenshot. I have everything mostly working and the simulation worked as expected. However, when I program ...
AyyBotto's user avatar
-5 votes
1 answer
684 views

Polling a button and delaying/switching based on the input. Millis? Delay and loop counter? [closed]

So this is the setup: I previously asked a question about this assignment. THIS IS A NEW QUESTION. THIS IS NEW CODE. ONLY THE IMAGES ARE THE SAME. I originally approached this using an interrupt on ...
EmptyAtoms's user avatar
0 votes
1 answer
201 views

FSM state assignment techniques, which one should I use?

I'm currently studying finite-state machines at my university and the topic of state assignment optimization came up today. Apparently there are several technique for finding the correct state ...
G. Ajello's user avatar
-10 votes
3 answers
619 views

Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
Shashank V M's user avatar
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-7 votes
2 answers
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Is a combinational logic circuit a Finite State Machine? [closed]

Is a combinational logic circuit a Finite State Machine? In other words, is the class of combinational circuits a subset of the class of Finite state machines?
Shashank V M's user avatar
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1 answer
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How to Setup the following Finite State Machine

The question goes as follows: Design a finite state machine (FSM) with two inputs (x and y) with an output z, which is asserted every time x and y change state to opposing values at the same time. A ...
A. Radek Martinez's user avatar
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1 answer
335 views

Access VHDL FSM state type in SystemVerilog testbench?

I have a VHDL block that implements a state machine, with states defined as a type and the current state as a signal of that ...
Travis Bassano's user avatar
0 votes
2 answers
755 views

Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
Michael's user avatar
2 votes
0 answers
328 views

block diagram model for elevator FSM

I have tried to design the block diagram for an elevator FSM as outlined by the steps provided by Mikef in this Stack Exchange post: SystemVerilog Elevator FSM issues with conceptual design and ...
James Dean's user avatar
-2 votes
1 answer
363 views

SystemVerilog Elevator FSM issues with conceptual design and translation to code

So I'm trying to create a FSM elevator system (single elevator 5 floors) in SystemVerilog and I'm having trouble mapping out how to write the code. In a traditional Moore or Mealy style FSM I can see ...
James Dean's user avatar
4 votes
4 answers
992 views

What's importance of finite state machines (FSM) with respect to embedded systems implementation?

I was studying a project that involves implementation of a digitally controlled bridgeless power factor correction (BL PFC) converter. It uses PWM to drive the gate driver of the MOSFET switch and ...
Vinayak P B's user avatar
1 vote
2 answers
1k views

FSM vs Pipeline

I am new to the world of HDL. I am currently working on implementing AES in Verilog code. I manage the flow of my logic using varying FSMs. Given this approach I currently have to wait for the first ...
ChrisMcNeill's user avatar
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2 answers
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Handling of complementary errors in embedded software

I've to design a firmware for an embedded device which may be in different error conditions at the same time. Each error condition requires to set the hardware components of the system into different ...
thinwybk's user avatar
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2 answers
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Why does Moore Finite State Machine need more states than Mealy Finite State Machine?

I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in ...
Ehsanul Karim Pappu's user avatar
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1 answer
70 views

Finite State Machine and Robotics [closed]

I have been wondering if I have for example to calculate one sum and a multiplication, I would have two different states, and if so, how would my truth table be, for example if I have a register tot ...
João Víctor Melo's user avatar
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2 answers
306 views

how to implement several large state machines in hardware?

There are several ways to encode state machines. However, since a circuit is required to decode the next state and output, implementing a bigger state machine would possibly reduce fmax of a design ...
gyuunyuu's user avatar
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1 answer
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FSM binary number divisible by 5 truth table

I am having trouble seeing if my truth table based on the exercise's instructions is correct (mostly because the instructions are really confusing me and the TA's explanation really didn't help, this ...
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