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Questions tagged [state-machines]

State machine is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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How can I further simplify this state machine to use fewer states? [on hold]

The following state diagram describes a mealy FSM that performs division by 5 on a binary number, A, and outputs the quotient bits. Node A is the reset state. It takes the 2 MSB bits at a time, a1 ...
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I have designed a Mealy FSM, that performs Divide by 5 operation on a binary number. How to implement control signal state for bitstream?

The FSM shown by both the table and state diagram perform Division by 5 on a binary input A. The individual states represent the remainders and the transition outputs are meant to be loaded into ...
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How would I finish out this mini project (emitting 1 whenever 101 is read)?

Design a Moore finite state machine that detects 1 0 1 in consecutive digits in the input stream of 0's and 1's received every clock cycle. The circuit should output a 1 when it detects 1 0 1 ...
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One-hot fsm in vhdl

I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state ...
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How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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66 views

Digital Logic: What are “hamming code” and “Binary code” state machines?

I'm asked to draw the circuit for a state machine in one hot, hamming code and binary code models. I know what is one hot state machine, but i'm not sure what are the other 2. Google also didn't help. ...
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Finite State Machine FSM

I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit, but what is the function of ROM here ?
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How do I get the FSM table from the given diagram?

Given one is question and another solution. I cant come to this solution. can anyone help here
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113 views

Sequence Detector with multiple inputs

The question: Design an automaton that receives inputs X0, X1 and produces outputs Z0, Z1. Z0 is 1 If the last two bits of X0 are the complement of the last two received on X1. Z1 is 1 If in the ...
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Can we apply state reduction to a state table having more than 1 input?

Consider the following state diagram: I assigned states as follows: a=00 b=01 c=10 d=11 But when I attempted to reduce the table, I realized that: Some present states do have the same next state ...
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Finite State Machine Minimization

I can't understand how to eliminate the states. I draw this automa and after I create a table of the states (I must minimize it now and after create a minimal table of the states) Is someone who can ...
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60 views

Producing a VHDL design unit from a State Diagram

I need help understanding a stateflow diagram. I'm supposed to design it in VHDL as a beginner's exercise. I've gone through the VHDL tutorials on nandland.com, and could say I understand the basics ...
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Calculate number of states in edge triggered flip flops

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. simulate this circuit – Schematic created using CircuitLab The number ...
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State Machines - What happens to 'Don't Care's in the Output?

This is referencing the article about state machines on allaboutcircuits.com In their state table, they have a 'Don't Care' listed under the output for the state 11. However, in their k-map of the ...
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206 views

K-maps, do they completely simplify?

I've been told that K-maps produce a completely simplified boolean equation, and they can't or shouldnt be simplified anymore after that. However, on allaboutcircuits.com they were able to simplify an ...
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In practical FSM next state is function of current state and current inputs, what if next state is function of current and previous state?

A long time ago I came across an interesting FSM in which the next state was a function of current state and previous state, along with the current input values. Here previous state is not the state ...
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402 views

Warning!! Latch has unsafe behavior (vhdl)

will the warning affect the output result??? Why is this warning happen? This is my code ...
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66 views

Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however. Both flip-flops were ...
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152 views

State trasnsition diagram for a mealy machine

I created a state Transition diagram for the mealy machine below but I wasn't sure if this is correct. The part that confused me was that s1 has no edges.
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51 views

What's wrong with my taillight verilog design?

I'm working on a T-bird car taillight design code, here is my design: B means brake, all lights on at break, when turn left lights on sequence: 000000 -> 001000 ->011000->111000 turn right ...
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1answer
44 views

Implementing a Mealy Machine in Verilog

I have a piece of code that I don't understand: always_ff @(posedge CLK) state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate; ...
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1answer
105 views

Deign Finite State Machine - result doesn't look like what I want -vhdl

everyone. I design a Finite State Machine and try to implement it using VHDL, but the result confuses me. I take too much time on this but I still cannot solve this. Could you give me some advice ? ...
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How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
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Getting overly complicated logic functions when designing a state machine, is there any way to simplify them?

I am having a bit of problem when trying to solve a state machine exercise. Basically I am supposed to design lock, when we get the right input in sequence etc it will open. The problem are the ...
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How many flip-flops are required for the implementation of this Mealy diagram?

I'm trying to create a circuit diagram that corresponds to the Mealy diagram I created for the following problem, but I'm not sure how many flip-flops I should use. Problem: A data stream receives ...
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CMOS logic circuit design state diagram [duplicate]

there is an alarm,which has three input(Wrong_pin,Correct_pin,Clock). This is the timing diagram of alarm trigger. . How can I start to draw state diagram using this timing diagram? Thank you. Edit: ...
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Embedded system task scheduling for data aquisition on a CAN network

I'm struggling with the concept of how to schedule my tasks. My Setup: STM32F103 hooked up on CAN. Taking measurements with a Lidar V3 module comms via I2C, then distributing that measurement on the ...
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1answer
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When and how to separate Control and Datapaths for hardware designs?

Must we always separate control and datapath during hardware programming? Are there any advantages? If yes then what is the basic methodology followed for this strategy? I am trying to interface an ...
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3answers
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Moore vs mealy, why the output is delayed in the former?

I am not an engineer (software developer myself) but would like to understand why moore machine output is delayed. I know that in Moore's machine, output depends only on the state, while in Mealy's ...
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11answers
4k views

VHDL interview question - detecting if a number can be divided by 5 without remainder

I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they ...
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3answers
575 views

How do I eliminate latches in FSM Verilog implementation?

I'm trying to create an FSM that left shifts a register until the MSB is 1 while counting the number of shifts completed. However, I have an issue with latches because I don't re-assign each register ...
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665 views

JK flip-flop counter State table

I'm having doubts that this JK flipflop counter is supposed to count in this order. (010>011>001>100>110>111>101>000) I labeled the flipflops as A, B, and C from starting from left to right. Can ...
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User Defined reset in VHDL

I am making a synchronous D-FLipFLop circuit for an assignment about car blinkers, I am only having a final issue with what the system does and should do when i change blinker direction immediately (e....
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Create state transition diagram of a SSM that will output a “0” until the sequence 0, 1, 0 occurs.

As the title states, I'm trying to draw the state transition diagram of a sequential state machine that will output a "0" until the sequence 0, 1, 0 occurs. After the sequence occurs, the machine ...
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309 views

From a state transition table, how do I determine if I'm dealing with a Mealy or Moore machine?

From the state transition table below, how do I know if I'm constructing circuits for a Mealy or a Moore machine? Could someone explain the difference and what I should be looking for?
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141 views

Don't Understand the Notation on this State Diagram

This like a simple question, but I can't find a clear answer anywhere. Basically, I am used to seeing and implementing state diagrams that look like this: Where the output and input are in this ...
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Critical Races in Asynchronous Sequential Circuits

I have this flow table: I want to find out all the races in this, and whether they are critical races or not. My solution so far: x1=0, x2=1 and state as c, 2 changes are needed in the secondary ...
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How do you determine what the circuit that determines the next state looks like?

This is a homework question. I've only started to learn about circuits and it's just that I'm completely lost on what the circuit to determine the next state would look like. I'm looking for the ...
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1answer
481 views

FSM implementation using single always block in Verilog?

So while looking up for material on implementing high level state machines in Verilog I came upon this: I am also trying to implement a high level FSM in Verilog that has a number of nested ...
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1answer
444 views

Finite State Machine for x/3

I was asked to design a FSM for outputting x/3 without the remainder. This should be implemented using a synchronous system defined as follows: input: on each clock cycle t, one bit x[t] output: on ...
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2answers
543 views

How can I make the state diagram from the code in Verilog?

How do I draw the state diagram of this state machine?
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Where finite-state machine code belong in µC?

When I learned about micrcontrollers, teachers taught me to always end the code with while(1); with no code inside that loop. This was to be sure that the software ...
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1answer
104 views

Determining the ROM contents of a circuit

I have a state transition table and a truth table stored in a ROM. The truth table was obtained from the state transition table but I'm not sure how. Could anyone explain how the truth table is ...
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1answer
52 views

Synchonous finite state machine from output sequence

I'm reviewing for my exam and this questing popped from questions that were previously asked in the exam. Problem is below. Question: I'm totally confused about this, how do I get started? Trial: My ...
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4answers
776 views

What is state in a sequential circuit?

I understand that the output of a flip flop is also called as the state and the output of the flip flop before the clock pulse is applied is called as present state and after the application of clock ...
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331 views

Nested Interrupts - Design with Finite State Machine

I am developping an event-drive embedded system that will use three kind of interrupts : timer interrupt, SPI interrupt and USART interrupt. I am working with an STM32F7 MCU and the idea is to use the ...
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3answers
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Designing a state machine to detect if input was high exactly 2 times in last 4 clocks

Design a Mealy machine with a one bit input, and a one bit output. The output is 1 if in the last 4 clock s, exactly 2 of 4 values on input are 1. Use D flip-flops and discrete gates. Use binary ...
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160 views

Verilog LCD State Machine

Project: LCD initialize on Altera DEO (EP3C16F484C6 FPGA) using Hitachi HD47780 Design: State machine to step through all the necessary timing constraints. Sources: Based heavily on http://www.xess....
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State machine of a coffee machine [closed]

I can not solve this exercise. I really need help. Design a coffee vending machine with the following specifications: Each coffee costs 15 c. The only output from the state machine, Y, ...
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1answer
965 views

Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation ...