Questions tagged [state-machines]

A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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First encounter with State Diagrams

I'm a beginner to all this and have had a little bit of trouble understanding how exactly these tables work outside their base examples. I've made an attempt at drawing a diagram from a table that ...
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Median Filter FSM Modelling

I'm trying to build a median filter in Verilog using a comparator to sort out the highest pixel value and erase it, then sort out the next highest etc. until I have only 5 pixels left (I'm treating ...
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Implementing Moores or Mealys State Machine to display different numbers in 4-Digit 7-Segment Display using VHDL

Ok so i am here again, i posted this question some hours earlier and the answer was to use a state machine in order to achieve it. Now the the question is how do i implement it. I would like it to use ...
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Moore machine for LED display

I want to know if my understanding of this state machine diagram is correct. The input is connected to a toggle: 0001,1 <- This 1 represent toggling the input Initially, when the circuit powers ...
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How do I get the FSM table from the given diagram?

Given one is question and another solution. I cant come to this solution. can anyone help here
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Rotation Detector Sequential Circuit

o I have tried tackling this problem, but I cant seem to get anywhere. I dont know if I am making things too complex. I came up with this state diagram and state table. But I dont know if this is too ...
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38 views

Verilog state machine not as expected

I have a simple problem, but not able to debug. I am not a novice in Verilog, but this problem seems surreal and weird. I have tried all I could to debug, but still cannot figure it out, so sking for ...
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HDL code for a wrapper or resizer between AMBA APB bus (32-bit) and the FPGA Fabric design (128-bit variable)

The design is implemented on a System On Chip (SoC) The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are ...
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Draw a State Diagram

I've been struggling with this problem for awhile now and I need a state diagram before I can move on to the other steps. Please lmk if there is anything I can do to explain this problem. If somebody ...
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Determining FSM states hint

I want to get the idea behind determining states of a FSM. I would appreciate a hint for the following problem as to where to look for the states. "A FSM should send out a signal to open a door. If ...
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Verilog code: how do I make the state transitions instantaneous?

I have the following Verilog code to implement ...
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Digital Circuits - clocked synchronous sequintal circuit ANALYSIS

i reached out to the final stage in solution . But i did not figure out what exactly wanted in homework “Assume that the machine is in state 00 and the output is also 0. Write the shortest ...
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55 views

Designing a counter

I want to design a counter which doesn't increments value every rising clock pulse(assuming positive edge triggered). Say I have a FSM which has 4 states . Only after traversing of the 4 states , I ...
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197 views

Moore machine state diagram and state table

Is it me not understanding this table and diagram or something? If in a Moore machine, the output only depends on the current state Then why does the table for states F and H say the output is ...
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Identifying Moore machine from state diagram

i am just learning about state machines. I wanted to ask, if in a moore machine the output depends only on the current state, how can i identify this from a state diagram? $$\begin{array}{ccc|ccc} S0&...
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Mealy machine state transition

I'm currently learning about mealy machines and I'm slightly confused. If I am at state 00 and transition to state 01 indicated by the arrow. On the weighting on the arrow, the top refers to an input ...
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113 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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183 views

I have designed a Mealy FSM, that performs Divide by 5 operation on a binary number. How to implement control signal state for bitstream?

The FSM shown by both the table and state diagram perform Division by 5 on a binary input A. The individual states represent the remainders and the transition outputs are meant to be loaded into ...
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How to create a state transition table for a Mealy machine

I'm trying to design the counter shown in the diagram below with the counting sequence 123456 (i.e X1=1, X2=2, ...) as a Mealy machine. However, I'm having trouble figuring out how to create the ...
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State trasnsition diagram for a mealy machine

I created a state Transition diagram for the mealy machine below but I wasn't sure if this is correct. The part that confused me was that s1 has no edges.
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Create state transition diagram of a SSM that will output a “0” until the sequence 0, 1, 0 occurs.

As the title states, I'm trying to draw the state transition diagram of a sequential state machine that will output a "0" until the sequence 0, 1, 0 occurs. After the sequence occurs, the machine ...
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128 views

How do you determine what the circuit that determines the next state looks like?

This is a homework question. I've only started to learn about circuits and it's just that I'm completely lost on what the circuit to determine the next state would look like. I'm looking for the ...
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209 views

Determining the ROM contents of a circuit

I have a state transition table and a truth table stored in a ROM. The truth table was obtained from the state transition table but I'm not sure how. Could anyone explain how the truth table is ...
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57 views

Synchonous finite state machine from output sequence

I'm reviewing for my exam and this questing popped from questions that were previously asked in the exam. Problem is below. Question: I'm totally confused about this, how do I get started? Trial: My ...
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asychronous finite state machine , minimization and encode states

Hey. I have Moore type asychronous fsm. I need to minize it, then encode states and get excitation functions for JK flip flops and output. I have problem with encoding. As far as I know anti race ...
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Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...