Questions tagged [state-machines]

A finite state machine (or state machine) is a very generic term for any process (electronic or otherwise) whose output is not simply a function of its current inputs, but also depends on its past history. In other words, it has "memory", or internal state information.

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724 views

K-maps, do they completely simplify?

I've been told that K-maps produce a completely simplified boolean equation, and they can't or shouldnt be simplified anymore after that. However, on allaboutcircuits.com they were able to simplify an ...
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90 views

In practical FSM next state is function of current state and current inputs, what if next state is function of current and previous state?

A long time ago I came across an interesting FSM in which the next state was a function of current state and previous state, along with the current input values. Here previous state is not the state ...
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1k views

Warning!! Latch has unsafe behavior (vhdl)

will the warning affect the output result??? Why is this warning happen? This is my code ...
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167 views

Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however. Both flip-flops were ...
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715 views

State trasnsition diagram for a mealy machine

I created a state Transition diagram for the mealy machine below but I wasn't sure if this is correct. The part that confused me was that s1 has no edges.
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63 views

What's wrong with my taillight verilog design?

I'm working on a T-bird car taillight design code, here is my design: B means brake, all lights on at break, when turn left lights on sequence: 000000 -> 001000 ->011000->111000 turn right ...
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1answer
60 views

Implementing a Mealy Machine in Verilog

I have a piece of code that I don't understand: always_ff @(posedge CLK) state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate; ...
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163 views

Deign Finite State Machine - result doesn't look like what I want -vhdl

everyone. I design a Finite State Machine and try to implement it using VHDL, but the result confuses me. I take too much time on this but I still cannot solve this. Could you give me some advice ? ...
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2answers
3k views

How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
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75 views

Getting overly complicated logic functions when designing a state machine, is there any way to simplify them?

I am having a bit of problem when trying to solve a state machine exercise. Basically I am supposed to design lock, when we get the right input in sequence etc it will open. The problem are the ...
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9k views

How many flip-flops are required for the implementation of this Mealy diagram?

I'm trying to create a circuit diagram that corresponds to the Mealy diagram I created for the following problem, but I'm not sure how many flip-flops I should use. Problem: A data stream receives ...
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2answers
149 views

Embedded system task scheduling for data aquisition on a CAN network

I'm struggling with the concept of how to schedule my tasks. My Setup: STM32F103 hooked up on CAN. Taking measurements with a Lidar V3 module comms via I2C, then distributing that measurement on the ...
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312 views

When and how to separate Control and Datapaths for hardware designs?

Must we always separate control and datapath during hardware programming? Are there any advantages? If yes then what is the basic methodology followed for this strategy? I am trying to interface an ...
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3answers
2k views

Moore vs mealy, why the output is delayed in the former?

I am not an engineer (software developer myself) but would like to understand why moore machine output is delayed. I know that in Moore's machine, output depends only on the state, while in Mealy's ...
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7k views

VHDL interview question - detecting if a number can be divided by 5 without remainder

I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they ...
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3answers
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How do I eliminate latches in FSM Verilog implementation?

I'm trying to create an FSM that left shifts a register until the MSB is 1 while counting the number of shifts completed. However, I have an issue with latches because I don't re-assign each register ...
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Create state transition diagram of a SSM that will output a “0” until the sequence 0, 1, 0 occurs.

As the title states, I'm trying to draw the state transition diagram of a sequential state machine that will output a "0" until the sequence 0, 1, 0 occurs. After the sequence occurs, the machine ...
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1answer
502 views

From a state transition table, how do I determine if I'm dealing with a Mealy or Moore machine?

From the state transition table below, how do I know if I'm constructing circuits for a Mealy or a Moore machine? Could someone explain the difference and what I should be looking for?
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1answer
366 views

Don't Understand the Notation on this State Diagram

This like a simple question, but I can't find a clear answer anywhere. Basically, I am used to seeing and implementing state diagrams that look like this: Where the output and input are in this ...
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1answer
128 views

How do you determine what the circuit that determines the next state looks like?

This is a homework question. I've only started to learn about circuits and it's just that I'm completely lost on what the circuit to determine the next state would look like. I'm looking for the ...
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1k views

FSM implementation using single always block in Verilog?

So while looking up for material on implementing high level state machines in Verilog I came upon this: I am also trying to implement a high level FSM in Verilog that has a number of nested ...
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1answer
2k views

Finite State Machine for x/3

I was asked to design a FSM for outputting x/3 without the remainder. This should be implemented using a synchronous system defined as follows: input: on each clock cycle t, one bit x[t] output: on ...
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982 views

How can I make the state diagram from the code in Verilog?

How do I draw the state diagram of this state machine?
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597 views

Where finite-state machine code belong in µC?

When I learned about micrcontrollers, teachers taught me to always end the code with while(1); with no code inside that loop. This was to be sure that the software ...
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1answer
209 views

Determining the ROM contents of a circuit

I have a state transition table and a truth table stored in a ROM. The truth table was obtained from the state transition table but I'm not sure how. Could anyone explain how the truth table is ...
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57 views

Synchonous finite state machine from output sequence

I'm reviewing for my exam and this questing popped from questions that were previously asked in the exam. Problem is below. Question: I'm totally confused about this, how do I get started? Trial: My ...
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4answers
2k views

What is state in a sequential circuit?

I understand that the output of a flip flop is also called as the state and the output of the flip flop before the clock pulse is applied is called as present state and after the application of clock ...
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3answers
392 views

Designing a state machine to detect if input was high exactly 2 times in last 4 clocks

Design a Mealy machine with a one bit input, and a one bit output. The output is 1 if in the last 4 clock s, exactly 2 of 4 values on input are 1. Use D flip-flops and discrete gates. Use binary ...
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278 views

Verilog LCD State Machine

Project: LCD initialize on Altera DEO (EP3C16F484C6 FPGA) using Hitachi HD47780 Design: State machine to step through all the necessary timing constraints. Sources: Based heavily on http://www.xess....
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State machine of a coffee machine [closed]

I can not solve this exercise. I really need help. Design a coffee vending machine with the following specifications: Each coffee costs 15 c. The only output from the state machine, Y, ...
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2k views

Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation ...
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1answer
225 views

Do all non self starting counters have lock out problem? [closed]

I understand that a self starting counter is one which could start counting from any state but eventually reaches the required count sequence, meaning if a non self starting counter starts from an ...
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2answers
345 views

How to set initial state of 4 bit “exclusive output” Latch?

I have extended SR flip-flop to have four inputs and four outputs. It works well once an input has been pressed but I'm not sure how to set the initial state. I saw a schematic online where a ...
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424 views

Overlapping clock and data edges in multiple state machine designs

I have a general question about multiple state machine logic designs. Think of a system having multiple finite state machines with a single clock and rising edged flip flops. These machines share ...
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1answer
1k views

Creating a State Diagram and State Table with known output

I've been given a word problem, and I must make a state diagram followed by a state table. The problem reads Design a circuit that has two inputs, clk and X and produces output O. X may change every ...
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2answers
555 views

Design Asynchronous State Machine using T flip-flop

There is this question that i don't really get the solution: Design a pulse-mode circuit having two input lines x1 and x2, and one output line z. The circuit should produce an output pulse coincide ...
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1answer
294 views

Is there a “standard” way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
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1answer
187 views

What would be state diagram of robot controller?

Robot Controller Problem A computer needs to control a robot, where the computer sends the following commands: Do nothing 00 Turn right 01 Turn left 10 Move forward 11 You have to design a circuit ...
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2answers
911 views

Traffic Light Controller

I have to design a sequential circuit for a traffic light controller. It has 6 outputs, Red-Green-Yellow for North/South and East/West lights. What has to happen is that every 8 clock cycles (one ...
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2answers
84 views

how to identify no of states? [closed]

If a sequential circuit will produce output as high if both present and previous inputs represent even number with present input being LSB. How many states are required to analyze this? how to ...
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1answer
286 views

Is there an example of a Mealy state machine that can not be converted to a Moore?

I understand that they are generally interchangeable, and also that all Moore machines can be converted to Mealy, hence the doubt if there is one where the reverse is not possible?
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766 views

Mealy subtractor using JK flip-flops

I have to prepare a subtractor FSM for my laboratories (using Mealy graph, and build it with JK flip-flops). I'm in the point where I can do it using D flip-flops. So here's how it looks: ...
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2answers
1k views

debounce state machine graph

I need to make the graph for a state machine that debounces an input signal, maintaining the current up/low input signal for a certain time, and to calculate this time im using a counter. I am having ...
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1answer
57 views

asychronous finite state machine , minimization and encode states

Hey. I have Moore type asychronous fsm. I need to minize it, then encode states and get excitation functions for JK flip flops and output. I have problem with encoding. As far as I know anti race ...
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2answers
2k views

2 bit saturating counter

I'm trying to design a 2 bit saturating counter but am very stuck in figuring out the state diagram and building the circuit from there. This is what I understand of the saturating counter so far. ...
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1answer
382 views

Should we use asynchronous inputs in Moore blocks and synchronous in Mealy blocks?

Consider we have two n-bit counters CNT_A and CNT_B two n-bit unsigned comparators CMP_A, CMP_B and two n-bit binary numbers N1, N2. The counters have two inputs C, L for synchronous count and load ...
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1answer
41 views

How to plan diagram states of this machine?

How can I design a tracking system that receives two numbers x and y parallel, bit per cycle, starting LSB, and emitting a "1" when x>2y ? I know that "2y" is like "y" with zero in right side .. ...
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2answers
93 views

State diagram and an unknown table

I am wondering what kind of table that is, is that perhaps a state table? I am not sure what \$q_1\$ and \$q_2\$ stand for. They don't look like next state functions since these are denoted \$q^+\$ in ...
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49 views

How to find out the output of state machine if not listed

I'm studying Moore and Mealy machines, everything works fine, until I found a Moore machine where output was not listed.I know that outputs of Moore machines depend of present state, but how can I ...
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457 views

One-hot machine transition table

I began to study One-hot machines, and I want you to check my transition table, because I'm not sure if it is true. Below you will find: state machine transition table Karnaugh map First of all, I ...