Questions tagged [std-logic-vector]
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4
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-1
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VHDL - Why do runtime-determined std_logic_vector assignments fail, but succeed if it's assigned to an array
In my process declarations, I have
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2
votes
1answer
393 views
Working of resize function in VHDL
I am using resize function as below to convert 32bit vector(temp2_32) to 16 bit vector(temp2).
temp2<=std_logic_vector(resize(to_sfixed(temp2_32,3,-28),1,-14));
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0
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1answer
85 views
0
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0answers
330 views
VHDL: how to take a character out of a string
I have an array of strings. A state machine is supposed to take one at a time, then push it to a FIFO character by character. The fifo is of an std_logic_vector(7 downto 0) type. What is the syntax to ...
