Questions tagged [std-logic-vector]

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Working of resize function in VHDL

I am using resize function as below to convert 32bit vector(temp2_32) to 16 bit vector(temp2). temp2<=std_logic_vector(resize(to_sfixed(temp2_32,3,-28),1,-14)); ...
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Subtracter with VHDL

I have this: ...
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VHDL: how to take a character out of a string

I have an array of strings. A state machine is supposed to take one at a time, then push it to a FIFO character by character. The fifo is of an std_logic_vector(7 downto 0) type. What is the syntax to ...