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Microchip Libero SOC warning: Sharing sequential element Cmd_TimErr. Add a syn_preserve attribute to the element to prevent sharing

I am programming an FPGA (A3PE3000-FG484) and I get this warning when I ran synthesis in Libero: Sharing sequential element Cmd_TimErr. Add a syn_preserve attribute to the element to prevent sharing. ...
user389831's user avatar
-1 votes
1 answer
987 views

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
Arseniy's user avatar
  • 2,247
1 vote
1 answer
1k views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
axk's user avatar
  • 825
1 vote
2 answers
2k views

Inferring RAM block usage with FIFO

I'm trying to infer the usage of a RAM block of my FPGA, but I fail to understand what are the hints needed. I use Synplify Pro as my synthesis tool. If I'm not mistaken, this is a dual port ...
Fluffy's user avatar
  • 308
3 votes
1 answer
766 views

passing Synplify options from Lattice Diamond TCL code

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at ...
vermaete's user avatar
  • 390