Questions tagged [synthesis]

Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.

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Non Synthesizable VHDL Code

I am trying to synthesize this VHDL code and it won't do it -- Why ? ...if( v(0) = '1' AND o_done = '1' ) then.... it complains about o_done ? Read error: trying to read port of mode OUT What can I do ...
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Post-synthesis simulation using Nangateopencelllibrary_pdkv1_3_v2010_12

I'm wondering if anyone has used the open-source Nangate library to do synthesis and post-synthesis simulation? I was trying to synthesis my processor and got the netlist verilog file from design ...
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72 views

How do digital pianos work? [closed]

I know somehow it combines different harmonics to synthesize notes, but I don't exactly know how this is implemented.
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66 views

Realization of network function and positive real function

I just studied 'network realizibility theory' from 'Franklin F.kuo's ' book and it mainly talks about postive real functions from start to finish and to me what I understand that for a function to be ...
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35 views

Transfer function synthesis problem

I think the answer is 1 and 2, so option C. But for the circuit to be realized, is the rule that there is a maximum of 1 degree difference between the highest and lowest order terms of the P (s) and Q ...
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Meaning of numbers inside parentheses in Lattice Synthesis Engine Utilization Report?

I'm using Lattice Radiant 2.0 to synthesize a design. In the "Synthesis Utilization Report file", I see the following line: ...
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21 views

Is it possible to specify a script that should be executed as soon as synthesis starts in Synopsys Synplify?

The Synopsys Synplify Pro is used internally to carry out synthesis in Libero and probably other places. Is there a method to assign a tcl or python script to be executed just before or just after ...
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How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...
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41 views

SDC Constraints for digitally noise filtered CLOCK and DATA inputs

I need help if my SDC constraints are correct for a digitally noise filtered CLOCK and DATA inputs. I'm not sure if CLK3 grouping and create_clk CLK2 are correct. I would like to know on how to make a ...
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65 views

Bit flipped and back on FPGA

I have a weird problem on a Xilinx Ultrascale FPGA (although I think the board shouldn't matter). I have an array called logic[2047:0] enabled which is basically a ...
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1answer
104 views

Difference between always @ block and @ statement in Verilog and SystemVerilog

I am new to SystemVerilog. I have not across the statement @(posedge clk) before. I would like to know how this statement is different from the ...
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105 views

Inferring a pipelined divider in Verilog

I want to synthesize an integer divider in Verilog to divide 16-bit integers by 8-bit integers. I assume that the compiler will be way more clever than me when it comes to implementing the details of ...
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324 views

How resolve “logic” is an unknown type error in Vivado synthesis? [closed]

the verilog code at output logic PIPE_PCLK;
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Synthesis error in module using Verilog (Xilinx Vivado 2015.4)

I am facing an issue with the post-synthesis implementation of a special Serial-In-Serial-Out kind of buffer. It receives inputs and stores them in registers and can later output the stored inputs. ...
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79 views

Why do block RAMs have synchronous reading instead of async reading?

I'm programming FPGA boards (Artix 7 to be exact) and I recently noticed that, in order to be synthesized into block RAM, an array of storage must have synchronous reading, otherwise it will only be ...
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118 views

Transfer Verilog Code to For Loops Syntax

I have built an block that does simple moving average on a "factor" numbers in the vector.. and its works good for my needs. My problem with it that I think my syntax is bit dumb. I have an array and ...
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1answer
46 views

RISC-V Arithmetic Shift vs Operator “<<<”

I'm new at learning Verilog so some of my practices are based on already existing codes. I was reading the RISC-V implementation of arithmetic shift and didn't quite understand why it's that way when ...
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137 views

Does frequency scale proportionally?

Suppose that I am working with an FPGA and I synthesize two architectures A and B. A achieves a maximum frequency of 60 MHz on FPGA and B achieves 50 MHz on the same FPGA. Now suppose that I ...
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1answer
180 views

How to constrain delay in the circuit without a clock?

Background: The image below is, in essence, a simplified schematic of the, so called asynchronous state machine (AM_fsm.v). The design does not have any clock input signal. It contains many SR latches ...
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76 views

Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
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90 views

Embedding data in RAM during synthesis

I have designed a CPU that works in simulation using Verilator, and would now like to test it in hardware on an FPGA. A quick way to get to the testing phase would be to embed a program to run on the ...
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254 views

VHDL optimization

If I need to perform the same function on a number of different signals in a VHDL design will placing them in a vector affect synthesis optimization in any way? As as example, let's say I'm trying to ...
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169 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
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1answer
195 views

How to specify a value for each bit of the reg in Verilog?

I want to declare a reg of 8 bits and set the value for each one of the bits separately (based on another "counter" reg) inside ...
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143 views

Can I replace the transistor in this circuit (Esaki oscillator) with a Zener diode?

Can I replace the transistor in this circuit (Esaki oscillator) with a Zener diode?
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1answer
172 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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Detect the first rising edge of 3 input signals

I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected. Is there a digital circuit from logic gates, flip flop that ...
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71 views

vhdl synthesizable code

I have a CPLD XC9536XL-10VQG44C. On this CPLD I have one input "INPUT_4", one clock at 4MHz "clock" and 2 outputs "OUTPUT4_1" and "OUTPUT4_2", I also have 1 LED to drive that takes the same value than ...
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268 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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70 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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2answers
476 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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1answer
223 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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173 views

VHDL SLV dynamic width slice assignment

I have some code that takes in 2^X samples and outputs 2^Y samples, where X and Y are integers and Y is less than X. So for example X=6,Y=4, I ingest 64 samples and output 16 samples. As of right ...
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40 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
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136 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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93 views

Elaborating a VHDL design with Generics

So this query is related to DC synthesis compiler for digital design. I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters ...
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188 views

How many flip-flips would this code require?

H, I'm trying to understand the below code what how many FFs would be required when synthesis. TEST1. ...
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1answer
400 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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2answers
356 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
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58 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
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91 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments? I ...
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3k views

How to read multiple Verilog files in Design Compiler?

I'm trying to read multiple Verilog files in Design Compiler, but I have found just one command, read_verilog. It can read only one file at a time. If I've got ...
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1answer
79 views

Expressions in Verilog module instantiations

If I have the following verilog module definition: module foo ( input a, output b ); assign b = !a; endmodule And then I instantiate it within another ...
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720 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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682 views

Is the initial block in Verilog sythesizable?

I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-...
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114 views

Is there a way to convert BSDL format to synthesizable verilog?

I have a BSDL file for a device for which I need to generate test patterns through an FPGA. I learnt that BSDL is a subset of VHDL but the file looks like it describes the hardware of the DUT. I know ...
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2answers
230 views

question about Vivado synthesis and implementation

I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and ...
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2answers
96 views

Analysis of Ringing Oscillator

I am looking at an analog synthesizer circuit the design of which incorporates several "ringing oscillators", which look like this: I understand that this is a resonant system that enters oscillation ...
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46 views

How does synthesis tool handle the ports either driven by or to a module that is empty(Black Box)?

I have a design that instantiates a Memory and a Ring oscillator which I am excluding from synthesis by making them black boxes.(Not specifying explicitly, but instantiating an empty module with only ...

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