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Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

6
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3answers
948 views

Detect the first rising edge of 3 input signals

I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected. Is there a digital circuit from logic gates, flip flop that ...
1
vote
1answer
582 views

Sending SPI signals to the Flash Memory through verilog FPGA controller, but not receiving anything from it, why does it happens?

As a school project I want to write a very simple controller for a flash memory in a IC board. The FPGA chip is Altera 5CEFA4F23C8 and the flash is MX25L3206E. I did an effort to produce the SCLK, SI ...
1
vote
2answers
751 views

How to read multiple Verilog files in Design Compiler?

I'm trying to read multiple Verilog files in Design Compiler, but I have found just one command, read_verilog. It can read only one file at a time. If I've got ...
0
votes
1answer
60 views

vhdl synthesizable code

I have a CPLD XC9536XL-10VQG44C. On this CPLD I have one input "INPUT_4", one clock at 4MHz "clock" and 2 outputs "OUTPUT4_1" and "OUTPUT4_2", I also have 1 LED to drive that takes the same value than ...
0
votes
1answer
62 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
3
votes
0answers
594 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
0
votes
1answer
54 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
1
vote
3answers
76 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
0
votes
2answers
91 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
0
votes
1answer
183 views

Understanding data-flows graph

I've been trying to improve my understanding of optimization of digital circuit. With such goal in mind I've been studying from this book. I've been trying to understand mathematically the meanings of ...
1
vote
1answer
133 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
0
votes
1answer
55 views

VHDL SLV dynamic width slice assignment

I have some code that takes in 2^X samples and outputs 2^Y samples, where X and Y are integers and Y is less than X. So for example X=6,Y=4, I ingest 64 samples and output 16 samples. As of right ...
3
votes
1answer
60 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
0
votes
0answers
23 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
0
votes
1answer
33 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
2
votes
1answer
119 views

Synopsys Synthesis with underlying modules as gate libraries

I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module. With setting -hierarchy option in write_file, I get all the modules ...
1
vote
1answer
249 views

How to save and reuse outputs of different steps of synthesis in Design Compiler?

Is it possible to save outputs of different steps of synthesis in Design Compiler and load them later? For example, is it possible to do analyze, save the output of ...
0
votes
0answers
85 views

Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
0
votes
2answers
177 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
0
votes
0answers
62 views

Elaborating a VHDL design with Generics

So this query is related to DC synthesis compiler for digital design. I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters ...
0
votes
1answer
122 views

How many flip-flips would this code require?

H, I'm trying to understand the below code what how many FFs would be required when synthesis. TEST1. ...
6
votes
1answer
432 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
4
votes
0answers
170 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
0
votes
1answer
52 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
0
votes
1answer
56 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments? I ...
3
votes
3answers
819 views

Xilinx XST won't infer block ram

I'm having trouble getting the design of my FPGA 80's computer to fit on a Papilio Duo board which is a Spartan 6 - xcs6slx9. The problem stems from RAM being inferred as distributed instead of block....
0
votes
1answer
26 views

Expressions in Verilog module instantiations

If I have the following verilog module definition: module foo ( input a, output b ); assign b = !a; endmodule And then I instantiate it within another ...
0
votes
1answer
224 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
0
votes
1answer
47 views

Is there a way to convert BSDL format to synthesizable verilog?

I have a BSDL file for a device for which I need to generate test patterns through an FPGA. I learnt that BSDL is a subset of VHDL but the file looks like it describes the hardware of the DUT. I know ...
0
votes
2answers
121 views

question about Vivado synthesis and implementation

I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and ...
4
votes
1answer
290 views

What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is ...
2
votes
3answers
1k views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns (...
0
votes
2answers
2k views

Xilinx ISE Synthesis taking too long

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly. Therefore, I tried to move to the ...
0
votes
2answers
67 views

Analysis of Ringing Oscillator

I am looking at an analog synthesizer circuit the design of which incorporates several "ringing oscillators", which look like this: I understand that this is a resonant system that enters oscillation ...
0
votes
0answers
87 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
0
votes
1answer
38 views

How does synthesis tool handle the ports either driven by or to a module that is empty(Black Box)?

I have a design that instantiates a Memory and a Ring oscillator which I am excluding from synthesis by making them black boxes.(Not specifying explicitly, but instantiating an empty module with only ...
5
votes
3answers
771 views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
3
votes
2answers
1k views

Using Webpack from the command line, but without a project file?

I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's ...
0
votes
1answer
55 views

Synthesizable averaging scheme

Looking for a clever solution (writing in Verilog) Let’s say I have two 8 bit values, and each value has an 8 bit score, for a total of four inputs, and I want to combine the two values into one 8 ...
1
vote
1answer
175 views

Initialising FPGA internal RAM from file

I have a design that relies heavily on internal dual port RAM found in the FPGA and I want to take advantage of the fact that blockram can have power-on initial values to populate all this memory with ...
0
votes
0answers
106 views

How to map a C/C++/Python code to an Intel FPGA?

I have a piece of code that mainly consists of matrix-matrix and matrix-vector multiplications, but has other operations too. I have written my code in both Python and C and would like to map it to an ...
3
votes
2answers
1k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
0
votes
1answer
104 views

efficiency and speed in image processing with FPGA

Hi I have been writing a code in VHDL for some image processing. However, due to some reasons I have not yet determined the sythesis does not stop. I suspect that efficiency of the code is not as much ...
2
votes
3answers
758 views

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
0
votes
1answer
29 views

How to implement Quartus IP cores using ALMs?

This is a follow-up question on this, where I had asked about how one can implement multiplications without using any DSPs of the FPGA. Now, I would like to know whether one can implement Quartus IP ...
0
votes
2answers
117 views

Design a circuit from logic gates, flip flops and/or multiplexers

I would like to create a simple circuit from logic gates, flip-flops (no RLC components) to do the following task: This circuit has 5 inputs (4 positive real-valued signals \$x_1, x_2, x_3, x_4\$ and ...
2
votes
1answer
216 views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
1
vote
1answer
78 views

How to partition a combinational circuit into parts with equal delay?

I have a huge combinational circuit with a large delay. I like to partition this design (based on delay) into smaller parts and later, convert it to a sequential pipelined circuit. Are any of the ...
3
votes
1answer
434 views

How to find power, delay, and area of a synthesized design using Design Compiler?

I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without ...
2
votes
1answer
244 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...