Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

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1answer
244 views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
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1answer
82 views

How to partition a combinational circuit into parts with equal delay?

I have a huge combinational circuit with a large delay. I like to partition this design (based on delay) into smaller parts and later, convert it to a sequential pipelined circuit. Are any of the ...
3
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1answer
490 views

How to find power, delay, and area of a synthesized design using Design Compiler?

I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without ...
2
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1answer
269 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...
1
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1answer
457 views

Ungrouping synthesized modules in Synopsys Design Compiler for better synthesis results

I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A ...
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4answers
5k views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
3
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4answers
369 views

Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something? this is the truth table ...
2
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1answer
1k views

how to get the timing report register to register and input to output in STA?

I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths. Input to register Register to register Register to output Input to output Practically, I want to ...
2
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1answer
645 views

Partially associated formal cannot have actual OPEN in VHDL under Vivado

I'm getting the error "[Synth 8-2519] partially associated formal q8 cannot have actual OPEN" - this error is for the line Q8(0) => OPEN, and all similar OPEN ...
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1answer
103 views

High Level Synthesis of a Microprocessor [closed]

I am working at an FGPA shop right now using Xilinx FPGAs. I do not have a ton of experience with designing logic, especially when it comes to microprocessors. One of the big movements my team is ...
2
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1answer
1k views

While loop in VHDL

To check the synthesisability of while loop, I created one hypothetical vhdl code as follows. ...
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1answer
492 views

removing inout from port arrays

This question is in the context of using verilog/systemverilog for synthesizable RTL. I have some vector signals that are going across module boundaries that are currently defined as inout ports. The ...
4
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1answer
710 views

Handling inferred clocks during RTL Synthesis

I am trying to synthesize a design in VHDL into a ProASIC3 FPGA using the Synplify Pro tool. The synthesis report gives me the following warning on inferred clocks. ...
17
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3answers
18k views

VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc. I use std_logic at top level ports, but internally I was using ranged integers all over the place. ...
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2answers
72 views

How to effectively determine if given truth table is equal to another one (when we take into account that they can differ at order of inputs)

I'm working on some project which is not really related to digital circuits but rather boolean algebra analysis. In some point I stucked at algorithmic or maybe data structure problem: How to ...
2
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2answers
1k views

VHDL: Are if-else and case statements supposed to synthesize the same hardware?

The if-else and case statements are equivalent. The later maybe easier to read when we have a lot of possibilities being checked. A conditional is supposed to infer mux in hardware. However, there is ...
0
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1answer
155 views

VHDL Flip Flop Syntax Error

I'm trying to figure out how to VHDL, and am having some difficulties writing a simple flip flop. I want a T flip flop that runs strictly off of the clock, changing state every time it receives a ...
0
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1answer
1k views

How to successfully trigger an ILA core in Vivado

I am trying to debug my VHDL project in Vivado 2014.03 on a KC705. My project consists of multiple VHDL modules implemented as custom IP cores, which are connected in a block design. I selected <...
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0answers
332 views

When is VHDL code considdered compile time

EDIT: I am working with a lookup table which is generated in compile time. Is this compile time code: because sinus_table is a constant or because any ...
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1answer
56 views

Verilog Synthesis Automation

I am trying to synthesize around 3000 different modules. The verilog codes for these were generated using a python code. Is it possible to automate the synthesis and compile the results such as ...
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1answer
2k views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
5
votes
1answer
904 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
2
votes
1answer
313 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...
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0answers
1k views

Speed up Vivado Implementation

In Vivado, implementation of my projects can take a while especially if I use debug cores. What can I do to make implementation faster? I tried the "RuntimeOptimized" constraint and it made no ...
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0answers
211 views

VHDL: how do you perform asynchronous data transfer between entities?

How do you implement the following sort of functionality in VHDL that is synthesizable? ...
2
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1answer
480 views

Vivado HLS: Is it Xilinx specific?

I've been using Vivado HLS (High-Level Synthesis) for the last months and making designs for a Xilinx's ZedBoard. Now I will probably have to work with a FPGA from another vendor and I don't know if ...
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1answer
80 views

DC compiler, synthesis, terminology

In the DC compiler user manual the following term is reported when talking about a command. Use the set_driving_cell command to specify drive characteristics on ports that are driven by cells in ...
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1answer
285 views

Hierarchichal netlist vs Flatten netlist?

I'm learning about synthesis of VHDL code and I have the doubt about the advantages and disadvantages of Hierarchichal vs Flatten netlists. The first is like interconnection of blocks and the second ...
2
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4answers
101 views

Little change in Verilog module results in high change in power consumption (Synopsys Design Compiler)

I am comparing two Verilog designs: Design (1): A top module that is driven by a clock running at 50MHz, which is the main system clock. Design (2): The same top module as in Design (1) with one ...
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0answers
187 views

Minimum AND gates for 4 input-2 output functions

It seems that Karnaugh maps and Quine–McCluskey algorithm are used to minimize the general number of gates to represent some truth table (boolean function) with $n$ inputs (usually small $n$) and one ...
0
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1answer
228 views

What is the real speed of my system implemented on FPGA? How to check this value?

I created an FPGA system on ModelSim (a simple algorithm that calculate an equation and save on-chip), synthesized with Quartus Prime, then downloaded to my DE1-SOC. My intention is to compare my ...
2
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2answers
2k views

XST Verilog - Casting real to integer constants

When I try to synthesize the following Verilog code using Xilinx XST, I get the error, "Unsupported real constant". If I try wrapping that expression in an $rtoi function, XST gives a different error:...
11
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2answers
25k views

How can I specify “don't care” signals in VHDL?

In Logic Design courses we all learned that it is possible to minimize a logic function, for example by using a Karnaugh map or the Quine–McCluskey algorithm. We also learned that "Don't Care" values ...
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1answer
90 views

Cycle-Time/Latency optimization in synthesis of digital circuit question

I've been trying to build a solid understanding of digital synthesis. And I've found a useful book (this one) for it, specifically I'm into "Architectural optimization" now (section 4.5). In such ...
2
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1answer
4k views

Assigning the different value to parameters in Generate block in Verilog

I want to instantiate a module having parameters using generate block. But I want to assign different values to parameter for different instantiation of the module. For example: This is my module ...
0
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2answers
1k views

In Xilinx Vivado, simulation mismatch between behavioral and post-synthesis implementations

While designing PISO (parallel in serial out) in Xilinx Vivado using Verilog, the output waveform of the behavioral simulation (RTL-level, pre-synthesis) shows correct (desired output) value but post-...
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1answer
411 views

Why isn't this decoder being inferred as a LUT?

I'm trying to model a stack which has push and pop operations. ...
1
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1answer
1k views

Is there any tool that can create a logic circuit equivalent to some Verilog code?

For the purpose of learning, I would like to know if there is any tool (free or commercial) that can synthesize some Verilog code and produce the equivalent logic circuit. Example : ...
9
votes
2answers
8k views

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable ...
0
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1answer
74 views

Simple methods for synthesizing circuits [closed]

I'm studying systems engineering and I am currently attending a course in computer architecture. In our career, we don't have much training in regard to hardware, so we find very hard to synthesize ...
1
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1answer
204 views

Is RAM with read ahead (Look ahead) possible?

Is it possible to efficiently infer a RAM with "peek" ports apart from the usual standard ports? A 32-bit x 4 RAM might have a peek port to peek at data just ahead of the current data being accessed ...
2
votes
1answer
111 views

non static error in Precision RTL

I'm writing a VHDL code for an integer to float converter using variables. I have simulated it and the results match expectations. However, when looking to compile and synthesize using Precision RTL ...
3
votes
1answer
449 views

Power categories in ASIC design (Design Compiler)

I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module. In the power reports there are three power categories specified : Switching Power Internal Power ...
0
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2answers
543 views

Introduce delays of alternating value for synthesis on hardware

My question here is with reference to this question previously asked. Currently, I am able to generate delays for each signal as desired. Next, I want to generate different delays for alternate ...
3
votes
2answers
4k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
1
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2answers
2k views

Unconnected port warning on reset port in asynchronous register in Vivado

I've been trying to synthesis this register model. Its simulation in ModelSim is correctly fine. However, when synthesis, it always yields warnings: [synth 8-3331] design register1 has unconnected ...
0
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1answer
166 views

operand isolation in RTL

I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
3
votes
6answers
3k views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
0
votes
1answer
187 views

How to borrow time in STA?

Now I'm trying to study about time borrow as refer to here: "Time Borrowing": Static Timing Analysis (STA) basic (Part 2). Especially, I'm looking at this: How to get time and how to get this not ...
2
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1answer
161 views

How to define a false path using design entities

I'm trying to do a timing analysis on a design I wrote in VHDL. The design looks like this: And the mux's are only activated in a way that the path is either: in -> circuit1 -> circuit2 -> out in -...