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Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

2
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0answers
214 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
7
votes
2answers
6k views

What is the difference between reg and wire after synthesizing?

Assuming i have these two codes: module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule and the second one ...
8
votes
4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
0
votes
1answer
740 views

How is the difference between sdf back annotation and spf back annotation?

I'm a rtl engineer. I'm confused between the difference of sdf and spf back annotation. As I know sdf came from STA( PT) and SPF came from STAR-RC. So In my experiance, the sdf used to timing close ...
1
vote
2answers
645 views

In Verilog Synthesis, Creating several Instantiation of a Module is the same than instantiate several modules with same content?

I wonder if there is a difference between creating several instantiation of a single module and to instantiate different modules (with identical hardware code) only one time. For example, I want to ...
-2
votes
1answer
184 views

Explanation of how to create circuit from transfer function

So I'm in this lab course that must be taken concurrently with the main upper div circuits class, but we were assigned a lab that our professor did not explain and that the lab manual does not explain....
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1answer
2k views

How to properly describe a Math Equation in Verilog to be synthesizable?

I have not been able to find a book or information in internet, about the correct way to describe a Math Equation in Verilog. With the correct way I mean for example, how to analyze the equation and ...
0
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2answers
233 views

Cadence SoC encounter

I am trying to create the layout of my design for an 8 bit multiplier accumulator in SoC Cadence encounter tool. After routing the design using wroute command, the ...
1
vote
1answer
730 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...
2
votes
0answers
225 views

Xilinx unconstrained path analysis

I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis. ...
2
votes
0answers
209 views

Does sequential clock gating useful? [closed]

I know there is clock gating method that xor-ing the input and output of FF, and use that signal as clock enable. (figure 1, i'll call it xor-ing from now) I'm now studying sequential clock gating. I ...
2
votes
2answers
160 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...
1
vote
1answer
116 views

Some pointers on how to begin VHDL writing

I'm currently doing some tutorials and reading some books on how to write VHDL. As I'm curious and learn better with hands-on tutorials I'm going to start implementing my projects that will serve me ...
1
vote
1answer
664 views

Synthesis tool free-source [closed]

I'm currently learning VHDL and to simulate the code that I write I found out GHDL (open-source), which I haven't tried yet but I think does what it needs to be done. In order to synthesize the VDHL ...
1
vote
1answer
3k views

loop synthesis vhdl

Suppose we have an iterative algorithm like: r(j) := f(r(j-1)) r(0) := value And that vhdl i implemened a process for such algorithms (assuming a bit of ...
1
vote
1answer
62 views

Product-of-Sums Synthesis

Alright, have another one which the solutions manual is vague on. I have to reduce \$f =(x1+x3+x4)(x1+x2'+x3)(x1+x2'+x3'+x4)\$. Right in the first step, though, the solution does something I don't ...
1
vote
2answers
912 views

Constant value required for VHDL array indexing?

I basically have a line like this in a vhdl code. ...
1
vote
1answer
623 views

How to concatenate unsized parameters

My verilog module is instantiated in a VHDL top entity. I want to pass integer design-time configurations to the verilog module. These are the initial configurations that should appear at reset. <...
2
votes
1answer
314 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...
2
votes
0answers
163 views

Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
4
votes
1answer
1k views

VHDL functions with generic or “run time variable”, synthesis issues

I have been thinking about functions in VHDL. If we have a function we could have both a function where we pass a "generic" (i.e. a fixed parameter known at compilation time) and a variable/signal (...
1
vote
0answers
113 views

Synthesis error when using “-opt_mode area” in Xilinx XST

I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...
4
votes
1answer
374 views

How to read Map-Report in FPGA Synthesis Tools

I have this Map-Report piece product by Lattice Diamond: ...
1
vote
1answer
99 views

Nonlinear increase in logic utilization for FPGA design

I am creating a design using the Altera Stratix V GX-series FPGA. For host device communication we are using the PCIe x8 interface. The interface itself takes up 3,058 ALMs (out of available 234,720)...
1
vote
1answer
191 views

how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it ...
0
votes
2answers
2k views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
0
votes
1answer
85 views

data bus power consumption

In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing: use a mux for the read data of each master, so that if the ...
1
vote
1answer
885 views

This design does not fit into the number of slices available in this device

Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum ...
0
votes
1answer
2k views

getting started fpga video processing? [closed]

Hi i am a electrical engineering student first year since we study only microcontrollers and processors I have decided to learn more about fpga (I have a little experience with spartan 3e vhdl) . My ...
0
votes
1answer
553 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
0
votes
1answer
171 views

VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error: Signal sig_enable cannot be synthesized, bad synchronous ...
2
votes
3answers
501 views

Thought Process on Designing Circuits

I'm currently in my second year of computer engineering. I've taken circuit analysis courses and have a good general understanding of components, and a little bit of digital design, however, I'm very ...
1
vote
1answer
473 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
1
vote
2answers
182 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
12
votes
3answers
2k views

Why does digital equipment have more latency than analogue?

Is the explanation that the digital equipment takes longer to propagate? For instance, a software synthesis is very slow compared to a hardware synthesis.
1
vote
1answer
2k views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
1
vote
1answer
255 views

Boolean Network Simplification using Satisfiability Don't care Conditions

I couldn't really understand how SDC conditions are applied to minimize the following Boolean Network from Giovanni De Micheli's slide I am studying. Given: $$x=a'+b$$ $$y=abx + a'cx$$ Minimize \$...
1
vote
1answer
159 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
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votes
3answers
322 views

How to design a circuit using inverting op-amp when input-output relation equation is given?

Like this: $$V_0 = 5V_1 - 3V_2 + \frac{V_3 + V_4}{2} - V_5$$ I know about the transfer function but I am not able to make circuits from these relation and I am not able to find it in any book.
0
votes
1answer
4k views

Removing warning FF/Latch trimming

I have a 16 bit signal, for me only the last 4 bits are important and the first 12 bits are always "0", so I'm doing nothing with the first 12 bits and in the end it goes out of my component to next ...
3
votes
3answers
3k views

Open Source verilog synthesizer

I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
0
votes
2answers
549 views

Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is: ...
3
votes
1answer
531 views

How to embed a clock oscillator inside a digital block? Specifically, how is this defined for Synopsys DC?

I have to embed a clock oscillator inside my logic block for layout purposes. It's not an option to leave this block out and just bring the clock port in. Is there any way to define an internal net as ...
0
votes
1answer
313 views

Synthesis of Verilog code in Cadence

I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in ...
4
votes
1answer
783 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
1
vote
0answers
251 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
0
votes
2answers
310 views

System verilog on Quartus synthesis issue

module blockingbad(input logic clk,a,b,c,output logic y); logic x; always_ff @(posedge clk) begin y=x|c; x=a&b; end endmodule For ...
5
votes
1answer
967 views

Empty Netlist Vivado Design Suite

I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem ...
10
votes
3answers
9k views

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
1
vote
1answer
273 views

Specify Xilinx FPGA DSP placement with Vivado

How can I, either in the RTL or in a constraint file, map specific DSP blocks to certain locations? I see that DSPs are labeled by site, with names like DSP48_X5Y30 and I'd like to be able to map a ...