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Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

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1answer
4k views

VHDL: when is process sensitivity list triggered?

In VHDL simulation, there is a concept of "delta time," which is loosely interpreted as "group of events triggered by the previous delta time." After a change, once all cascading changes have settled, ...
3
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5answers
4k views

Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst

I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
2
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1answer
164 views

Where did my state machine go?

Working on some VHDL I for Xilinx virtex parts, I found that the code I inherited had attempted to implement user encoding for the state variables used in the various state machines in the design. The ...
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1answer
527 views

Part select in verilog

I am a bit confused because of a odd situation in part select operator in verilog. I had read about part select and vector part select operators. But there is a situation where I am having ...
0
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1answer
248 views

Verilog Netlist and verilog file not justifying each other

i generated a verilog netlist file with the help of a test case for 2-1 encoder .To test the netlist i draw the schematic diagram and try to find the output.I can't upload the pic of schematic which i ...
2
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1answer
664 views

Making combinational component synchronous

I have an combinational entity that is implemented with a lot of combinational logic. Synthesis (using Xilinx ISE) indicates: Maximum combinational path delay: 62.367ns When placed into a ...
-3
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1answer
2k views

LHS of always block in verilog need to be reg, but index of array in LHS of always block cannot be a reg, is it true? [duplicate]

I am trying to synthesize a verilog file with some part of code like this(obviously i hadn't declared module and other input and output variables) ...
1
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1answer
20k views

Read and write values in Multidimensional arrays in verilog

How can we read and write values in a multidimensional array in verilog, i had read in this link regarding different operations that can be done on multidimensional array. like if there is a part of ...
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3answers
3k views

How many harmonics are needed to produce a proper square/saw/triangle/etc wave?

I'm new to software sound synthesis, but I have a question that I can't seem to find the answer to. I understand that, for example, a square wave at 100 Hz has its third harmonic at 300 Hz with 1/3 ...
2
votes
1answer
4k views

Memory modelling and Memory module in Verilog synthesis

I am using a synthesis tool and when I am synthesizing a verilog file module test(); reg reg1; reg [1:0] reg2; reg reg3 [1:0]; reg [1:0] reg4 [0:4]; endmodule ...
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0answers
331 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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2answers
4k views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
2
votes
2answers
2k views

Transfer function synthesis

Is there a design methodology to create a circuit that implements a specified transfer function? I know that there are automatic top-down design flows in logic design where you describe a function ...
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2answers
59 views

value of variable in Veriog not defined

I am analyzing a verilog file for always. in this, what should be the value of "en" in case first and then in second? ...
2
votes
1answer
865 views

Understanding Verilog Netlist

This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic ...
1
vote
1answer
5k views

Maximum and Minimum delay of combinational logic circuits

I am preparing for my exam and I am stuck with this past year question: In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same ...
2
votes
1answer
783 views

What does non-combinational area represent in synopsys design compiler

I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
5
votes
1answer
718 views

Why does Synplify error out whereas Xilinx XST passes without problems?

I have a project with several inferred dual port RAM blocks. The code for this dual port RAM is as follows: ...
2
votes
1answer
5k views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
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votes
1answer
705 views

Synthesis error for generated IP express single port RAM with shift register design

I have generated single port RAM (DP8KC primitive) from IP express using Lattice tool and then I am instantiating with 48 bit shift register, which is at input side. The output of shift register is ...
2
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2answers
407 views

How to generate wait until division is over in verilog?

I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to ...
3
votes
2answers
1k views

Synthesize VHDL into discrete TTL integrated circuits

I've got a small project in VHDL (fully working in a Xilinx FPGA) and I would like to implement it using an old-school printed circuit board and discrete TTL integrated circuits, in the spirit of ...
0
votes
1answer
948 views

Why is ISE / XLS is mapping a signal to the global clock GCK0?

I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this: ...
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1answer
484 views

Can I create a verilog file to both simulate and synthesize?

Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one ...
4
votes
1answer
92 views

Synthesis using Synopsis

I'm using Synopsys to synthesize designs. I've noticed that when I synthesize exactly the same design several times, I get different synthesis reports. When I launch the tool for the first time, ...
3
votes
1answer
2k views

Unsigned addition overflow and synthesis

Let's say we have the following code where a, b and c are 3-bit wide representing unsigned ...
3
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2answers
593 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...
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2answers
580 views

about Synplify VHDL (code imported from Xilinx ISE)

Good day, Need some help. Start to work with Synopsys Synplify. Import my Xilinx ISE project (fully work). Try to run and receive - "No matching overload for to_integer" for this line ...
6
votes
3answers
701 views

Which synthesis tools support VHDL libraries?

On various places across the net, I read that (some) synthesis tools do not respect VHDL libraries. These tools just throw all entities and packages into a single namespace, so that you cannot have <...
5
votes
3answers
295 views

What options do I have when synthesising control registers?

When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those? For instance: Do you keep them on their own clock ...