Questions tagged [synthesis]

Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.

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This design does not fit into the number of slices available in this device

Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum ...
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2k views

getting started fpga video processing? [closed]

Hi i am a electrical engineering student first year since we study only microcontrollers and processors I have decided to learn more about fpga (I have a little experience with spartan 3e vhdl) . My ...
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1answer
663 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...
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1answer
188 views

VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error: Signal sig_enable cannot be synthesized, bad synchronous ...
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3answers
521 views

Thought Process on Designing Circuits

I'm currently in my second year of computer engineering. I've taken circuit analysis courses and have a good general understanding of components, and a little bit of digital design, however, I'm very ...
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1answer
501 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...
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2answers
187 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...
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3answers
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Why does digital equipment have more latency than analogue?

Is the explanation that the digital equipment takes longer to propagate? For instance, a software synthesis is very slow compared to a hardware synthesis.
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1answer
2k views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
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1answer
261 views

Boolean Network Simplification using Satisfiability Don't care Conditions

I couldn't really understand how SDC conditions are applied to minimize the following Boolean Network from Giovanni De Micheli's slide I am studying. Given: $$x=a'+b$$ $$y=abx + a'cx$$ Minimize \$...
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1answer
170 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?
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3answers
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How to design a circuit using inverting op-amp when input-output relation equation is given?

Like this: $$V_0 = 5V_1 - 3V_2 + \frac{V_3 + V_4}{2} - V_5$$ I know about the transfer function but I am not able to make circuits from these relation and I am not able to find it in any book.
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Removing warning FF/Latch trimming

I have a 16 bit signal, for me only the last 4 bits are important and the first 12 bits are always "0", so I'm doing nothing with the first 12 bits and in the end it goes out of my component to next ...
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3answers
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Open Source verilog synthesizer

I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
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2answers
670 views

Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is: ...
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1answer
543 views

How to embed a clock oscillator inside a digital block? Specifically, how is this defined for Synopsys DC?

I have to embed a clock oscillator inside my logic block for layout purposes. It's not an option to leave this block out and just bring the clock port in. Is there any way to define an internal net as ...
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1answer
325 views

Synthesis of Verilog code in Cadence

I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in ...
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1answer
811 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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0answers
260 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
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2answers
356 views

System verilog on Quartus synthesis issue

module blockingbad(input logic clk,a,b,c,output logic y); logic x; always_ff @(posedge clk) begin y=x|c; x=a&b; end endmodule For ...
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1answer
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Empty Netlist Vivado Design Suite

I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem ...
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3answers
11k views

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
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1answer
284 views

Specify Xilinx FPGA DSP placement with Vivado

How can I, either in the RTL or in a constraint file, map specific DSP blocks to certain locations? I see that DSPs are labeled by site, with names like DSP48_X5Y30 and I'd like to be able to map a ...
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1answer
4k views

VHDL: when is process sensitivity list triggered?

In VHDL simulation, there is a concept of "delta time," which is loosely interpreted as "group of events triggered by the previous delta time." After a change, once all cascading changes have settled, ...
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5answers
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Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst

I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
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1answer
166 views

Where did my state machine go?

Working on some VHDL I for Xilinx virtex parts, I found that the code I inherited had attempted to implement user encoding for the state variables used in the various state machines in the design. The ...
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1answer
777 views

Part select in verilog

I am a bit confused because of a odd situation in part select operator in verilog. I had read about part select and vector part select operators. But there is a situation where I am having ...
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1answer
260 views

Verilog Netlist and verilog file not justifying each other

i generated a verilog netlist file with the help of a test case for 2-1 encoder .To test the netlist i draw the schematic diagram and try to find the output.I can't upload the pic of schematic which i ...
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1answer
700 views

Making combinational component synchronous

I have an combinational entity that is implemented with a lot of combinational logic. Synthesis (using Xilinx ISE) indicates: Maximum combinational path delay: 62.367ns When placed into a ...
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1answer
2k views

LHS of always block in verilog need to be reg, but index of array in LHS of always block cannot be a reg, is it true? [duplicate]

I am trying to synthesize a verilog file with some part of code like this(obviously i hadn't declared module and other input and output variables) ...
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1answer
20k views

Read and write values in Multidimensional arrays in verilog

How can we read and write values in a multidimensional array in verilog, i had read in this link regarding different operations that can be done on multidimensional array. like if there is a part of ...
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3answers
4k views

How many harmonics are needed to produce a proper square/saw/triangle/etc wave?

I'm new to software sound synthesis, but I have a question that I can't seem to find the answer to. I understand that, for example, a square wave at 100 Hz has its third harmonic at 300 Hz with 1/3 ...
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1answer
4k views

Memory modelling and Memory module in Verilog synthesis

I am using a synthesis tool and when I am synthesizing a verilog file module test(); reg reg1; reg [1:0] reg2; reg reg3 [1:0]; reg [1:0] reg4 [0:4]; endmodule ...
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0answers
368 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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2answers
4k views

Synthesis timing summary in Xilinx tool (ISE)

I'm getting the following timing summary from the synthesis: ...
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2answers
3k views

Transfer function synthesis

Is there a design methodology to create a circuit that implements a specified transfer function? I know that there are automatic top-down design flows in logic design where you describe a function ...
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2answers
61 views

value of variable in Veriog not defined

I am analyzing a verilog file for always. in this, what should be the value of "en" in case first and then in second? ...
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1answer
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Understanding Verilog Netlist

This might be a out of stand question.I am trying to understand a verilog netlist for 1 bit adder and make schematic out of it.But as i am very new to Verilog, though can understand some basic ...
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1answer
5k views

Maximum and Minimum delay of combinational logic circuits

I am preparing for my exam and I am stuck with this past year question: In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same ...
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1answer
908 views

What does non-combinational area represent in synopsys design compiler

I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to ...
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1answer
726 views

Why does Synplify error out whereas Xilinx XST passes without problems?

I have a project with several inferred dual port RAM blocks. The code for this dual port RAM is as follows: ...
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1answer
5k views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
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1answer
741 views

Synthesis error for generated IP express single port RAM with shift register design

I have generated single port RAM (DP8KC primitive) from IP express using Lattice tool and then I am instantiating with 48 bit shift register, which is at input side. The output of shift register is ...
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2answers
421 views

How to generate wait until division is over in verilog?

I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to ...
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2answers
2k views

Synthesize VHDL into discrete TTL integrated circuits

I've got a small project in VHDL (fully working in a Xilinx FPGA) and I would like to implement it using an old-school printed circuit board and discrete TTL integrated circuits, in the spirit of ...
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1answer
989 views

Why is ISE / XLS is mapping a signal to the global clock GCK0?

I've synthesized a design for a Coolrunner II CPLD. I intend to use the CPLD's internal clock. I have an input named CLK. I look at the fitter report and I see this: ...
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1answer
529 views

Can I create a verilog file to both simulate and synthesize?

Recently I was reading a Verilog study book. I finally realized that a Verilog file may not be synthesizable, because some Verilog statements are for simulation use only. But I'm too lazy to make one ...
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1answer
95 views

Synthesis using Synopsis

I'm using Synopsys to synthesize designs. I've noticed that when I synthesize exactly the same design several times, I get different synthesis reports. When I launch the tool for the first time, ...
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1answer
2k views

Unsigned addition overflow and synthesis

Let's say we have the following code where a, b and c are 3-bit wide representing unsigned ...
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2answers
624 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...