Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

9
votes
2answers
8k views

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable ...
0
votes
2answers
550 views

Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is: ...
8
votes
4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
3
votes
6answers
3k views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
3
votes
2answers
4k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
2
votes
0answers
330 views

When is VHDL code considdered compile time

EDIT: I am working with a lookup table which is generated in compile time. Is this compile time code: because sinus_table is a constant or because any ...
2
votes
1answer
263 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...
1
vote
1answer
80 views

How to partition a combinational circuit into parts with equal delay?

I have a huge combinational circuit with a large delay. I like to partition this design (based on delay) into smaller parts and later, convert it to a sequential pipelined circuit. Are any of the ...
1
vote
1answer
2k views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...
1
vote
1answer
20k views

Read and write values in Multidimensional arrays in verilog

How can we read and write values in a multidimensional array in verilog, i had read in this link regarding different operations that can be done on multidimensional array. like if there is a part of ...