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Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

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751 views

How to read multiple Verilog files in Design Compiler?

I'm trying to read multiple Verilog files in Design Compiler, but I have found just one command, read_verilog. It can read only one file at a time. If I've got ...
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2answers
72 views

How to effectively determine if given truth table is equal to another one (when we take into account that they can differ at order of inputs)

I'm working on some project which is not really related to digital circuits but rather boolean algebra analysis. In some point I stucked at algorithmic or maybe data structure problem: How to ...
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2answers
177 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
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1answer
119 views

Synopsys Synthesis with underlying modules as gate libraries

I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module. With setting -hierarchy option in write_file, I get all the modules ...
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1answer
582 views

Sending SPI signals to the Flash Memory through verilog FPGA controller, but not receiving anything from it, why does it happens?

As a school project I want to write a very simple controller for a flash memory in a IC board. The FPGA chip is Altera 5CEFA4F23C8 and the flash is MX25L3206E. I did an effort to produce the SCLK, SI ...
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1answer
60 views

vhdl synthesizable code

I have a CPLD XC9536XL-10VQG44C. On this CPLD I have one input "INPUT_4", one clock at 4MHz "clock" and 2 outputs "OUTPUT4_1" and "OUTPUT4_2", I also have 1 LED to drive that takes the same value than ...
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1answer
62 views

PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me <...
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1answer
33 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
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1answer
183 views

Understanding data-flows graph

I've been trying to improve my understanding of optimization of digital circuit. With such goal in mind I've been studying from this book. I've been trying to understand mathematically the meanings of ...
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0answers
170 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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0answers
594 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
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308 views

When is VHDL code considdered compile time

EDIT: I am working with a lookup table which is generated in compile time. Is this compile time code: because sinus_table is a constant or because any ...
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0answers
212 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
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0answers
224 views

Xilinx unconstrained path analysis

I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis. ...
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0answers
163 views

Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
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0answers
1k views

Speed up Vivado Implementation

In Vivado, implementation of my projects can take a while especially if I use debug cores. What can I do to make implementation faster? I tried the "RuntimeOptimized" constraint and it made no ...
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0answers
202 views

VHDL: how do you perform asynchronous data transfer between entities?

How do you implement the following sort of functionality in VHDL that is synthesizable? ...
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0answers
112 views

Synthesis error when using “-opt_mode area” in Xilinx XST

I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...
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0answers
251 views

Integrating third-party IP core using Xilinx command line tools

I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was ...
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0answers
328 views

Area vs Operating Frequency in asic synthesis

I am trying Synopsys dc tool for synthesizing my design. I tried different operating frequencies and observed the design area. Normally area should increase with increasing operating frequency but in ...
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0answers
23 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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85 views

Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
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62 views

Elaborating a VHDL design with Generics

So this query is related to DC synthesis compiler for digital design. I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters ...
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87 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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106 views

How to map a C/C++/Python code to an Intel FPGA?

I have a piece of code that mainly consists of matrix-matrix and matrix-vector multiplications, but has other operations too. I have written my code in both Python and C and would like to map it to an ...
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183 views

Minimum AND gates for 4 input-2 output functions

It seems that Karnaugh maps and Quine–McCluskey algorithm are used to minimize the general number of gates to represent some truth table (boolean function) with $n$ inputs (usually small $n$) and one ...