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Questions tagged [synthesis]

Transform a high-level design description (e.g. VHDL or Verilog) into a low-level implementation to be loaded onto programmable logic.

17
votes
3answers
18k views

VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc. I use std_logic at top level ports, but internally I was using ranged integers all over the place. ...
12
votes
3answers
2k views

Why does digital equipment have more latency than analogue?

Is the explanation that the digital equipment takes longer to propagate? For instance, a software synthesis is very slow compared to a hardware synthesis.
10
votes
3answers
9k views

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
10
votes
2answers
25k views

How can I specify “don't care” signals in VHDL?

In Logic Design courses we all learned that it is possible to minimize a logic function, for example by using a Karnaugh map or the Quine–McCluskey algorithm. We also learned that "Don't Care" values ...
9
votes
2answers
8k views

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable ...
8
votes
4answers
1k views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (...
7
votes
2answers
6k views

What is the difference between reg and wire after synthesizing?

Assuming i have these two codes: module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule and the second one ...
6
votes
3answers
946 views

Detect the first rising edge of 3 input signals

I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected. Is there a digital circuit from logic gates, flip flop that ...
6
votes
3answers
700 views

Which synthesis tools support VHDL libraries?

On various places across the net, I read that (some) synthesis tools do not respect VHDL libraries. These tools just throw all entities and packages into a single namespace, so that you cannot have <...
6
votes
1answer
431 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
5
votes
3answers
294 views

What options do I have when synthesising control registers?

When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those? For instance: Do you keep them on their own clock ...
5
votes
1answer
718 views

Why does Synplify error out whereas Xilinx XST passes without problems?

I have a project with several inferred dual port RAM blocks. The code for this dual port RAM is as follows: ...
5
votes
3answers
771 views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
5
votes
1answer
886 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
5
votes
1answer
961 views

Empty Netlist Vivado Design Suite

I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time. The behavior of my design is correct as verified by the pre-synthesis simulation. My problem ...
4
votes
1answer
672 views

Handling inferred clocks during RTL Synthesis

I am trying to synthesize a design in VHDL into a ProASIC3 FPGA using the Synplify Pro tool. The synthesis report gives me the following warning on inferred clocks. ...
4
votes
1answer
1k views

VHDL functions with generic or “run time variable”, synthesis issues

I have been thinking about functions in VHDL. If we have a function we could have both a function where we pass a "generic" (i.e. a fixed parameter known at compilation time) and a variable/signal (...
4
votes
1answer
92 views

Synthesis using Synopsis

I'm using Synopsys to synthesize designs. I've noticed that when I synthesize exactly the same design several times, I get different synthesis reports. When I launch the tool for the first time, ...
4
votes
1answer
776 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
4
votes
1answer
290 views

What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is ...
4
votes
1answer
4k views

VHDL: when is process sensitivity list triggered?

In VHDL simulation, there is a concept of "delta time," which is loosely interpreted as "group of events triggered by the previous delta time." After a change, once all cascading changes have settled, ...
4
votes
1answer
372 views

How to read Map-Report in FPGA Synthesis Tools

I have this Map-Report piece product by Lattice Diamond: ...
4
votes
0answers
170 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
3
votes
3answers
3k views

Open Source verilog synthesizer

I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
3
votes
3answers
819 views

Xilinx XST won't infer block ram

I'm having trouble getting the design of my FPGA 80's computer to fit on a Papilio Duo board which is a Spartan 6 - xcs6slx9. The problem stems from RAM being inferred as distributed instead of block....
3
votes
6answers
3k views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
3
votes
2answers
1k views

Synthesize VHDL into discrete TTL integrated circuits

I've got a small project in VHDL (fully working in a Xilinx FPGA) and I would like to implement it using an old-school printed circuit board and discrete TTL integrated circuits, in the spirit of ...
3
votes
4answers
328 views

Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something? this is the truth table ...
3
votes
2answers
1k views

Using Webpack from the command line, but without a project file?

I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's ...
3
votes
1answer
434 views

How to find power, delay, and area of a synthesized design using Design Compiler?

I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without ...
3
votes
2answers
4k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
3
votes
5answers
4k views

Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst

I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
3
votes
2answers
592 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...
3
votes
1answer
446 views

Power categories in ASIC design (Design Compiler)

I am currently working on the synthesis, with Synopsys' Design Compiler, of an AES encryption module. In the power reports there are three power categories specified : Switching Power Internal Power ...
3
votes
1answer
60 views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
3
votes
2answers
1k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
3
votes
1answer
530 views

How to embed a clock oscillator inside a digital block? Specifically, how is this defined for Synopsys DC?

I have to embed a clock oscillator inside my logic block for layout purposes. It's not an option to leave this block out and just bring the clock port in. Is there any way to define an internal net as ...
3
votes
0answers
593 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
3
votes
1answer
2k views

Unsigned addition overflow and synthesis

Let's say we have the following code where a, b and c are 3-bit wide representing unsigned ...
2
votes
3answers
498 views

Thought Process on Designing Circuits

I'm currently in my second year of computer engineering. I've taken circuit analysis courses and have a good general understanding of components, and a little bit of digital design, however, I'm very ...
2
votes
2answers
160 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...
2
votes
2answers
2k views

Transfer function synthesis

Is there a design methodology to create a circuit that implements a specified transfer function? I know that there are automatic top-down design flows in logic design where you describe a function ...
2
votes
3answers
758 views

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
2
votes
2answers
407 views

How to generate wait until division is over in verilog?

I am using a division module which has two signals other than inputs "go" to indicate start of division. "done" to indicate stop of division. It is taking approx 300 clock cycles for the division to ...
2
votes
1answer
592 views

Partially associated formal cannot have actual OPEN in VHDL under Vivado

I'm getting the error "[Synth 8-2519] partially associated formal q8 cannot have actual OPEN" - this error is for the line Q8(0) => OPEN, and all similar OPEN ...
2
votes
4answers
101 views

Little change in Verilog module results in high change in power consumption (Synopsys Design Compiler)

I am comparing two Verilog designs: Design (1): A top module that is driven by a clock running at 50MHz, which is the main system clock. Design (2): The same top module as in Design (1) with one ...
2
votes
3answers
1k views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns (...
2
votes
1answer
1k views

While loop in VHDL

To check the synthesisability of while loop, I created one hypothetical vhdl code as follows. ...
2
votes
2answers
1k views

VHDL: Are if-else and case statements supposed to synthesize the same hardware?

The if-else and case statements are equivalent. The later maybe easier to read when we have a lot of possibilities being checked. A conditional is supposed to infer mux in hardware. However, there is ...
2
votes
1answer
108 views

non static error in Precision RTL

I'm writing a VHDL code for an integer to float converter using variables. I have simulated it and the results match expectations. However, when looking to compile and synthesize using Precision RTL ...