Questions tagged [synthesis]

Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.

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Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
2 votes
1 answer
198 views

Embedding data in RAM during synthesis

I have designed a CPU that works in simulation using Verilator, and would now like to test it in hardware on an FPGA. A quick way to get to the testing phase would be to embed a program to run on the ...
3 votes
1 answer
1k views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
7 votes
1 answer
748 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
3 votes
2 answers
9k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
6 votes
2 answers
677 views

VHDL optimization

If I need to perform the same function on a number of different signals in a VHDL design will placing them in a vector affect synthesis optimization in any way? As as example, let's say I'm trying to ...
0 votes
1 answer
527 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
0 votes
1 answer
2k views

How to specify a value for each bit of the reg in Verilog?

I want to declare a reg of 8 bits and set the value for each one of the bits separately (based on another "counter" reg) inside ...
1 vote
1 answer
511 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
2 votes
2 answers
2k views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
6 votes
3 answers
2k views

Detect the first rising edge of 3 input signals

I have 3 input signals which are pulse waveforms The output is switch to high once once all 3 first rising edges of 3 inputs are detected. Is there a digital circuit from logic gates, flip flop that ...
0 votes
1 answer
139 views

vhdl synthesizable code

I have a CPLD XC9536XL-10VQG44C. On this CPLD I have one input "INPUT_4", one clock at 4MHz "clock" and 2 outputs "OUTPUT4_1" and "OUTPUT4_2", I also have 1 LED to drive that takes the same value than ...
0 votes
3 answers
780 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
0 votes
2 answers
2k views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
1 vote
1 answer
144 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
0 votes
1 answer
818 views

VHDL SLV dynamic width slice assignment

I have some code that takes in 2^X samples and outputs 2^Y samples, where X and Y are integers and Y is less than X. So for example X=6,Y=4, I ingest 64 samples and output 16 samples. As of right ...
0 votes
1 answer
179 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
0 votes
1 answer
2k views

How to save and reuse outputs of different steps of synthesis in Design Compiler?

Is it possible to save outputs of different steps of synthesis in Design Compiler and load them later? For example, is it possible to do analyze, save the output of ...
0 votes
1 answer
1k views

How many flip-flips would this code require?

H, I'm trying to understand the below code what how many FFs would be required when synthesis. TEST1. ...
6 votes
1 answer
903 views

Latches and Two Phase Clocking in modern ASICs

Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
0 votes
1 answer
93 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
0 votes
1 answer
299 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments? I ...
2 votes
3 answers
2k views

Xilinx XST won't infer block ram

I'm having trouble getting the design of my FPGA 80's computer to fit on a Papilio Duo board which is a Spartan 6 - xcs6slx9. The problem stems from RAM being inferred as distributed instead of block....
1 vote
1 answer
356 views

Expressions in Verilog module instantiations

If I have the following verilog module definition: module foo ( input a, output b ); assign b = !a; endmodule And then I instantiate it within another ...
0 votes
2 answers
399 views

question about Vivado synthesis and implementation

I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and ...
4 votes
1 answer
869 views

What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is ...
2 votes
3 answers
2k views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns (...
0 votes
2 answers
3k views

Xilinx ISE Synthesis taking too long

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly. Therefore, I tried to move to the ...
0 votes
2 answers
114 views

Analysis of Ringing Oscillator

I am looking at an analog synthesizer circuit the design of which incorporates several "ringing oscillators", which look like this: I understand that this is a resonant system that enters oscillation ...
0 votes
1 answer
89 views

How does synthesis tool handle the ports either driven by or to a module that is empty(Black Box)?

I have a design that instantiates a Memory and a Ring oscillator which I am excluding from synthesis by making them black boxes.(Not specifying explicitly, but instantiating an empty module with only ...
6 votes
3 answers
2k views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
3 votes
2 answers
1k views

Using Webpack from the command line, but without a project file?

I recently got Webpack to sorta work for me on my Linux system... but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's ...
0 votes
1 answer
71 views

Synthesizable averaging scheme

Looking for a clever solution (writing in Verilog) Let’s say I have two 8 bit values, and each value has an 8 bit score, for a total of four inputs, and I want to combine the two values into one 8 ...
2 votes
1 answer
535 views

Initialising FPGA internal RAM from file

I have a design that relies heavily on internal dual port RAM found in the FPGA and I want to take advantage of the fact that blockram can have power-on initial values to populate all this memory with ...
1 vote
0 answers
171 views

How to map a C/C++/Python code to an Intel FPGA?

I have a piece of code that mainly consists of matrix-matrix and matrix-vector multiplications, but has other operations too. I have written my code in both Python and C and would like to map it to an ...
2 votes
2 answers
3k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
0 votes
1 answer
195 views

efficiency and speed in image processing with FPGA

Hi I have been writing a code in VHDL for some image processing. However, due to some reasons I have not yet determined the sythesis does not stop. I suspect that efficiency of the code is not as much ...
3 votes
3 answers
2k views

How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?

From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
0 votes
1 answer
97 views

How to implement Quartus IP cores using ALMs?

This is a follow-up question on this, where I had asked about how one can implement multiplications without using any DSPs of the FPGA. Now, I would like to know whether one can implement Quartus IP ...
0 votes
2 answers
201 views

Design a circuit from logic gates, flip flops and/or multiplexers

I would like to create a simple circuit from logic gates, flip-flops (no RLC components) to do the following task: This circuit has 5 inputs (4 positive real-valued signals \$x_1, x_2, x_3, x_4\$ and ...
2 votes
1 answer
1k views

VHDL: Optmize signal comparisons for synthesis

As a preface, there are certain coding styles used in VHDL/Verilog which help the synthesis tools infer different hardware(some better in perfomance than the other). For example using an if-else-if ...
0 votes
1 answer
254 views

How to partition a combinational circuit into parts with equal delay?

I have a huge combinational circuit with a large delay. I like to partition this design (based on delay) into smaller parts and later, convert it to a sequential pipelined circuit. Are any of the ...
2 votes
1 answer
2k views

How to find power, delay, and area of a synthesized design using Design Compiler?

I have a huge design that is synthesized and mapped to 45nm Nangate library. Is it possible to read the mapped Verilog file in design compiler and find estimates of power, area, and delay without ...
2 votes
1 answer
1k views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...
0 votes
1 answer
3k views

Ungrouping synthesized modules in Synopsys Design Compiler for better synthesis results

I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A ...
4 votes
4 answers
19k views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...
3 votes
4 answers
2k views

Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something? this is the truth table ...
3 votes
1 answer
4k views

Partially associated formal cannot have actual OPEN in VHDL under Vivado

I'm getting the error "[Synth 8-2519] partially associated formal q8 cannot have actual OPEN" - this error is for the line Q8(0) => OPEN, and all similar OPEN ...
0 votes
1 answer
128 views

High Level Synthesis of a Microprocessor [closed]

I am working at an FGPA shop right now using Xilinx FPGAs. I do not have a ton of experience with designing logic, especially when it comes to microprocessors. One of the big movements my team is ...
2 votes
1 answer
4k views

While loop in VHDL

To check the synthesisability of while loop, I created one hypothetical vhdl code as follows. ...