Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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Is it a good practice to implement your own modules in SystemVerilog to estimate and assign delays? [closed]

I'm building a RISC-V CPU in Verilog. I have already some instructions implemented and, before continuing, I want to start adding delays to test the circuit better. My design uses several ...
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How to finish the forever statement on run_phase in UVM?

I'm trying to understand forever statement in raise_objection()/drop_objection(). I thought that the ...
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ModelSim cannot find SystemVerilog standard library file

I am trying to compile a very simple SystemVerilog module; however, I am getting the following error messages. ...
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What can procedural statements do that assignment statements cannot do in Verilog?

It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
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Auto Prediction Register model update Issue in RAL

I'm trying to understand the auto prediction concept in UVM RAL model, and I came across the Auto Prediction Register model update Issue in https://youtu.be/hrxhUE_RHyY?t=145. But, I didn't understand ...
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How to setup a Backdoor Access within UVM RAL model?

I'm trying to understand Backdoor Access within UVM RAL mode example https://www.edaplayground.com/x/jy3U . In uvm_guide, it wrote that if HDL paths are used, the root HDL paths must be specified in ...
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Verilog state machine, state does not change [closed]

Below is my code in which i want to shift the data serially out from the FPGA in state "transfer". However when I simulate it, the state does not update. It is stuck in "update state.&...
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Does the "input" keyword do anything in a SystemVerilog function declaration?

Is there a difference between these two SystemVerilog function declarations? Does the "input" keyword change any functionality? I've seen it both ways in examples. ...
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SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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Lattice Diamond - trying to pipeline but tool is fighting me

I am trying to pipeline a 1-bit signal that has to travel pretty far across the chip (an ECP5 FPGA). The software is Lattice Diamond. The Verilog looks like this: ...
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Verilog: Can I chain nonblocking assignments?

I'm trying to find the most human-readable way to pipeline some logic in system verilog. Most of my delays are routing delays. Is it valid to write something like this? ...
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SystemVerilog Assertions wizard

A few years ago, Axiom Design Automation (acquired by Mentor Graphics in 2013) had a tool called Assertion Studio. It was a high-quality wizard to create assertions (including SystemVerilog ones). Are ...
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SystemVerilog ring oscillator simulation with different delays

I am currently encountering issues with my ring oscillator simulation in SystemVerilog, which I cannot explain. Toolchain: ...
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Can someone explain how this code execution is happening?

module test; int j; initial begin for(j=0;j<3;j=j+1) fork $display("inside fork join",j); join_none $display(j); end endmodule I ...
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How to use case for continuous assignment?

I get a bunch of these errors on the following code: (VERI-1100) procedural assignment to a non-register 'nextstate' is not permitted The problem is mostly with the ...
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What is the new constructor's argument rule in UVM?

I'm wondering why some new constructor has been implemented with argument and some new constructor has been implemented with no ...
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What is exactly a transaction initiator and executor in UVM port and export?

Screenshot from this video. Whereas in UVM, sequencer has an import/export and driver has a port. Sequencer seems to be the transaction initiator and driver as the executor (as it is finally ...
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SystemVerilog - clk not toggling in verification

I'm testing an AES encryption machine that's written in Verilog. I know that the DUT is perfect because I created a Verilog testbench. When I simulate in VCS, the clk stays at 0 the whole time and the ...
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How to print a created handle information in UVM?

I create an object handle in UVM usually with new or create to allocate memory. Is there any possible way to print about ...
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Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...
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By design, why does SystemVerilog logic type has 4-states possible but VHDL std_logic type has 9-states possible?

The SystemVerilog logic type can take one of these possible values per bit: '0', '1', 'X' and 'Z'. The VHDL std_logic type can take one of these values per bit: '0', '1', 'X', 'Z', along with 'U', 'W',...
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Pitfall with mixing of blocking and non-blocking assignments for the same logic/reg in SystemVerilog

VHDL has a clear distinction between signals and variables. Variables are always updated as soon as we assign a value to them. However, a signal is only updated at the end of the process block. In ...
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Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
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Passing Unpacked Array of Packed Array as task arguments

task xyz(output op, output bit [width-1:0] write_data []); I have my task xyz definiton in an interface. I want to call this ...
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How to partial port connect by using interface bundle?

I'm trying to connect DUT's port list with interface by using bundling. The current problem is that the DUT was implemented with lots of ports. It's almost 1500 more. I want to connect a partial ...
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How to connect multiple interfaces within DUT in UVM?

I have two interfaces: virtual intf vif; virtual i2c_intf i2c_vif; I need to connect them at my top level. Currently, I am connecting it like below: ...
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What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a ...
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What is the SystemVerilog equivalent of the VHDL "library"?

I have been writing VHDL for a while. There, we have the concept of libraries, which comes in handy. I cannot find something of this nature in SystemVerilog. Is it true that SystemVerilog has no ...
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How to start task in virtual sequence from testcase?

I'd like to execute a virtual sequence's task as below: ...
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Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...
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Array of genvar in SystemVerilog

I'm trying to implement a Dadda tree multiplier in SystemVerilog using generate blocks. However, the algorithm I'm using to instantiate the logic requires arrays, ...
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Verilog file naming question

I just started to learn Verilog in college so please forgive me if this is an elementary question. I know there can be multiple modules in one .sv file. But in that case, what is the naming convention ...
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How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
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Synthesizing designs in yosys [closed]

If you have a sequential circuit in verilog or system verilog and want to synthesize it to specific gate types and flip-flops, how do you go about it. For example, may be synthesize the design to nor,...
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Access VHDL FSM state type in SystemVerilog testbench?

I have a VHDL block that implements a state machine, with states defined as a type and the current state as a signal of that ...
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2 votes
1 answer
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SystemVerilog vs VHDL - Is there a way in SV to do late definitions of array sizes?

In VHDL I can make my modules arbitrary. Bus sizes flow from higher levels. That way I don't need to edit all my code every time I reuse a module. Consider the following (incomplete) examples (This ...
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System Verilog Mux Implementation using tri-state buffers

I found a verilog implementation of a mux using tri-state buffers in the document UMD Lab Tutorial on Verilog (I'm not a student, graduated 2 years ago :)) ...
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SystemVerilog Mux design with "always_comb and tri state variables"

Here is my code for a mux inside an always_comb block. I'm designing a mux with combinatorial logic where I use the shortened ...
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-4 votes
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Verilog truth tables [closed]

I am starting in verilog, I am very confused with truth tables, how do I do it in verilog using "if-else", my instructor introduced us to the topic with the following example: after seeing ...
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How to rotate bits in Verilog

I am trying to create a way to rotate bits in Verilog according to a calculated register. Here is what I have tried: ...
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Addition of two hex numbers in Verilog gives wrong result

I am trying to add hexadecimal numbers in Verilog but I am getting the wrong outputs. Here are the numbers I am adding. Variables temp_1 and ...
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SystemVerilog Elevator FSM issues with conceptual design and translation to code

So I'm trying to create a FSM elevator system (single elevator 5 floors) in SystemVerilog and I'm having trouble mapping out how to write the code. In a traditional Moore or Mealy style FSM I can see ...
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Verilog for loop not iterating

The current for loop that I have coded below is getting stuck at its last iteration value. In other words, the value of i initially starts at 0 but once it reaches ...
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Defining a variable in bytes using Verilog

I am trying to implement a 16byte input (K) in Verilog which I have never done before. Also, I need to pull each byte from the index K using a for loop. In this case, b=16bytes, w=32bits, u=w/8. Here ...
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2 votes
2 answers
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What happens when the number of bits required to represent possible values in constraint (var inside {[x:y]};) exceed the rand variable width?

For the following class: ...
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How to Use Modular Arithmetic in Verilog

I am trying to code the RC6 (Rivest cipher 6) algorithm using Verilog. The algorithm requires addition, subtraction and multiplication in modulo 232. I've been told that I can use conventional +, -, * ...
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5 votes
1 answer
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Why don't I see the clocking block input skew in waveforms?

That's the code: ...
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SystemVerilog Synchronizing Processes with Events

Can anybody please explain why that's the order of the outputs for each case? 1. ...
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1 vote
3 answers
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Declaring Verilog parameters with division in Verilator produces width error

I am having trouble declaring Verilog parameters with division in Verilator tool. Here's the whole module: ...
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1 answer
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SystemVerilog Assertions

For the following property assertion: property COMPLEX_SEQ; @(negedge CLK) disable iff (X) (C ##1 B[*1:3] ##1 A) |=> (J[*4] ##1 K); endproperty And ...
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