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Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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SystemVerilog: VCS detect combinational loop

first of all I'm still learning English so thanks for your patience I'm debugging a large code, I did a testbench for every module and I think they work as intended but when I connect them together ...
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1answer
31 views

How to assert multiple concurrent assertions in system verilog?

I want to do something like this using concurrent assertions (I want to check that when from_clk changes to_clk must change and when to_clk changes from_clk must change): ...
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2answers
91 views

SystemVerilog: Race condition in memory

Hello I'll be brief because my English isn't good thank you for your patience I'm working on a system that drives this memory: ...
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0answers
42 views

Logic synthesis tool

I'm looking for a SW that can do logic synthesis of HDL code (System Verilog) and can show critical path length. I know there's Synplify, but it's paid (From what I've read it costs a lot) and the ...
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4answers
81 views

Toggle output using Verilog

Can anybody explain this code to me? ...
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19 views

SDF back annotation in systemVerilog design using interfaces

I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the ...
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1answer
38 views

always_ff is always executed earlier than always_comb in ModelSim

I have an exercise that separating comb logic from sequential logic in always_ff block. However, I found that the ordering of always_comb and always_ff executions is different between different ...
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1answer
50 views

verilog code for bitlength operation

What is the Verilog code for bitlength operation. Example: If Y=45897, I need BitLength(Y)=16. verilog code for BitLength(Y) is ? Please help me to write this.
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1answer
88 views

Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
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1answer
30 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
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1answer
28 views

Will temp variable in always_comb create latch

I have following code snippet where a temp variable is used to count number of 1s in an array: ...
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2answers
113 views

Bidirectional assignment in Systemverilog

I need to create mux block that works with inout pins. My module has n inputs and n outputs, I want to be able to switch between different outputs. The problem that I am currently having is that I ...
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1answer
147 views

System verilog instantiation of parameterized module

If I have a mymodule that has parameters and I am instantiating this mymodule inside a top level block which has a few sub module and mymodule is also a submoulde then when instantiating mymodule ...
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24 views

IVerilog in CMD: `include statement not working

I've written the code for every component in a simplyfied PIC Microcontroller in different .v files. To instantiate a module present in a file different to the testbench, I wrote the following line of ...
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2answers
233 views

Opening and reading pixel values from bitmap images in Modelsim

How do I open a bitmap image, read the pixel data (24 bits) and store it in a memory that I created in a Verilog module in ModelSim? How do I open the below image in Modelsim? Is it possible in the ...
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2answers
99 views

Design a circuit from logic gates, flip flops and/or multiplexers

I would like to create a simple circuit from logic gates, flip-flops (no RLC components) to do the following task: This circuit has 5 inputs (4 positive real-valued signals \$x_1, x_2, x_3, x_4\$ and ...
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1answer
49 views

SystemVerilog Assertion consecutive repetition for overlapping sequences

I have a specification as follows : "Check that 'valido' is not asserted when 'validi=1' for only two, one or zero consecutive clk cycles." the following assertion FAILS (n-3 times) on a sequence of ...
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0answers
58 views

Variable clock counts in System Verilog assertion property

Is there a way to introduce variable clock counts in assertion properties as shown in the example below ? ...
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0answers
84 views

System verilog - streaming operator multidimensional array to stream of bits

I cant figure out how to take multidimensional array such as: bit unsigned [10:0] img [3:0][3:0]; Think of it as an 4X4 image that each pixel is 11 bits in my ...
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260 views

How to use struct in an interface?

Since it's not possible to have an interface in a package, what is the best practice to manage interface containing struct of a package ? ...
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1answer
71 views

Is it possible to use `.*` in SystemVerilog to register interfaces' elements?

Let's say I have one interface, I'd like to ...
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1answer
134 views

How to assert multiple properties in System Verilog

What is the most efficient way to assert multiple properties in SV ? Example: ...
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0answers
122 views

“range must be the final index in the indexed name”, system verilog slice array and send to module

I have an 2d array (and 1 more dimension of 11 bits),and I dont want to send to module "cb" the entire 2d array, but only part of him, and I understood that if I want to slice an array I cant use not ...
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1answer
59 views

Read and write simultaneously from different indices of an associative array in system verilog

Is it possible to read and write simultaneously (In parallel) from different indices of an associative array in System Verilog ?
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1answer
25 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1answer
39 views

Implementing a Mealy Machine in Verilog

I have a piece of code that I don't understand: always_ff @(posedge CLK) state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate; ...
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1answer
37 views

SystemVerilog: selecting bits without storing calculation in variable

Is there really no way to select bits straight from a calculation without giving them a name and then selecting the bits from the name in SystemVerilog? ...
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1answer
254 views

SystemVerilog Enumerated Multi-Domain Array -> how to declare/define?

Here is an example how to define the 2*N array of enum types of {S0,S1,S2,S3}: typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} state_t; (*) So, each element of the above 2*N array could be either S0 ...
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1answer
367 views

Testbench for simple register file

I want to test my register file before connecting it to ALU. So I wrote a testbench for my register file. ...
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1answer
171 views

System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations

Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
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3answers
2k views

Using $floor in Verilog

Verilog has a bunch of math system functions. I'm trying to use $floor in my Verilog code but I'm getting this message: System function call floor is not allowed here Does anyone know why I'm ...
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1answer
457 views

SystemVerilog: Sensitivity list of always_comb

It seems to me that always_comb is not sensitive to variables assigned in the block itself. For example, the following block: ...
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1answer
575 views

SystemVerilog: How to give different parameters to modules in the same array?

In my design, I wanted to use a number of counters with different initial values on reset. Therefore I defined the counter module as follows: ...
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1answer
240 views

Verilog modulus operator for wrapping around a range

My background is in software and I'm new to (System)Verilog so when tasked with implementing a caesar shifter (shift each letter in a string by N letters, wrapping around if necessary e.g. ABCXYZ ...
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0answers
72 views

Load instruction fetching wrong value

I have written some code for mips but in my program the LW insturction didnot fetch the correct answer. For example: ...
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1answer
251 views

(System)Verilog: signal is x or 1 depending on placement of concurrent blocks in the code?

I'm basically aware that the Verilog scheduler is inherently indeterminate, but I really don't understand why that's the case with the following code (I've simulated both cases with Icarus and ...
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1answer
276 views

SystemVerilog import statement outside module definition

What does an import statement outside of a module (|class|package) definition mean? Does it apply to entire file? Is it even legal? I don't see it in IEEE Std 1800™-2012. It seems to be ...
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1answer
2k views

what is the difference between logic,reg and wire in system verilog?? explaination with an example would be helpful

explanation with an example would be helpful.i tried:- input logic [9:0] data1 as the input of the counter and loaded this value into the count1 (logic [9:0] count;) and then assigned count1<=data1;...
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1answer
352 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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1answer
97 views

ASIC verification of a multiport switch

simulate this circuit – Schematic created using CircuitLab I have a DUT that can take packets from all 4 identical interfaces (A, B, C, D) Packets from one port can go to either one of the ...
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1answer
3k views

What is the use of 'import' in SystemVerilog?

Once a package is included the file is compiled. Then why it is required to import same package ?
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1answer
580 views

SystemVerilog module instantiation with non-existent parameter

I am instantiating a module in SystemVerilog that has a lot of parameters. One of them (this is actually someone else's code) does not exist in the module definition. What will the compiler do in ...
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367 views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this ...
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1answer
164 views

Redefining a parameter in verilog

I'm new to verilog and I got a question. Can I initializing a parameter in global scope and reinitializing it module scope. ...
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2answers
102 views

SystemVerilog: S-R Latch doesn't work correctly

Here is my gate level description of an S-R latch: ...
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0answers
45 views

Directing synthesis tool to use same hardware for MAX and Comparator circuits

I want to create a circuit with always statement in Verilog which has comparator and max functions. I want to describe them in a way that synthesis tool generates same hardware for greater output of ...
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0answers
32 views

Multidimentional Variable Range Array in Systemverylog [duplicate]

Please anyone tell me how to declare multidimentional variable range array in systemverylog. i.e I need to declare 2D array of size 'm' rows and 'n' columns. logic v[m-1:0][n-1:0]; giving me an error ...
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1answer
78 views

SystemVerilog in ModelSim ignores negedge/posedge when monitoring

Using SystemVerilog and ModelSim, I want to monitor the values of some signals in my design when the clock is on its negative edge. Strangely, the code responses on both edges (positive and negative). ...
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1answer
649 views

Reading data from register file in system verilog

I'm creating a simple register file in system verilog, with a total of 6 registers that can be written to/read from. When I run a simulation in ModelSim, the output never shows the correct data - it ...
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1answer
823 views

How to measure time difference between 2 signal changes in verilog?

There are two signals sig, enable - and I wanted to find the time difference after which enable toggles after sig falls. ( >Sig Low to Enable toggle< time) I understand that always@() block can't ...