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Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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Can generated events get placed before events already in the event queue in SystemVerilog?

I tried to consult the Verilog LRM but wasn't successful; some of the reason is because I don't really know the correct terminology. This question is related to this one here, but I never got an ...
EE18's user avatar
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Synthesizable system verilog code to find least number in an array

I have tried a few ways using for loops to find the least number in array, but having a hard time in updating the pointer whenever a new least value is encountered. I am following the below textbook ...
Saransh Choudhary's user avatar
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How can I reduce the amount of resources I'm using in this system verilog design

I want to implement a design that follow a paper written by a researcher the part, this lead us to this picture that resume what the code I have so far is supposed to do: As you can se the goal is to ...
fabrice's user avatar
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Creating entity/module containing IP from different vendors

In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
quantum231's user avatar
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Using a parameter as a macro in system verilog code

Assume that I have below module definition with a parameter N: ...
Saransh Choudhary's user avatar
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Increase operation width during the operation without extra registers in Verilog

I have two signals of type "reg" with different bit lengths: reg [15:0] A; reg [11:0] B; I want to display the value of ...
Saeed Jazaeri's user avatar
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2 answers
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The quality of testbenches with UVM testing

This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied. So I come from a hardware engineering background, as I was discussing how ...
Lannan Jiang's user avatar
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Verilog-A compiler directive inside an analog block - legal or not?

In Verilog-A, we desire to insert an `include directive inside a module and specifically inside an analog process block. Is this legal or not? I can not find any ...
TomH's user avatar
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Passing Matrices (larger arrays) between modules

I'm trying to have my design be more compartmentalized and separate each task into different modules/source files. I basically want to pass a matrix and a vector into a module I created where I'll do ...
Samuel's user avatar
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What is SystemVerilog way of writing the VHDL 'range attribute?

In VHDL I can write this: slv_1(slv_2'range) so that I select slice of slv_1 that has same range as ...
quantum231's user avatar
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doubt regarding class handle in system verilog

I am unable to understand what actually the assignment smpl=e_smpl; does. I thought that by doing so sample class handle will also point to the ext_sample but it is ...
Kartikey's user avatar
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AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton

I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum. While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
My Name's user avatar
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Single-Digit BCD Adder

I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
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QuestaSim shows internal signals of VHDL module but not SystemVerilog module

So for the first time, I created a SystemVerilog module and testbench in QuestaSim today. I created a project inside QuestaSim and then created a counter and a testbench for the counter. When I ...
quantum231's user avatar
1 vote
1 answer
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SystemVerilog help, I'm stuck

Please help with this SystemVerilog code. The intended behavior is that the seven-segment displays 7 and 5 will show the current inputs, and the segment displays 0 and 1 will be the two-digit result ...
David's user avatar
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Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
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1 answer
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Dissect code related to "Convergent rounding: Round half to even" written in SystemVerilog

This question is related to article on rounding found here. The "Convergent rounding: Round half to even" code is written as follows: ...
quantum231's user avatar
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Null pointer access error in SystemVerilog

I am practising the SystemVerilog class concepts. I got an error while running the code: Fatal Error: RUNTIME_0029 code.sv (67): Null pointer access. Here is ...
Kartikey's user avatar
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How are event-controlled events scheduled in Verilog?

Consider the following snippet (please let me know if you need me to include more): ...
EE18's user avatar
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How does Verilog deal with this snippet (procedural block order dependence)?

At the outset, I would like to say that I am not able to run this snippet at the moment but, even if I were, I hope this question would still stand as I'd like to understand why the Verilog standard ...
EE18's user avatar
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Can an event name be manipulated in Verilog/SystemVerilog?

In a Verilog testbench.v, there are commands that are used in a task. ...
Carter's user avatar
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How to indicate a constant to a surrounding module

I have a SystemVerilog module that calculates a constant. How can I make this constant available to an enclosing module? Parameters are good for passing constants into a submodule, but they don't seem ...
Spices's user avatar
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Is there any restriction on the maximum size of a SystemVerilog packed array?

Suppose I make a packed array as: logic [x:0] packed; As packed arrays guarantee continuous memory allocation, is there any restriction on the maximum value ...
Kartikey's user avatar
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1 answer
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How to connect multiple TLM ports to UVM Sequencer?

There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
TSyi's user avatar
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Functions in Verilog for combinational logic

I encountered something weird in a Verilog code, and I have doubts about it. Someone used a function in Verilog in the following way: ...
Michael Rahav's user avatar
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1 answer
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Interface definition in package in SystemVerilog

I have a very simple interface definition in a package in SystemVerilog: ...
fiedel's user avatar
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Fixed point multiplication circuit in HDL doesn't work as expected

I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
Becker's user avatar
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1 answer
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Error 10170 in SystemVerilog for adder

I'm trying to build an n_bit adder, but the Quartus gives me this error: Error (10170): Verilog HDL syntax error at n_bit_adder.sv(12) near text: "for"; expecting "endmodule". ...
Abner Arroyo's user avatar
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Generate random numbers in a range with some others excluded

I need to generate random number between 0 and 191. This will fit in 8 bits. Then depending on certain constants being defined or not, certain slices of this range shall be included or excluded. e.g ...
quantum231's user avatar
4 votes
2 answers
367 views

SystemVerilog array initialization

I want to know what is the use of default initialization in SystemVerilog. How are int a[3] = '{3{2}}; and ...
Kartikey's user avatar
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1 answer
518 views

Bit order when assigning SystemVerilog struct directly to a logic type

SystemVerilog has packed struct where VHDL has record. Unlike VHDL that requires an explicit conversion between a record and std_logic_vector, SystemVerilog is able to make an implicit conversion. I ...
gyuunyuu's user avatar
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2 votes
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How to find syntax error in RTL file quickly?

My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit ...
quantum231's user avatar
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Does SystemVerilog permit using slice of output port during portmap similar to VHDL?

In VHDL, one can do this: ...
quantum231's user avatar
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What is the technical reason an array of interfaces can't be indexed into unless the index is constant?

I'm curious as to why an array of interfaces can't be indexed into unless the index is constant. Specifically I'm curious as to the case where a for loop is used, because a for loop elaborates into an ...
avor's user avatar
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Why the prohibition against blocking statements in FF synthesis?

In most intros to Verilog, it's basically stated as a law that "blocking is for combinational and nonblocking is for sequential". That turns out to be a good rule of thumb because of how ...
EE18's user avatar
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4 votes
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Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

In a number of sources I've come across, it's mentioned that for sensitivity lists which include an "edge", you cannot include other signals in the sensitivity list if you want synthesis to ...
EE18's user avatar
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In SystemVerilog, is the set of operators usable in a continuous assignment smaller than that usable in an always statement?

My question is, essentially, as stated in the title. For what it's worth, it's prompted by a comment made by Stuart Sutherland on page 256 of his RTL Modelling with SystemVerilog: The primary RTL ...
EE18's user avatar
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3 votes
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How do void functions get their results "out" in and more on functions and tasks?

I am reading Stuart Sutherland's RTL Modelling with System Verilog and up to this point have had no trouble understanding. However, unless I missed it, it seems he has gone way too quickly over ...
EE18's user avatar
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-2 votes
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How can I run Verilog code with data at a specific time in the past?

My simulation takes hours until it's stopped from my SystemVerilog code using $stop;. When it stops, to have proper information, I need to run a Verilog task/...
None's user avatar
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1 answer
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How to stop ModelSim at a condition based on signals?

From the window, I'd like to give a condition in the console when to stop the simulation. I've tried: when {/tb/DUT/sequence==256806} {stop} run -all but it doesn'...
None's user avatar
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1 vote
1 answer
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How to bind a module in system verilog, with parameters not from the target location

I would like to bind a module, and pass a parameter from the module I declared the bind in, rather than them all coming from the module I am binding to. ...
ET_FPGA's user avatar
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-1 votes
1 answer
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Program block avoiding race condition

I have a small design that assigns a value to a variable "addr" using initial block. ...
totochan1965's user avatar
1 vote
2 answers
346 views

How does this SystemVerilog compiler directive work?

The text I am reading (Stuart Sutherland's text on SystemVerilog for Simulation and Synthesis) gives the following snippet which apparently should be used in order to avoid including the same package ...
EE18's user avatar
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1 vote
1 answer
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Assign statement in testbench doesn't seem to work as it should

I have a small Verilog code example asked as an interview question. I am not sure why it prints "p=01" but not "00" since assign should update <...
totochan1965's user avatar
1 vote
2 answers
107 views

Connecting cross referenced nets to inout ports in verilog

I am prototyping an ASIC on Xilinx FPGA, which has a third party DDR interface. In order to implement the design, the ASIC DDR controller is replaced with a Xilinx DDR4 controller. This controller ...
matryx's user avatar
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Do HDL synthesizers "optimize code", more or less as compilers do?

I'm implementing a pipelined CPU in SystemVerilog. I need to propagate datapath signals from one pipeline stage to the next but, of course, not all stages produce the same number of signals. To keep ...
Dan's user avatar
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1 answer
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Using a function to parameterize the length of port in SystemVerilog module

In SystemVerilog and in VHDL as well, we can parameterize the length of ports on modules/entities. This means that the bit length of a port can be changed by using a parameter/generic. The required ...
quantum231's user avatar
3 votes
2 answers
610 views

Does SystemVerilog have (others=>'0') expression like VHDL?

In VHDL, we can set all bits of something a value by using (others=>'0'). It is also possible to use slice index e.g., ...
quantum231's user avatar
1 vote
1 answer
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Verilog counter delay in task not working

I'm trying to generate different delays in multiple places using task WAIT in a synthesizable module, and the code is as follows:...
Shakil's user avatar
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How to truncate an expression bit width in Verilog in 2023?

I have the same question as here: How to truncate an expression bit width in Verilog? But I was hoping that in 2023, there would be more interesting answers that in 2013! My specific use-case: ...
Bamban's user avatar
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