Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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Library creation RTL

I am expected to create a Library for a certain function that needs to be used reputedly. This needs to be done in RTL. I am not very sure what this means because until now I have only directly ...
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59 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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46 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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34 views

SystemVerilog: delay in next_state

for some reason there is a delay in when the next_state is evaluated. To my understanding it should be updated on the same rising clock as when state is updated. Could someone please help me explain ...
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1answer
58 views

Quartus 10166 error: “Always_comb construct does not infer purely combinational logic”

The error is coming from the second always construct. I have no idea how a latch is inferred since I've specified the output for every possible input state. Any ideas? ...
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SystemVerilog Finite State Machine debugging

I am trying to debug my finite state machine in modelsim and I have no idea what's wrong with the code. It would be helpful to see the state/next_state internal signals in the waveform viewer. Is this ...
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1answer
47 views

“Dynamic” shifter in priority queue implemented on FPGA (SystemVerilog)

I'm implementing a priority queue on FPGA such that if some external signal is up (\$w_r\$) the priorities are evaluated and the priority queue us updated accordingly. The schematic is the following: ...
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3answers
94 views

XOR all signals of a vector of two dimensions together

I have a vector that contains 15 elements of 8 bits each. I want to XOR each element: $$ out = f_0 \oplus f_1 \oplus \dots \oplus f_{15} $$ where each \$f_i\$ has 8 bits (it's declared as logic [7:0] ...
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52 views

How can one test that a signal is High-Z when simulating with Verilator?

Say I have this module: module Test( input logic a, output logic b ); assign output = a ? 1'bZ : 1'b1; endmodule; Currently, when testing the ...
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Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: ...
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3answers
94 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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58 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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105 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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54 views

Difference between wire and logic for this particular problem

I've worked this problem before in Verilog and no problem at all. Tried the same problem with SV and the problems started. The idea is to just show numbers on the first 3 7-segments based on switches. ...
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In SystemVerilog, must nets be declared with the **logic** data type?

I'm reading Sutherland's "RTL Modeling with SystemVerilog ..." book. On pages 77 and 79 he makes the following claims respectively: The data type must be the keyword logic, which can be specified ...
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1answer
27 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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3answers
157 views

Calculating rolling sum of array

I am trying to implement a rolling average of an array of 12 bit samples in SystemVerilog. New samples are generated and shift into an array via a clocked flip flop. The goal is to have a register ...
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1answer
788 views

What is the difference Verilog race condition, X's propagation and Metastability?

I'm trying to understand Verilog Race Condition X's propagation and Metastability with http:/...
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2answers
38 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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HDL implementation of Numerical Analysis Techniques

I am looking for open-source implementations of Numerical analysis techniques (specifically root-finding techniques like the secant method) on FPGA using any HDL. Would also appreciate if anyone could ...
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1answer
108 views

Verilog style: one large always block vs multiple small always blocks?

Say I have multiple registers set up to update on the same clock, based on different conditions. I could set this up as a series of multiple always blocks: ...
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1answer
68 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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2answers
231 views

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

This question explains how to use Verilog parameters to combine constants from different modules at compile time. I am wondering if it is also possible to use conditional statements to modify ...
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2answers
62 views

Is it possible to make hierarchy of constants in System Verilog?

Is it possible to make a synthesizable hierarchy of constants in System Verilog? For example: There is a board with FPGA and several peripheral ICs. Each IC have some setting registers. Each ...
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1answer
93 views

How do I calculate constant values across several modules at compile time in Verilog?

I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
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212 views

'11' sequence detector systemverilog

I wrote a program for a '11' sequence detector to be implemented by both Moore and Mealy machine. The problem statement is for z to be asserted high after x has been high for 2 cycles. I've attached ...
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73 views

Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
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134 views

Connecting the following structure of multipliers and adders in an elegant way in verilog

I am attempting to write a synthesizable verilog (or Systemverilog) module. I also want to make the modul parameterizable, which has presented a problem when trying to connect the following structure ...
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What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
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199 views

A question about instantiating a module with a parameter in systemverilog

I'm now writing a testbench. In my testbench, I want to read the length of a text file and pass it to another module while instantiating. The idea is like this: ...
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2answers
130 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
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1answer
39 views

ModelSIM not generating outputs for any variables

I have been working on this issue for days and have not been able to figure it out. I was hoping one of you could help me solve this issue. So, when I run my SV code in Quartus and compile it, I don'...
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Unexpected behaviour of implication operator in SVA

There is an issue I face while using an implication operator in one of my code examples. This code can be found at https://www.edaplayground.com/x/4fVz Code Summary In my code, I have defined ...
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1answer
263 views

Undefined signal in simulation

I am trying to verify a design written in VHDL using SystemVerilog's assertions. however I got a problem when I have a non defined signal'X' Just for example here is a code of a Comparator: ...
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3answers
182 views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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238 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
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1answer
228 views

How to write constraint file for the divided clock in Verilog?

I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
75 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
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1answer
163 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
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69 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
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77 views

Using two different clocks in my assertion

I am using SystemVerilog to write assertions in order to test the behavior of my design. In my design I have two clock : the usual CLK_int and another clock called ...
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How to assert multiple concurrent assertions in system verilog?

I want to do something like this using concurrent assertions (I want to check that when from_clk changes to_clk must change and when to_clk changes from_clk must change): ...
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2answers
214 views

SystemVerilog: Race condition in memory

Hello I'll be brief because my English isn't good thank you for your patience I'm working on a system that drives this memory: ...
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4answers
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Toggle output using Verilog

Can anybody explain this code to me? ...
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SDF back annotation in systemVerilog design using interfaces

I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the ...
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181 views

always_ff is always executed earlier than always_comb in ModelSim

I have an exercise that separating comb logic from sequential logic in always_ff block. However, I found that the ordering of always_comb and always_ff executions is different between different ...
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1answer
60 views

verilog code for bitlength operation

What is the Verilog code for bitlength operation. Example: If Y=45897, I need BitLength(Y)=16. verilog code for BitLength(Y) is ? Please help me to write this.
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264 views

Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
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48 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...