Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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Assigning a value to a tri data type variable in Verilog

Suppose there is a 'tri' data type variable A declared in a module m in verilog. A is connected to the output of another module n which is instantiated twice inside m, in both the instances. In one ...
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23 views

Declaring Pins in Top Module gives unspecified I/O default error, declaring it gives me the design is empty error

I have two modules top (input a, input b, output c) second(input a, input b, output c) I instantiate second in ...
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89 views

How to get signal dependencies from RTL verilog?

How can I find out if a signal B has any combinational dependency on a signal A without manually examining the verilog source code? (Question edited to try and make the reason/background more clear) ...
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81 views

Verilog finite state machine won't reset (asynchronous) current state to initial state (shows xx)

I have mostly worked on VHDL and I have recently started learning Verilog. I wrote a Moore Finite State Machine (FSM). The FSM is not resetting properly as current state upon reset doesn't go into ...
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46 views

Net has multiple drivers (Verilog)

I've looked at some other forums and know that this type of error occurs when multiple outputs drive the same input however I am struggling to see how to fix this error and what specifically is ...
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Verilog: Conditionally setting single bits to high-Z in vector

I have written a single-pin GPIO module for my project, and it is working fine. A simplified version looks like this: ...
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2answers
45 views

Override Top Level Parameters

I have the following top level module: ...
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1answer
39 views

Accessing same variables in Verilog on different clocks

I have a 50Mhz master clock clk and from that I have a derived baudClock clock which runs at 9600bps. I have a transmitter module that I want to follow a state machine flow every baudClock. The ...
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87 views

How to extend a pulse in system verilog

I am trying to make a very simple module in System Verilog that receives a short pulse as an input, and returns as an output a pulse which is twice wider. For example, if the input is a 1ns pulse, ...
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80 views

System verilog: check if logic signal changes at posedge

I'm relatively new to SV. I'm building a testbench in which I want to monitor a signal and take some action if it value changes @ clock posedge. I’m looking for a compact way to this (I.e. not using a ...
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52 views

Median Filter FSM Modelling

I'm trying to build a median filter in Verilog using a comparator to sort out the highest pixel value and erase it, then sort out the next highest etc. until I have only 5 pixels left (I'm treating ...
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2answers
89 views

Combinational loop in Verilog/System verilog

What's the difference between a += 1 and a = a+1 in SV/V? always_comb begin a = '0; a += 1; end always_comb begin a= '0; a = a+1; end Is 2nd case combinational loop?
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Vivado Simulator copy multiple values

I'm simulating a SystemVerilog based core on Vivado 2019.1. I can copy the value of any signal simply by select+right click+Copy Value, but when I select multiple signals (for my case I need to select ...
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45 views

FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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122 views

Understanding the Verilog Stratified Event Queue

I'm trying to understand how the Verilog scheduling algorithm works. The below example outputs 0, xxxx and not 1010. I'm not ...
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2answers
76 views

Data type of Clock signals

I've read a standard that says: "Logic type signals add a tick delay". What does the above statement mean? And why is the logic type signal adding a tick delay?
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Is it better to combine logic for two flip flops in a single always block?

I have always used separate always block for infering different flip flops when they dont have much in common. ...
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173 views

Are there any free simulators for SystemVerilog?

Are there any free simulators available for a hardware design coded in SystemVerilog? In particular, I need SystemVerilog's dynamic arrays.
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How to write the negation of 'a until b' property without using until (in SystemVerilog)?

I would like to write the negation of the property a until b (a and b being different ...
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2answers
50 views

How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format. signal a should never be 2 until it attains the value 1 How can we do that?
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106 views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
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1answer
147 views

Vivado:Error-Ambiguous clk in event control

Ambiguous clk in event control error and is pointed to always block. ...
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1answer
39 views

Generating unique values for multiple cyclic random variables

In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possibles values (due to a constraint). So, I expect to ...
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2answers
74 views

Verilog Generic Multiplexer - synthesis warning and simulation compile error using Xilinx ISE 14.7 “Port must not be declared to be an array”

I am pretty new to Verilog. I wrote a description for a generic multiplexer in Verilog as follows: ...
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50 views

Error with Assert statement in Verilog

I have the following assert statement in a for loop, which is within a generate block: ...
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1answer
84 views

How to use QSUB to submit jobs in parallel?

I would like to run thousands of simulations using qsub command, but I am not sure how to use it adding variables. Right now I have made this bash script to run my simulations, but it is too slow, ...
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43 views

Forcing verilator to take loop label given in RTL

I want to force the hierarchy of signal to take the loop names given in RTL written in System Verilog. Example: for (genvar i=0; i<4; i++) begin: GenLabel ...
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42 views

How Dump automatic variable in VCD

The automatic variable written inside module in systemverilog donot dumping in VCD.How dump automatic variable in VCD? ...
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32 views

Inconsistent behaviour in setting block name for genvar in Verilator

in systemverilog I am using block_name to set a unique name to genvar blocks as for (genvar i=0; i<5; i++) begin : block_name ---- --- end : block_name I am ...
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53 views

Transaction randomization succeeds, yet values do not meet constraints

In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value, please note that ...
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1answer
65 views

Failed to randomize dynamic array using foreach in constraint

In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction: ...
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1answer
147 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
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1answer
149 views

Dumping values of multi-dimensional arrays into gtkwave for verilator

I am able to do a VCD dump of multidimensional arrays using $dumpfile(),$dumpvars() commands in iverilog simulator but the same commands is not working for verilator. Kindly do let me know if there is ...
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1answer
123 views

How to automate Instantiation of modules in Verilog? (permutation)

Consider this file tb_sr_latch.v: ...
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82 views

Using arithmetic operations in systemverilog

I was trying to create a module for using the sensors that I recently bought. My module works well in simulation , synthesis and implementation. but when I used my module inside the top leveled module,...
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33 views

SystemVerilog FSM not working correctly

So, I was trying to create an FSM for my module which supposed to control five sensors. I thought I did it, but when I synthesized it, I saw that the code is synthesized as bunch of buffers and ...
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29 views

Finding all state sequential state elements in SystemVerilog code

I wanted to count all sequential state elements in SystemVerilog code. This was easy in verilog: grep reg *.v (multiply with bus width for busses) How do I do ...
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120 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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66 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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45 views

SystemVerilog: delay in next_state

for some reason there is a delay in when the next_state is evaluated. To my understanding it should be updated on the same rising clock as when state is updated. Could someone please help me explain ...
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1answer
372 views

Quartus 10166 error: “Always_comb construct does not infer purely combinational logic”

The error is coming from the second always construct. I have no idea how a latch is inferred since I've specified the output for every possible input state. Any ideas? ...
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100 views

SystemVerilog Finite State Machine debugging

I am trying to debug my finite state machine in modelsim and I have no idea what's wrong with the code. It would be helpful to see the state/next_state internal signals in the waveform viewer. Is this ...
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1answer
68 views

“Dynamic” shifter in priority queue implemented on FPGA (SystemVerilog)

I'm implementing a priority queue on FPGA such that if some external signal is up (\$w_r\$) the priorities are evaluated and the priority queue us updated accordingly. The schematic is the following: ...
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495 views

XOR all signals of a vector of two dimensions together

I have a vector that contains 15 elements of 8 bits each. I want to XOR each element: $$ out = f_0 \oplus f_1 \oplus \dots \oplus f_{15} $$ where each \$f_i\$ has 8 bits (it's declared as logic [7:0] ...
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127 views

How can one test that a signal is High-Z when simulating with Verilator?

Say I have this module: module Test( input logic a, output logic b ); assign output = a ? 1'bZ : 1'b1; endmodule; Currently, when testing the ...
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54 views

Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: ...
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3answers
179 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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62 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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266 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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62 views

Difference between wire and logic for this particular problem

I've worked this problem before in Verilog and no problem at all. Tried the same problem with SV and the problems started. The idea is to just show numbers on the first 3 7-segments based on switches. ...

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