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Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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Data type of Clock signals

I've read a standard that says: "Logic type signals add a tick delay". What does the above statement mean? And why is the logic type signal adding a tick delay?
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Is it better to combine logic for two flip flops in a single always block?

I have always used separate always block for infering different flip flops when they dont have much in common. ...
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63 views

Are there any free simulators for SystemVerilog?

Are there any free simulators available for a hardware design coded in SystemVerilog? In particular, I need SystemVerilog's dynamic arrays.
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How to write the negation of 'a until b' property without using until (in SystemVerilog)?

I would like to write the negation of the property a until b (a and b being different ...
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47 views

How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format. signal a should never be 2 until it attains the value 1 How can we do that?
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How can I tell the size of an array in Verilog?

If I declare an array in Java with "someType[] abc;" and use the "new" operator to give it a meaningful value, I can take a look at the value in "abc.length" to see how long array "abc" is. Is there a ...
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Need to concatenate 1 bit of a 2nd data with every new 1st data

I have two different datas. 1st data keeps coming in chunks every cycle (fixed width; new data comes in every cycle) 2nd data is fixed and needs to be appended 1 bit every cycle (fixed width and fixed ...
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1answer
38 views

Diamond: Warning: logical net has no load

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows: ...
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1answer
46 views

Vivado:Error-Ambiguous clk in event control

Ambiguous clk in event control error and is pointed to always block. ...
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1answer
38 views

Generating unique values for multiple cyclic random variables

In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possibles values (due to a constraint). So, I expect to ...
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2answers
37 views

Verilog Generic Multiplexer - synthesis warning and simulation compile error using Xilinx ISE 14.7 “Port must not be declared to be an array”

I am pretty new to Verilog. I wrote a description for a generic multiplexer in Verilog as follows: ...
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1answer
37 views

Error with Assert statement in Verilog

I have the following assert statement in a for loop, which is within a generate block: ...
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1answer
44 views

How to use QSUB to submit jobs in parallel?

I would like to run thousands of simulations using qsub command, but I am not sure how to use it adding variables. Right now I have made this bash script to run my simulations, but it is too slow, ...
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35 views

Forcing verilator to take loop label given in RTL

I want to force the hierarchy of signal to take the loop names given in RTL written in System Verilog. Example: for (genvar i=0; i<4; i++) begin: GenLabel ...
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How Dump automatic variable in VCD

The automatic variable written inside module in systemverilog donot dumping in VCD.How dump automatic variable in VCD? ...
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29 views

Inconsistent behaviour in setting block name for genvar in Verilator

in systemverilog I am using block_name to set a unique name to genvar blocks as for (genvar i=0; i<5; i++) begin : block_name ---- --- end : block_name I am ...
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1answer
49 views

Transaction randomization succeeds, yet values do not meet constraints

In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value, please note that ...
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1answer
49 views

Failed to randomize dynamic array using foreach in constraint

In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction: ...
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1answer
84 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
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1answer
67 views

Dumping values of multi-dimensional arrays into gtkwave for verilator

I am able to do a VCD dump of multidimensional arrays using $dumpfile(),$dumpvars() commands in iverilog simulator but the same commands is not working for verilator. Kindly do let me know if there is ...
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Using arithmetic operations in systemverilog

I was trying to create a module for using the sensors that I recently bought. My module works well in simulation , synthesis and implementation. but when I used my module inside the top leveled module,...
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30 views

SystemVerilog FSM not working correctly

So, I was trying to create an FSM for my module which supposed to control five sensors. I thought I did it, but when I synthesized it, I saw that the code is synthesized as bunch of buffers and ...
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Finding all state sequential state elements in SystemVerilog code

I wanted to count all sequential state elements in SystemVerilog code. This was easy in verilog: grep reg *.v (multiply with bus width for busses) How do I do ...
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1answer
68 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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36 views

SystemVerilog: delay in next_state

for some reason there is a delay in when the next_state is evaluated. To my understanding it should be updated on the same rising clock as when state is updated. Could someone please help me explain ...
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1answer
146 views

Quartus 10166 error: “Always_comb construct does not infer purely combinational logic”

The error is coming from the second always construct. I have no idea how a latch is inferred since I've specified the output for every possible input state. Any ideas? ...
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SystemVerilog Finite State Machine debugging

I am trying to debug my finite state machine in modelsim and I have no idea what's wrong with the code. It would be helpful to see the state/next_state internal signals in the waveform viewer. Is this ...
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1answer
53 views

“Dynamic” shifter in priority queue implemented on FPGA (SystemVerilog)

I'm implementing a priority queue on FPGA such that if some external signal is up (\$w_r\$) the priorities are evaluated and the priority queue us updated accordingly. The schematic is the following: ...
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169 views

XOR all signals of a vector of two dimensions together

I have a vector that contains 15 elements of 8 bits each. I want to XOR each element: $$ out = f_0 \oplus f_1 \oplus \dots \oplus f_{15} $$ where each \$f_i\$ has 8 bits (it's declared as logic [7:0] ...
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68 views

How can one test that a signal is High-Z when simulating with Verilator?

Say I have this module: module Test( input logic a, output logic b ); assign output = a ? 1'bZ : 1'b1; endmodule; Currently, when testing the ...
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43 views

Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: ...
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3answers
128 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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1answer
58 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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134 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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56 views

Difference between wire and logic for this particular problem

I've worked this problem before in Verilog and no problem at all. Tried the same problem with SV and the problems started. The idea is to just show numbers on the first 3 7-segments based on switches. ...
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In SystemVerilog, must nets be declared with the **logic** data type?

I'm reading Sutherland's "RTL Modeling with SystemVerilog ..." book. On pages 77 and 79 he makes the following claims respectively: The data type must be the keyword logic, which can be specified ...
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1answer
30 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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3answers
323 views

Calculating rolling sum of array

I am trying to implement a rolling average of an array of 12 bit samples in SystemVerilog. New samples are generated and shift into an array via a clocked flip flop. The goal is to have a register ...
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1answer
843 views

What is the difference Verilog race condition, X's propagation and Metastability?

I'm trying to understand Verilog Race Condition X's propagation and Metastability with http:/...
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2answers
46 views

Instantiating modules in SystemVerilog

This is a picture of a system that I am building: (original) I am writing SystemVerilog for the Counter4to3 module, whilst the other modules (Full adder and half adder) have already been provided to ...
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HDL implementation of Numerical Analysis Techniques

I am looking for open-source implementations of Numerical analysis techniques (specifically root-finding techniques like the secant method) on FPGA using any HDL. Would also appreciate if anyone could ...
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1answer
204 views

Verilog style: one large always block vs multiple small always blocks?

Say I have multiple registers set up to update on the same clock, based on different conditions. I could set this up as a series of multiple always blocks: ...
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1answer
68 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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2answers
613 views

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

This question explains how to use Verilog parameters to combine constants from different modules at compile time. I am wondering if it is also possible to use conditional statements to modify ...
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2answers
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Is it possible to make hierarchy of constants in System Verilog?

Is it possible to make a synthesizable hierarchy of constants in System Verilog? For example: There is a board with FPGA and several peripheral ICs. Each IC have some setting registers. Each ...
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1answer
124 views

How do I calculate constant values across several modules at compile time in Verilog?

I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
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2answers
291 views

'11' sequence detector systemverilog

I wrote a program for a '11' sequence detector to be implemented by both Moore and Mealy machine. The problem statement is for z to be asserted high after x has been high for 2 cycles. I've attached ...
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Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...