Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
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My FIR filter inputs and outputs are either giving zero or xxx on Systemverilog
I am trying to design an FIR filter which reads very small 10 bit decimal fractions of 2 integer bits and 8 fractional bits as the input and coefficients. But anytime I run the testbench my ...
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Dataflow operation on a variable is making it a don't care term (Verilog)
I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
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Detect a 1 to 0 transition in an input in Verilog
I'm practicing Verilog using the HDLBits website, and I am trying to solve this problem where I have been given a 32-bit wide input signal and I have to detect whenever a ...
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Synthesis tool support for system verilog nested interfaces [closed]
Does any one know an EDA synthesis tool for SystemVerilog nested interfaces?
A nested interface is an interface inside another interface.
I am targetting both FPGA and IC synthesizers.
Thank you for ...
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Instantiating an array of modules in Verilog without using a loop
Let's say I have a module called mymodule. I need to call it 10 times in my top_module file. I have seen someone on ResearchGate ...
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Questasim Unable to find VHDL package not compiled into work
I'm currently trying to simulate a VHDL module with a SV testbench.
The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the ...
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3
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How to use variable wire data as an integer data for part select? [duplicate]
I am trying to control the width of data bus using part select.
But, the following error occurs:
r_count is not a constant.
Is there a way in which I can use the ...
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Logical AND vs Bitwise AND for single bit and multibits [duplicate]
What is the functional and physical difference in using Logical AND ( && ) and Bitwise AND (&&) over singlebit and multibit signals.
Below shared cases.
case 1: A[3:0] & B[3:0] = ?...
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How to use IF/ELSE conditions in xemacs verilog-mode /*AUTO_TEMPLATE();*/
When using autoverilog to instantiate modules the character @ defines the module number. How do I instantiate many instances of the same module and tie some of the ...
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Verilog UDPs : What basic mistake am I making?
I've been designing digital logic in Verilog (and more recently SystemVerilog) since 1998 but I have never had much use for user-defined primitives (UDPs) as they're generally non-synthesizable. Well, ...
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Verilog: Self bitwise logical operation [duplicate]
I want the output out variable to be the output of 4 input AND gates, and the input variable is input [3:0] in;
Is there any ...
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Why don't signals change in For loop in Verilog?
I am trying to write memory elements using for loop. The for loop runs, and I get the value of ...
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What's the correct way of port declaration while instantiating modules in Verilog HDL?
From what I know, if we need to instantiate module1 in module2, then I need to declare all the ...
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How to use "question mark" in start method of UVM?
I am trying to modify the existing code using the start() method in UVM.
Basic code is below:
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Why does this Verilog testbench not undergo a race condition?
This is the testbench in question:
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How do I figure out if my Verilog code output was generated out of race condition?
Apart from physical observation, is there a way to know if my code will undergo a race condition?
For example, the following code has a race condition because both ...
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Assign a new (default) struct to a current struct
System verilog allows defining a structure type with variable initialization. That's is when I declare a struct type, the struct's members are already initialized. I was wondering if there is a way to ...
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Determine which clock of a compound sensitivity list triggered always block
I am trying to implement a non-synthesizable dual-clock FIFO in Verilog (solely for testbench purposes). Since the FIFO has to operate correctly even when both clocks toggle precisely at the same ...
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How do I create a 2D array in Verilog?
I want to use a 2D array in a Verilog testbench. I tried it this way:
...
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How do I instantiate modules within case statements in Verilog HDL?
I am trying to make a sequence detector with 4 modes - Moore machine overlapping & non-overlapping and Mealy machine overlapping & non-overlapping.
But writing my code like this gives me an ...
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Verilog, Question about 'include'
I'm trying to learn how to use the 'include thing properly. I had this basic code that works fine to run some 7 segment displays.
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Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
...
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Problem overridding parametrized UVM objects
In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
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Enabling sampling of coverage group in SystemVerilog
I am trying to run with functional coverage on my code, but I am getting a warning stating:
...
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Queue values are not being accessed
I am planning to implement a maze routing program using Lee's algorithm. After searching some online resources, it seems that it requires a queue implementation for the BFS to work. After storing the ...
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Warning about unused input pin with Verilog 2D array declaration
I want to declare a 2D array in Verilog, and based on the array's row and column, I will be able to access the values. A warning comes in the console showing one of the input pins not being used.
<...
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Simple Verilog problem with $display()
Why do I get 0 in the terminal with this code?
reg y = 4'b1100;
initial begin
$display("y: %b", y);
end
However, if I explicitly define the range, I ...
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32 Bit FileRegister with ALU
Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable.
It should be like figure1 below.
I'm ...
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How to write program counter in SystemVerilog?
I was trying to build an 8-bit program counter, and it should support branching. This is what I wrote:
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SystemVerilog error: Can't unroll generate for; Unable to unroll loop
I am trying to write a code that converts binary to thermometer code. Thermometer (a.k.a. unary) coding is frequently used in digital systems applications to represent a natural number.
In a ...
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Why does this show as a syntax error on Verilog?
I'm a newbie to Verilog, and I'm trying to follow the few youtube videos I've seen that use vscode as text editor for Verilog.
However, I get an error in the Verilog file itself. Here's my code:
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How do you implement two T flip-flops in Verilog with the input and output equations?
I have written this example to try to answer the question. There is one input, x, the clock, and three outputs. The clock pulses on and off, and x becomes 1 at random times for the positive edge of ...
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can we use the value of an input to define the width of other inputs or local variables in verilog?
Suppose we have an external processor gives our design the data width that we are allowed to work with.
for example the the data_width is the processor_data_bus[15:0] (processor_data_bus in 64 bits). ...
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What value will be assigned to x, is it a or ~x?
I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below :
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Matrix multiplier is not working
I am trying to design a matrix multiplier in Verilog using systolic array architecture. If I test the Processing Elements they work but when trying to connect them to build the array they get the ...
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Intuition or rather just knowing when to use flip flops vs combinatorial vs latch always blocks
I understand the differences between these types of circuits, but when it comes to implementation I find myself wondering which I should use. I don't have an intuition for this yet and would like to.
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Expecting datatype compatibility error packed vs unpacked array
I am trying to design a matrix multiplier using systolic arrays architecture. The inputs are 1D arrays with 2's complement 16bits elements. Here is my code:
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Passing register value in Verilog module as input to another module
I use the XADC IP, for which a module na7_chseq_xadc is used to write the digital data from the ADC in registers adc2_out, ...
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How can a systemverilog process suspend itself?
LRM indicates process::suspend() can suspend either its own execution or that of another. So I tried following code:
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How to sample the read data from blocking logic safely by using the interface of SystemVerilog?
I'm trying to read data from combinational logic.
module my_reg(;
...
output reg [31:0] rdata;
)
....
always @(data)
rdata = 32'h18;
and this dut's value ...
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How can I use clk as an input port in Verilog?
I am working on a simple FSM that counts to 3 and will either output 1 or 0 based on if the number of times a 1 is counted on is mod3 = 0.
FSM.sv
...
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Verilog netlist synthesis using assign vs always [duplicate]
If you have some sort of Verilog implementation like:
...
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462
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Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
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467
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Verilog code if else with localparam
What does the Verilog localparam X code below mean? From my understanding it is as follows:
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Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?
For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
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Sign Extension in Verilog [closed]
what is the difference between the following 3 sign extensions
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