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Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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'11' sequence detector systemverilog

I wrote a program for a '11' sequence detector to be implemented by both Moore and Mealy machine. The problem statement is for z to be asserted high after x has been high for 2 cycles. I've attached ...
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2answers
28 views

Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
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2answers
67 views

Connecting the following structure of multipliers and adders in an elegant way in verilog

I am attempting to write a synthesizable verilog (or Systemverilog) module. I also want to make the modul parameterizable, which has presented a problem when trying to connect the following structure ...
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0answers
51 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
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1answer
33 views

A question about instantiating a module with a parameter in systemverilog

I'm now writing a testbench. In my testbench, I want to read the length of a text file and pass it to another module while instantiating. The idea is like this: ...
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2answers
63 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
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1answer
32 views

ModelSIM not generating outputs for any variables

I have been working on this issue for days and have not been able to figure it out. I was hoping one of you could help me solve this issue. So, when I run my SV code in Quartus and compile it, I don'...
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0answers
90 views

Unexpected behaviour of implication operator in SVA

There is an issue I face while using an implication operator in one of my code examples. This code can be found at https://www.edaplayground.com/x/4fVz Code Summary In my code, I have defined ...
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1answer
110 views

Undefined signal in simulation

I am trying to verify a design written in VHDL using SystemVerilog's assertions. however I got a problem when I have a non defined signal'X' Just for example here is a code of a Comparator: ...
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3answers
84 views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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1answer
100 views

Net type, variable type, data type and data objects

I am really confused by the conception of net type, variable type, data type and data objects in SystemVerilog. I am using the simulator inside Xilinx Vivado 2018.02 for all the following codes. <...
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1answer
83 views

How to write constraint file for the divided clock in Verilog?

I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
60 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
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1answer
73 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
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1answer
67 views

How exactly does $cast work

When a $cast is executed between a base and a derived class objects, does it allocate more memory for the derived class handle? ...
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1answer
49 views

Using two different clocks in my assertion

I am using SystemVerilog to write assertions in order to test the behavior of my design. In my design I have two clock : the usual CLK_int and another clock called ...
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1answer
42 views

How to assert multiple concurrent assertions in system verilog?

I want to do something like this using concurrent assertions (I want to check that when from_clk changes to_clk must change and when to_clk changes from_clk must change): ...
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2answers
133 views

SystemVerilog: Race condition in memory

Hello I'll be brief because my English isn't good thank you for your patience I'm working on a system that drives this memory: ...
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4answers
308 views

Toggle output using Verilog

Can anybody explain this code to me? ...
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0answers
55 views

SDF back annotation in systemVerilog design using interfaces

I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the ...
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1answer
95 views

always_ff is always executed earlier than always_comb in ModelSim

I have an exercise that separating comb logic from sequential logic in always_ff block. However, I found that the ordering of always_comb and always_ff executions is different between different ...
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1answer
54 views

verilog code for bitlength operation

What is the Verilog code for bitlength operation. Example: If Y=45897, I need BitLength(Y)=16. verilog code for BitLength(Y) is ? Please help me to write this.
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1answer
175 views

Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
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1answer
38 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
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1answer
96 views

Will temp variable in always_comb create latch

I have following code snippet where a temp variable is used to count number of 1s in an array: ...
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2answers
285 views

Bidirectional assignment in Systemverilog

I need to create mux block that works with inout pins. My module has n inputs and n outputs, I want to be able to switch between different outputs. The problem that I am currently having is that I ...
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1answer
214 views

System verilog instantiation of parameterized module

If I have a mymodule that has parameters and I am instantiating this mymodule inside a top level block which has a few sub module and mymodule is also a submoulde then when instantiating mymodule ...
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0answers
36 views

IVerilog in CMD: `include statement not working

I've written the code for every component in a simplyfied PIC Microcontroller in different .v files. To instantiate a module present in a file different to the testbench, I wrote the following line of ...
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2answers
424 views

Opening and reading pixel values from bitmap images in Modelsim

How do I open a bitmap image, read the pixel data (24 bits) and store it in a memory that I created in a Verilog module in ModelSim? How do I open the below image in Modelsim? Is it possible in the ...
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2answers
104 views

Design a circuit from logic gates, flip flops and/or multiplexers

I would like to create a simple circuit from logic gates, flip-flops (no RLC components) to do the following task: This circuit has 5 inputs (4 positive real-valued signals \$x_1, x_2, x_3, x_4\$ and ...
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1answer
67 views

SystemVerilog Assertion consecutive repetition for overlapping sequences

I have a specification as follows : "Check that 'valido' is not asserted when 'validi=1' for only two, one or zero consecutive clk cycles." the following assertion FAILS (n-3 times) on a sequence of ...
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0answers
68 views

Variable clock counts in System Verilog assertion property

Is there a way to introduce variable clock counts in assertion properties as shown in the example below ? ...
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0answers
127 views

System verilog - streaming operator multidimensional array to stream of bits

I cant figure out how to take multidimensional array such as: bit unsigned [10:0] img [3:0][3:0]; Think of it as an 4X4 image that each pixel is 11 bits in my ...
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0answers
446 views

How to use struct in an interface?

Since it's not possible to have an interface in a package, what is the best practice to manage interface containing struct of a package ? ...
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1answer
107 views

Is it possible to use `.*` in SystemVerilog to register interfaces' elements?

Let's say I have one interface, I'd like to ...
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1answer
229 views

How to assert multiple properties in System Verilog

What is the most efficient way to assert multiple properties in SV ? Example: ...
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0answers
192 views

“range must be the final index in the indexed name”, system verilog slice array and send to module

I have an 2d array (and 1 more dimension of 11 bits),and I dont want to send to module "cb" the entire 2d array, but only part of him, and I understood that if I want to slice an array I cant use not ...
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1answer
84 views

Read and write simultaneously from different indices of an associative array in system verilog

Is it possible to read and write simultaneously (In parallel) from different indices of an associative array in System Verilog ?
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1answer
27 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1answer
44 views

Implementing a Mealy Machine in Verilog

I have a piece of code that I don't understand: always_ff @(posedge CLK) state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate; ...
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1answer
44 views

SystemVerilog: selecting bits without storing calculation in variable

Is there really no way to select bits straight from a calculation without giving them a name and then selecting the bits from the name in SystemVerilog? ...
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1answer
427 views

SystemVerilog Enumerated Multi-Domain Array -> how to declare/define?

Here is an example how to define the 2*N array of enum types of {S0,S1,S2,S3}: typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} state_t; (*) So, each element of the above 2*N array could be either S0 ...
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1answer
753 views

Testbench for simple register file

I want to test my register file before connecting it to ALU. So I wrote a testbench for my register file. ...
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1answer
243 views

System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations

Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
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3answers
3k views

Using $floor in Verilog

Verilog has a bunch of math system functions. I'm trying to use $floor in my Verilog code but I'm getting this message: System function call floor is not allowed here Does anyone know why I'm ...
2
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1answer
665 views

SystemVerilog: Sensitivity list of always_comb

It seems to me that always_comb is not sensitive to variables assigned in the block itself. For example, the following block: ...
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1answer
1k views

SystemVerilog: How to give different parameters to modules in the same array?

In my design, I wanted to use a number of counters with different initial values on reset. Therefore I defined the counter module as follows: ...
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1answer
312 views

Verilog modulus operator for wrapping around a range

My background is in software and I'm new to (System)Verilog so when tasked with implementing a caesar shifter (shift each letter in a string by N letters, wrapping around if necessary e.g. ABCXYZ ...
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0answers
113 views

Load instruction fetching wrong value

I have written some code for mips but in my program the LW insturction didnot fetch the correct answer. For example: ...