Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

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8
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2answers
26k views

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that ...
2
votes
1answer
112 views

How do I calculate constant values across several modules at compile time in Verilog?

I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
2
votes
1answer
35k views

Instantiating multidimensional array in system verilog

I want to create an array in systemverilog which has n entries of m bits. logic [n-1:0] arr [m-1:0]; (a) Is this the right way to do it? What if I change the ...
4
votes
6answers
3k views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
8
votes
3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
1
vote
3answers
255 views

Calculating rolling sum of array

I am trying to implement a rolling average of an array of 12 bit samples in SystemVerilog. New samples are generated and shift into an array via a clocked flip flop. The goal is to have a register ...
3
votes
2answers
1k views

Generate flip-flops using only combinational logic

Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation. My initial attempt, which ...
1
vote
3answers
2k views

How to remove this warning in Verilog?

I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement ...
0
votes
2answers
124 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
0
votes
1answer
20k views

Verilog 8 Bit ALU

Here's what I have so far but I'm stuck with what to do for the f values for the last two and whether the if statement syntax is correct. Any tips? ...