Questions tagged [systemverilog-assertions]

SystemVerilog Assertions are used to check if properties of a digital design are satisfied or to confirm that a certain test is run during simulation. They are used for both simulation and static analysis (model checking).

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$past is not working as expected in SystemVerilog

I am implementing a counter in SystemVerilog. To check the proper functionality of the circuit (if the increment happened correctly), I have the assertion below: ...
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Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
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SystemVerilog Assertions wizard

A few years ago, Axiom Design Automation (acquired by Mentor Graphics in 2013) had a tool called Assertion Studio. It was a high-quality wizard to create assertions (including SystemVerilog ones). Are ...
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Problem with back annotated netlist signals naming for simulation purposes in Modelsim

Some of the labels used in back-annotated netlist descriptions generated by Microchip (Microsemi) Libero rely on forward slash naming conventions as shown below ...
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Error message vsim-3171 keeps popping up in Modelsim DE 2021.1 even though it was solved in Modelsim ME 10.2c

I have a test bench where I'm using a SystemVerilog bind construct. My test bench follows a similar organization to the one described at this link Every time I run it, error vsim-3171 shows up. I came ...
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SystemVerilog Assertions

For the following property assertion: property COMPLEX_SEQ; @(negedge CLK) disable iff (X) (C ##1 B[*1:3] ##1 A) |=> (J[*4] ##1 K); endproperty And ...
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How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format. signal a should never be 2 until it attains the value 1 How can we do that?
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