Questions tagged [testbench]

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Verification of asynchronous FIFO

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings. The goal is to verify this design by using the Tb components, so no UVM at all. I ...
1 vote
1 answer
47 views

Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
1 vote
1 answer
54 views

Applying a force in a list of wires using Verilog

I want to apply a force command in a list of wires in Verilog. My netlist looks something like this: ...
1 vote
1 answer
91 views

Dense Neuron Neural Network in Verilog

I am trying to build NN in system verilog, but I am facing a problem with neuron implementaion, as it only displays 'x'. ...
2 votes
1 answer
34 views

Why I am having x as output from ReLU?

I am trying to test ReLU, but it always gives 'x' for the output. ...
1 vote
1 answer
58 views

How to fix the include statement error in Verilog testbench code?

I implemented the four-bit ripple carry adder using Verilog. However, I did not understand why the compiler generated this error Include file FBaddsub.v not found No top level modules, and no -s ...
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1 vote
1 answer
82 views

Cannot perform a part select on array error

I'm trying to read a file and use its data as inputs to my design. The file looks like this: ...
2 votes
1 answer
71 views

My test bench in VHDL is always showing U for all values

I am learning VHDL for a University course. My code: ...
1 vote
1 answer
31 views

Simulation waveform differs from testbench delay specification

I'm running the following Verilog code, and I got the image below as a result. I'm curious why the dout and start signal transitions don't coincide with the delays definitions on the testbench. Does ...
1 vote
1 answer
168 views

Problem with testing verilog instances using random vectors

I have a set of test vectors saved in a csv file and formatted as follows: 0010,1000,1010 1110,0101,0001 1001,0001,0000 These are randomly generated and can be of ...
1 vote
1 answer
80 views

Parameter binding error in Icarus Verilog

I am trying to design a shift register that can have both serial and parallel outputs. My implementation is posted below: ...
0 votes
1 answer
281 views

Problem with reading a .csv file into a Verilog module

I was trying to read a .csv file and use its contents. The csv is formatted as: 0001,1010,1110 0101,1100,1001 My code is: ...
1 vote
1 answer
162 views

SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
1 vote
1 answer
303 views

SystemVerilog ring oscillator simulation with different delays

I am currently encountering issues with my ring oscillator simulation in SystemVerilog, which I cannot explain. Toolchain: ...
1 vote
1 answer
109 views

SystemVerilog - clk not toggling in verification

I'm testing an AES encryption machine that's written in Verilog. I know that the DUT is perfect because I created a Verilog testbench. When I simulate in VCS, the clk stays at 0 the whole time and the ...
0 votes
1 answer
536 views

Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
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1 vote
1 answer
122 views

MAX134 and MAX3001E Troubleshooting

This is going to be a long question because I plan to include a lot of context that I feel is important to grasp the full scope of my issue. I am currently a senior year university student hard at ...
0 votes
1 answer
67 views

Test/programming rig with spring-loaded probes/connectors

I have ESP32-CAM module with two rows of 0.1" male pins. The pins are 0.22" high. Here is a picture: I would like to trim them, so they are too short to mate with the corresponding female ...
2 votes
1 answer
219 views

Resources for learning Open Source VHDL Verification Methodology (OSVVM) [closed]

I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following: Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based ...
1 vote
1 answer
110 views

Signals acting weirdly in VHDL

I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example if rising_edge(clk) then but in this testbench, after the first wait ...
1 vote
1 answer
77 views

8bitworkshop(verilog) to terminal transition

I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
0 votes
1 answer
502 views

Delays and/or how to manually cycle clock in a loop when building Verilog testbench to test FSM for microcode/ROM conversion

I am working on a project wherein I need to convert a Finite State Machine coded in Verilog into a ROM. In order to do this I need to create a memory file for the ROM version of the FSM which stores ...
0 votes
1 answer
994 views

Verilog Simulation: 16 to 1 Mux Output High Z

Verilog beginner here. I am attempting to implement a 16to1 mux by instantiating four 4to1 muxes. Here is my code: .v file: ...
0 votes
1 answer
33 views

Clock network remains at x when applying fast clock frequencies

I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of ...
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1 vote
1 answer
3k views

Why does this file give me "syntax error: I give up." in verilog program?

This is my original file saved as "example.v" module example(a,b,y); input b,y; output a; assign a=b&y; endmodule This is my testbench file ...
0 votes
1 answer
56 views

Off the Shelf Current Sensors?

What are the tradeoffs between making my own current sense setup with a precision shunt resistor and ADC versus just buying something? What are the most popular COTS current sensors for shunt current ...
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0 votes
2 answers
190 views

Verilog Code test bench problem

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2 votes
1 answer
160 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
0 votes
1 answer
47 views

Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
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0 votes
1 answer
148 views

Why does my VHDL simulation fail after one input for this device?

EDIT: Found a solution. See the bottom of the post I am wondering why my simulation of the following entity fails to run for more than one input. When I change the inputs, the system crashes, and I ...
1 vote
1 answer
57 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
0 votes
1 answer
155 views

Can I use a bench power supply as a substitute for a 9V DC adapter?

I want to test a guitar pedal but I don’t have a 9V adapter around - but I do have access to a DC power supply. Is it possible* to alligator clip the +ve to the power terminal and ground to the ...
1 vote
1 answer
106 views

Test bench when design is pipelined

I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
0 votes
2 answers
2k views

Why do we declare the inputs of our design as reg in testbench and outputs as wire?

Why do we declare the inputs of our design as reg in testbench and outputs as wire?
1 vote
2 answers
125 views

Testbench using Task operation [closed]

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...
1 vote
1 answer
291 views

How more efficiently can I write the test bench for a MOD 16 asynchronous counter using JK flip flop?

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2 votes
2 answers
114 views

Creating a three phase current system with e.g. 70Hz instead of 50Hz

I am doing magnetic field measurements on a 3-phase cable dummy, in order to develope a distance measurement system for power cables. This is a uni research project. For a test setup I want to create ...
1 vote
0 answers
169 views

TTL in an RF switch

I am hoping to find help on how to properly connect supply voltage to my switch assembly in order to actuate. My switch has input requirement of +15, -15, GND, and +5V. Also, the 5v logic inputs. ...
3 votes
1 answer
630 views

VHDL Clock Divider Problem

I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code: ...
3 votes
2 answers
802 views

How can I improve my testbench for testing a 1024x4 RAM memory in Verilog

This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog". Basically, I have modified the previous solution in an ...
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0 votes
0 answers
321 views

ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
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1 vote
1 answer
136 views

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result? I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...
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-2 votes
1 answer
76 views

Not getting correct results displayed from register

I am trying to input the numbers 1,0,3,2,32'hFFFFFFFF,32'h00000001 into the registers 0,1,2,3,6, and 7 respectively. I am doing this through always @(posedge clk) ...
0 votes
2 answers
273 views

Can I feed my level shifter with a voltage divider?

I need to level shift 3V3 to 2V8. I have a 2V8 source but that'll require some patching wires on testpads and as such I would like to avoid it. I'm wondering: would it be safe to feed the SN74LVC245AN ...
3 votes
1 answer
657 views

Pass parameters to covergroups in SV Testbench

I am trying to create a parameterized covergroup in my testbench as follows: ...
0 votes
1 answer
684 views

Syntax error near "else" in Verilog, in an initial block, next to assert

I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have: ...
-1 votes
2 answers
156 views

Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...
1 vote
1 answer
921 views

How do I implement the clock into this testbench?

I am trying to write a testbench for an adder/subtractor, but when it compiles, the clock does not shift. Here is the Verilog code for the adder/subtractor: ...
0 votes
1 answer
286 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
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1 vote
2 answers
87 views

How to efficiently mux many signals to/from a climate chamber?

I am building a setup to measure various parameters across a temperature range from -55°C to +125°C. The devices under test will be placed in a climate chamber. There are around 10 signals from each ...
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