Questions tagged [testbench]

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46 views

8bitworkshop(verilog) to terminal transition

I have been working through very basic Verilog code examples at https://8bitworkshop.com (supports a book I am following). I understand there are a few good online options available and will pursue ...
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1answer
44 views

Delays and/or how to manually cycle clock in a loop when building Verilog testbench to test FSM for microcode/ROM conversion

I am working on a project wherein I need to convert a Finite State Machine coded in Verilog into a ROM. In order to do this I need to create a memory file for the ROM version of the FSM which stores ...
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1answer
70 views

Verilog Simulation: 16 to 1 Mux Output High Z

Verilog beginner here. I am attempting to implement a 16to1 mux by instantiating four 4to1 muxes. Here is my code: .v file: ...
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1answer
29 views

Clock network remains at x when applying fast clock frequencies

I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of ...
0
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1answer
571 views

Why does this file give me "syntax error: I give up." in verilog program?

This is my original file saved as "example.v" module example(a,b,y); input b,y; output a; assign a=b&y; endmodule This is my testbench file ...
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1answer
52 views

Off the Shelf Current Sensors?

What are the tradeoffs between making my own current sense setup with a precision shunt resistor and ADC versus just buying something? What are the most popular COTS current sensors for shunt current ...
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2answers
107 views
2
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1answer
86 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
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1answer
37 views

Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
0
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1answer
92 views

Why does my VHDL simulation fail after one input for this device?

EDIT: Found a solution. See the bottom of the post I am wondering why my simulation of the following entity fails to run for more than one input. When I change the inputs, the system crashes, and I ...
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1answer
49 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
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1answer
92 views

Can I use a bench power supply as a substitute for a 9V DC adapter?

I want to test a guitar pedal but I don’t have a 9V adapter around - but I do have access to a DC power supply. Is it possible* to alligator clip the +ve to the power terminal and ground to the ...
1
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1answer
101 views

Test bench when design is pipelined

I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
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2answers
496 views

Why do we declare the inputs of our design as reg in testbench and outputs as wire?

Why do we declare the inputs of our design as reg in testbench and outputs as wire?
1
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2answers
70 views

Testbench using Task operation [closed]

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...
2
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2answers
99 views

Creating a three phase current system with e.g. 70Hz instead of 50Hz

I am doing magnetic field measurements on a 3-phase cable dummy, in order to develope a distance measurement system for power cables. This is a uni research project. For a test setup I want to create ...
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0answers
91 views

TTL in an RF switch

I am hoping to find help on how to properly connect supply voltage to my switch assembly in order to actuate. My switch has input requirement of +15, -15, GND, and +5V. Also, the 5v logic inputs. ...
3
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1answer
352 views

VHDL Clock Divider Problem

I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code: ...
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2answers
345 views

How can I improve my testbench for testing a 1024x4 RAM memory in Verilog

This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog". Basically, I have modified the previous solution in an ...
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0answers
186 views

ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
1
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1answer
98 views

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result? I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...
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1answer
57 views

Not getting correct results displayed from register

I am trying to input the numbers 1,0,3,2,32'hFFFFFFFF,32'h00000001 into the registers 0,1,2,3,6, and 7 respectively. I am doing this through always @(posedge clk) ...
0
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2answers
200 views

Can I feed my level shifter with a voltage divider?

I need to level shift 3V3 to 2V8. I have a 2V8 source but that'll require some patching wires on testpads and as such I would like to avoid it. I'm wondering: would it be safe to feed the SN74LVC245AN ...
0
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1answer
328 views

Syntax error near "else" in Verilog, in an initial block, next to assert

I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have: ...
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2answers
52 views

Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...
1
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1answer
81 views

How do I implement the clock into this testbench?

I am trying to write a testbench for an adder/subtractor but when it compiles the clock does not shift. Here is the verilog for the adder/subtractor: ...
0
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1answer
130 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
1
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2answers
79 views

How to efficiently mux many signals to/from a climate chamber?

I am building a setup to measure various parameters across a temperature range from -55°C to +125°C. The devices under test will be placed in a climate chamber. There are around 10 signals from each ...
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0answers
247 views

Using an internal signal in a testbench

I am using HDL Designer and have a pretty large design I need to test. I have created a test bench by using HDL Designer itself and did not do it standalone. Like the title states, I want to know how ...
0
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1answer
87 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
1
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1answer
3k views

Verilog Testbench - wait for specific number of clock cycle edges

In my testbench, I want to wait for two events in sequence: one after 60000 clock cycles and next after additional 5000 clock cycles I know I can wait for clock edges using statement @(posedge clk), ...
0
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2answers
158 views

Ultracapacitor initial voltage drop during discharging

I've been building a test stand for ultracapacitors, with very simple schematic looking like this: simulate this circuit – Schematic created using CircuitLab The resistor on the bottom is to ...
7
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3answers
3k views

VHDL: What is correct way to model open collector output for FPGA?

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though. How should open collector output be defined in a VHDL for an FPGA? How should open collector ...
1
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0answers
417 views

VHDL - rand*real(2**32-1) : can this cause an overflow issue?

I'm studying VHDL implementations of multipliers: I found this one and i'm trying to modify it. Default word size is 8 bit and the design is working (both simulation and synthesis) for any size up to ...
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1answer
1k views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...
2
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2answers
205 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
0
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1answer
1k views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
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1answer
2k views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
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1answer
851 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...
0
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1answer
244 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...
0
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1answer
2k views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
0
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1answer
79 views

Electrical gremlins under high Amp draws

I'm new here so I hope all goes well! I have used an ATX PSU to create a power bench tester for testing automotive headlights. HID in particular which draw around 8-10amps on startup. I have noticed ...
0
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1answer
2k views

Modelsim simulation doesn't work

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
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1answer
116 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
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1answer
853 views

getting outputs in simulation as all high impedance. topic: restoring algorithm for binary division

I am getting outputs of my hardware as all high impedance (ZZZZZ). i tried synthesizing the code and got these warnings. I think there might be a problem in the test bench i am trying to run. ...
1
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1answer
974 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...
-1
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1answer
658 views

Error: illegal Verilog output port specification

I am having problems with my verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times but I cannot ...
1
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1answer
199 views

VHDL Algorithm state machine output

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4answers
1k views

Usage of "initial" in Verilog module description

I'm writting a code and I have 2 dumb questions: 1- Is it a bad practice to use "initial" in the module description? I'm asking this because I have a frequency divider with 2 signals (clk_in and ...