Newest 'testbench' Questions

-2

votes

1answer

40 views

Why do we declare the inputs of our design as reg in testbench and outputs as wire?

asked yesterday

Akhil Mehta

152 bronze badges

1

vote

2answers

41 views

Testbench using Task operation

I have to write a testbench using "tasks" to verify the functionality of an 8-bit ALU. My tasks are not getting simulated properly in EDA playground. Can anyone please tell me where my ...

verilog system-verilog hdl testbench

asked yesterday

Akhil Mehta

152 bronze badges

0

votes

2answers

48 views

How more efficiently can I write the test bench for a MOD 16 asynchronous counter using JK flip flop?

...

verilog xilinx testbench

asked Jan 21 at 4:57

SUSMITHA M

11 bronze badge

2

votes

2answers

75 views

Creating a three phase current system with e.g. 70Hz instead of 50Hz

I am doing magnetic field measurements on a 3-phase cable dummy, in order to develope a distance measurement system for power cables. This is a uni research project. For a test setup I want to create ...

three-phase testbench

asked Jan 19 at 16:43

Andreas Schuldei

212 bronze badges

0

votes

0answers

14 views

Initiating DDR Reads From Zynq PL With DMA

I am trying to initiate reads from the Zynq PL over Xilinx AXI DMA IP, but I haven't been able to find an example to make things fully clear for me. If I am using the DMA in Direct Register Mode, what'...

xilinx vivado dma testbench zynq

asked Jan 13 at 2:56

Jake Daly

11 bronze badge

0

votes

0answers

40 views

Value XX In the testbench

Thanks for considering and spending your time. I'm trying to simulate UART VHDL code that I have written (which is not complete yet), but in the testbench I see XX value for the signal rx_data_out. I ...

vhdl uart testbench

asked Jan 5 at 16:20

mary

1

vote

0answers

59 views

TTL in an RF switch

I am hoping to find help on how to properly connect supply voltage to my switch assembly in order to actuate. My switch has input requirement of +15, -15, GND, and +5V. Also, the 5v logic inputs. ...

power-supply ttl testbench

asked Nov 24 '20 at 19:33

Kat_2112

112 bronze badges

0

votes

0answers

31 views

I have a Potentiometer - 5 k ohm 2W from a Mosa DC Welder; With Strange Test Readings

The pot is a Digikey part. The readings for the 5 kΩ pot start at .025 Ω to a high of 1.91 kΩ ... but it occurs 75% of the way into the rotation of the single turn pot, and then it drops to 1.39 kΩ at ...

potentiometer testbench

asked Oct 10 '20 at 15:27

morganplus8

11 bronze badge

2

votes

1answer

108 views

VHDL Clock Divider Problem

I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code: ...

vhdl testbench

asked Sep 10 '20 at 17:45

dubistweltmeister

616 bronze badges

0

votes

0answers

18 views

Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...

vhdl quartus modelsim testbench

asked Sep 9 '20 at 12:20

sr_m

92 bronze badges

1

vote

2answers

71 views

How can I improve my testbench for testing a 1024x4 RAM memory in Verilog

This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog". Basically, I have modified the previous solution in an ...

verilog ram testbench

asked Aug 31 '20 at 23:29

aLoHa

3352 silver badges11 bronze badges

0

votes

0answers

52 views

ModelSim does not run until “$stop” command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...

fpga verilog modelsim testbench libero

asked Aug 20 '20 at 15:44

yer

755 bronze badges

1

vote

1answer

84 views

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result? I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...

digital-logic verilog ram testbench

asked Aug 15 '20 at 16:56

aLoHa

3352 silver badges11 bronze badges

-2

votes

1answer

50 views

Not getting correct results displayed from register

I am trying to input the numbers 1,0,3,2,32'hFFFFFFFF,32'h00000001 into the registers 0,1,2,3,6, and 7 respectively. I am doing this through always @(posedge clk) ...

verilog multiplexer register alu testbench

asked Aug 5 '20 at 20:23

Nazar Zien

13 bronze badges

0

votes

2answers

149 views

Can I feed my level shifter with a voltage divider?

I need to level shift 3V3 to 2V8. I have a 2V8 source but that'll require some patching wires on testpads and as such I would like to avoid it. I'm wondering: would it be safe to feed the SN74LVC245AN ...

voltage-divider level-shifting testbench

asked Jul 28 '20 at 13:28

Tarick Welling

3822 silver badges13 bronze badges

0

votes

0answers

50 views

VHDL testbench for shift register 7495

I`m new to VHDL and i don't know how to write the testbench code for a 7495 register. I need to do this for a college project. Any help is greatly appreciated. This is the Design Source code i`ve ...

vhdl simulation shift-register vivado testbench

asked May 17 '20 at 19:00

andreb

1

0

votes

1answer

107 views

Syntax error near “else” in Verilog, in an initial block, next to assert

I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have: ...

verilog alu testbench

asked May 1 '20 at 19:22

Blucario

31 bronze badge

-1

votes

2answers

36 views

Test Verilog FSM for state with no reset

My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...

verilog state-machines test testbench

asked Apr 15 '20 at 20:25

Voxorin

11 bronze badge

1

vote

1answer

70 views

How do I implement the clock into this testbench?

I am trying to write a testbench for an adder/subtractor but when it compiles the clock does not shift. Here is the verilog for the adder/subtractor: ...

verilog clock adder testbench

asked Jan 29 '20 at 14:40

Colin Charlesworth

111 bronze badge

0

votes

1answer

83 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...

fpga vhdl xilinx testbench

asked Dec 19 '19 at 17:24

karthik

213 bronze badges

1

vote

2answers

70 views

How to efficiently mux many signals to/from a climate chamber?

I am building a setup to measure various parameters across a temperature range from -55°C to +125°C. The devices under test will be placed in a climate chamber. There are around 10 signals from each ...

temperature test-equipment testbench

asked Oct 19 '19 at 19:19

filo

8,1961 gold badge19 silver badges39 bronze badges

1

vote

0answers

126 views

Using an internal signal in a testbench

I am using HDL Designer and have a pretty large design I need to test. I have created a test bench by using HDL Designer itself and did not do it standalone. Like the title states, I want to know how ...

vhdl testbench

asked Oct 2 '19 at 17:38

nettek

9832 gold badges10 silver badges21 bronze badges

0

votes

1answer

59 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...

fpga hdl state-machines testbench

asked Sep 27 '19 at 6:14

nettek

9832 gold badges10 silver badges21 bronze badges

0

votes

1answer

1k views

Verilog Testbench - wait for specific number of clock cycle edges

In my testbench, I want to wait for two events in sequence: one after 60000 clock cycles and next after additional 5000 clock cycles I know I can wait for clock edges using statement @(posedge clk), ...

verilog testbench

asked Sep 11 '19 at 5:42

nurabha

8073 gold badges13 silver badges23 bronze badges

0

votes

2answers

101 views

Ultracapacitor initial voltage drop during discharging

I've been building a test stand for ultracapacitors, with very simple schematic looking like this: simulate this circuit – Schematic created using CircuitLab The resistor on the bottom is to ...

voltage charging discharge supercapacitor testbench

asked Jun 23 '19 at 7:36

QST

8410 bronze badges

7

votes

3answers

2k views

VHDL: What is correct way to model open collector output for FPGA?

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though. How should open collector output be defined in a VHDL for an FPGA? How should open collector ...

fpga vhdl i2c testbench

asked Jun 13 '19 at 20:31

quantum231

8,39819 gold badges76 silver badges155 bronze badges

1

vote

0answers

265 views

VHDL - rand*real(2**32-1) : can this cause an overflow issue?

I'm studying VHDL implementations of multipliers: I found this one and i'm trying to modify it. Default word size is 8 bit and the design is working (both simulation and synthesis) for any size up to ...

vhdl testbench

asked May 6 '19 at 8:54

a_bet

3233 silver badges12 bronze badges

0

votes

1answer

618 views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...

verilog simulation vivado testbench

asked Apr 29 '19 at 17:02

Rr Bb

638 bronze badges

2

votes

2answers

159 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...

verilog simulation xilinx delay testbench

asked Mar 27 '19 at 6:00

Marco Castro

1771 silver badge10 bronze badges

0

votes

1answer

523 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...

fpga verilog modelsim testbench

asked Feb 9 '19 at 13:20

thebionicandroid

133 bronze badges

0

votes

1answer

2k views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...

fpga vhdl modelsim testbench questasim

asked Dec 18 '18 at 20:03

rooter

33 bronze badges

0

votes

0answers

64 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...

digital-logic vhdl verilog system-verilog testbench

asked Dec 18 '18 at 5:31

user2077648

916 bronze badges

-1

votes

1answer

573 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...

verilog uart testbench

asked Nov 27 '18 at 4:59

MaxFrost

173 bronze badges

0

votes

1answer

116 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...

vhdl testbench

asked Oct 13 '18 at 18:00

Vinny Vigs

1

-1

votes

1answer

2k views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...

vhdl simulation lattice testbench

asked Sep 28 '18 at 15:45

schadjo

1,0546 silver badges16 bronze badges

0

votes

1answer

74 views

Electrical gremlins under high Amp draws

I'm new here so I hope all goes well! I have used an ATX PSU to create a power bench tester for testing automotive headlights. HID in particular which draw around 8-10amps on startup. I have noticed ...

power-supply hid testbench workbench

asked Aug 29 '18 at 21:35

Tisho

53 bronze badges

0

votes

1answer

1k views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...

vhdl modelsim testbench

asked Jul 21 '18 at 20:05

Toojer

32 bronze badges

0

votes

1answer

80 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...

system-verilog verification random-number testbench

asked Jul 4 '18 at 20:05

pavan sp

54 bronze badges

-1

votes

1answer

652 views

getting outputs in simulation as all high impedance. topic: restoring algorithm for binary division

I am getting outputs of my hardware as all high impedance (ZZZZZ). i tried synthesizing the code and got these warnings. I think there might be a problem in the test bench i am trying to run. ...

verilog high-impedance testbench

asked Jul 3 '18 at 2:03

Eris Drater

231 silver badge4 bronze badges

0

votes

1answer

825 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...

verilog flipflop modelsim testbench

asked Jun 1 '18 at 15:40

3bdalla

8051 gold badge11 silver badges22 bronze badges

0

votes

0answers

104 views

Adding of frequency divider causes no output VHDL

I'm trying to get the output from this code. The output is not showing after adding the frequency divider. Before the frequency divider, the code worked well and display the output. This is my code <...

vhdl frequency testbench

asked Mar 20 '18 at 14:59

Yap YiXien

416 bronze badges

-1

votes

1answer

536 views

Error: illegal Verilog output port specification

I am having problems with my verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times but I cannot ...

verilog output input error testbench

asked Mar 15 '18 at 19:48

user71126

1

vote

1answer

184 views

VHDL Algorithm state machine output

...

vhdl assembly testbench

asked Mar 13 '18 at 12:08

Yap YiXien

416 bronze badges

2

votes

4answers

1k views

Usage of “initial” in Verilog module description

I'm writting a code and I have 2 dumb questions: 1- Is it a bad practice to use "initial" in the module description? I'm asking this because I have a frequency divider with 2 signals (clk_in and ...

fpga verilog testbench

asked Jan 28 '18 at 14:02

Jose de arimatea

1134 silver badges12 bronze badges

-1

votes

1answer

367 views

Output internal reg to a .txt in Verilog

I would like to write an internal reg to a txt file. I have tried something like: ...

verilog testbench

asked Jan 22 '18 at 8:47

user204415

291 gold badge1 silver badge6 bronze badges

2

votes

1answer

408 views

What options exist to verify Avalon-MM slave component?

I am writing an Avalon-MM slave. It shall connect to Nios II as master device. What options exist to write testbench for it? I must be sure that an Avalon-MM master can correctly read/write it. I ...

fpga intel-fpga testbench

asked Dec 29 '17 at 21:45

quantum231

8,39819 gold badges76 silver badges155 bronze badges

0

votes

1answer

398 views

problem with verilog testbench

I have problem with clock signal in Verilog test bench. I've tried almost every possible ways to create clock, but in the waveform it's U meaning "Unknown". Here is my code for clock (...

verilog testbench

asked Nov 8 '17 at 11:26

Foad Hoseyni

216 bronze badges

11

votes

3answers

2k views

How do I protect myself when testing a PCB that involves an AC line?

I have to test prototype PCBs that convert household AC into several DC voltage levels. I concern about my safety when working with AC and would like to know how to properly setup a testbench that, ...

ac safety circuit-breaker testbench rcd

asked Oct 12 '17 at 9:57

Natthapol Vanasrivilai

2351 silver badge8 bronze badges

0

votes

2answers

351 views

Load image into VHDL testbench

Is there a standard way to load an image into VHDL testbench so image processing logic output can be tested? Obviously there will be an output from the testbench, also an image that must be possible ...

vhdl imageprocessing testbench

asked Aug 14 '17 at 22:23

quantum231

8,39819 gold badges76 silver badges155 bronze badges

0

votes

1answer

118 views

designing image debayer block, how should the testbench be written

A debayer block inputs image from a CCD Bayer filter and then estimates the missing color information for each pixel. The data comes from a camera. How should one go about writing a testbench for ...

vhdl imageprocessing testbench

asked Aug 14 '17 at 22:05

quantum231

8,39819 gold badges76 silver badges155 bronze badges

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