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How to create a 400 MHz synced clock from 1200 MHz in Verilog?

I'm trying to generate a 400 MHz synced clock from 1200 MHz. ...
Carter's user avatar
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2 votes
2 answers
39 views

The quality of testbenches with UVM testing

This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied. So I come from a hardware engineering background, as I was discussing how ...
Lannan Jiang's user avatar
1 vote
1 answer
54 views

Verilog set bit counter

I'm trying to create a Verilog program that would display the digit with greater number of bits set. The code is working. However, it counts the bits from the previous values instead of its current ...
Paula Bianca Pascual's user avatar
1 vote
2 answers
101 views

Null pointer access error in SystemVerilog

I am practising the SystemVerilog class concepts. I got an error while running the code: Fatal Error: RUNTIME_0029 code.sv (67): Null pointer access. Here is ...
Kartikey's user avatar
0 votes
0 answers
13 views

Questa instantiation during testbench issues

I'm new to EDA and trying to get the hang of simulations in Questa. I wrote the Verilog code "clock_divider" and the testbench "tb_clock_divider". They both compile successfully ...
Raquel's user avatar
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1 vote
2 answers
49 views

Can an event name be manipulated in Verilog/SystemVerilog?

In a Verilog testbench.v, there are commands that are used in a task. ...
Carter's user avatar
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1 vote
2 answers
67 views

Verilog Double Counter Testbench Issues

I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. ...
aofarmakis's user avatar
-1 votes
1 answer
81 views

Program block avoiding race condition

I have a small design that assigns a value to a variable "addr" using initial block. ...
totochan1965's user avatar
1 vote
1 answer
112 views

Assign statement in testbench doesn't seem to work as it should

I have a small Verilog code example asked as an interview question. I am not sure why it prints "p=01" but not "00" since assign should update <...
totochan1965's user avatar
1 vote
1 answer
104 views

I am trying to make a 32-bit mod operator in Verilog, but the result returns 32'xxxx in testbench. How can I fix this?

...
kayıp balık's user avatar
1 vote
2 answers
194 views

How can we safely test a mains powered device?

We have small non-isolated 230VAC devices that transform mains to LEDs running at 32V, 20mA. The lights are directly connected to live, neutral and earth like a standard lightbulb would be. Since ...
sandervd's user avatar
1 vote
1 answer
137 views

How to make a waveform simulation in Quartus II from testbench module

I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
South goodman's user avatar
12 votes
5 answers
4k views

Is it recommended to set the current limit on a bench power supply by shorting it?

I have a Rapid 85-1901 switching mode 0-20V 0-5A bench power supply: Without a load attached the current shows 0A no matter how you turn the dial. After searching how to set the current limit online, ...
Danny Beckett's user avatar
0 votes
1 answer
273 views

How can I make addition in Verilog wraparound?

I'm creating an ALU in Verilog, and I would like overflow to be dealt with by wrapping around to lower values. For example: ...
Connor's user avatar
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1 answer
271 views

Why isn't my addition in Verilog overflowing?

I'm testing a basic ALU in Vivado using a testbench. One of my tests checks that overflow works correctly. The test has the following form: ...
Connor's user avatar
  • 399
2 votes
2 answers
129 views

Verilog UDPs : What basic mistake am I making?

I've been designing digital logic in Verilog (and more recently SystemVerilog) since 1998 but I have never had much use for user-defined primitives (UDPs) as they're generally non-synthesizable. Well, ...
jdb2's user avatar
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2 votes
1 answer
242 views

Need help debugging Verilog I2C slave code

As you can see in the waveforms and the code after the start (busy line goes high) condition occurs, I start sending the slave address bit by bit in the testbench through the ...
Sushant Chachadi's user avatar
1 vote
1 answer
234 views

Unable to open input file in Verilog

I'm having trouble running my Verilog code. Here is my code: module hello(A,B); input A; output B; assign B = A; endmodule And here is my testbench: ...
Afonso Britto's user avatar
1 vote
2 answers
95 views

How to use "question mark" in start method of UVM?

I am trying to modify the existing code using the start() method in UVM. Basic code is below: ...
Carter's user avatar
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1 answer
67 views

Why does this Verilog testbench not undergo a race condition?

This is the testbench in question: ...
Killjoy's user avatar
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1 vote
1 answer
52 views

How do I figure out if my Verilog code output was generated out of race condition?

Apart from physical observation, is there a way to know if my code will undergo a race condition? For example, the following code has a race condition because both ...
Killjoy's user avatar
  • 131
1 vote
1 answer
108 views

Why is my testbench not driving any output?

In my testbench, I have connected the net z to the output of the seq_det module: ...
Killjoy's user avatar
  • 131
0 votes
3 answers
129 views

Determine which clock of a compound sensitivity list triggered always block

I am trying to implement a non-synthesizable dual-clock FIFO in Verilog (solely for testbench purposes). Since the FIFO has to operate correctly even when both clocks toggle precisely at the same ...
firegurafiku's user avatar
2 votes
1 answer
2k views

How do I create a 2D array in Verilog?

I want to use a 2D array in a Verilog testbench. I tried it this way: ...
Killjoy's user avatar
  • 131
1 vote
3 answers
497 views

Problem overridding parametrized UVM objects

In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
أحمد المحمودي's user avatar
2 votes
1 answer
110 views

Architecture for a virtual 3-phase motor

I would like to construct an electronic virtual 3-phase motor for testing VSD/servo drive systems in the workshop, where the actual motor is not available for testing (e.g. because it is on a running ...
Cliff Pennalligen's user avatar
1 vote
1 answer
465 views

Bad default binding, component port not on entity

I am trying to write a testbench for a basic component, but I am getting an error saying: bad default binding for component instance (component port not on entity) I have tried recompiling multiple ...
Baddioes's user avatar
  • 113
-1 votes
1 answer
421 views

Add multiple test cases in Verilog test bench

I am working with a Verilog test bench which needs multiple test cases to be added to it. How can I add multiple testcase files (approximate 8 test cases) to the test bench (by using package, import, ...
saurabh kumar's user avatar
1 vote
1 answer
348 views

AND gate in Verilog high-Z output

I implemented an AND gate with Verilog, but the waveform keeps showing high-Z on the output (t1 and t2 are OK, but the others ...
Lilda's user avatar
  • 11
1 vote
2 answers
108 views

How to give an input stimulus to the DUT in a testbench when we have a 10-bit input?

How do you get around this problem? I am spending a lot of time in giving a 10-bit input all the way from 1111111111 to 0000000000. How do I effectively write loops in my testbench when I am giving an ...
EngineeringStudent's user avatar
1 vote
1 answer
47 views

How to sample the read data from blocking logic safely by using the interface of SystemVerilog?

I'm trying to read data from combinational logic. module my_reg(; ... output reg [31:0] rdata; ) .... always @(data) rdata = 32'h18; and this dut's value ...
Carter's user avatar
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1 vote
1 answer
945 views

Verification of asynchronous FIFO

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings. The goal is to verify this design by using the Tb components, so no UVM at all. I ...
Giuseppe Trematerra's user avatar
1 vote
1 answer
96 views

Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
Giuseppe Trematerra's user avatar
1 vote
1 answer
971 views

Applying a force in a list of wires using Verilog

I want to apply a force command in a list of wires in Verilog. My netlist looks something like this: ...
Jorge Johanny Sáenz Noval's user avatar
1 vote
1 answer
311 views

Dense Neuron Neural Network in Verilog

I am trying to build NN in system verilog, but I am facing a problem with neuron implementaion, as it only displays 'x'. ...
Ghadeer Ali Jaradat's user avatar
2 votes
1 answer
45 views

Why I am having x as output from ReLU?

I am trying to test ReLU, but it always gives 'x' for the output. ...
Ghadeer Ali Jaradat's user avatar
1 vote
1 answer
734 views

Getting error "A reg is not legal lvalue in this context"

I am trying to create a blockwave in SimVision, but I am struggling with the top-level module. I keep getting the same error and can't figure out the solution. The error is: A reg is not legal lvalue ...
sam verachten's user avatar
1 vote
1 answer
1k views

How to fix the include statement error in Verilog testbench code?

I implemented the four-bit ripple carry adder using Verilog. However, I did not understand why the compiler generated this error Include file FBaddsub.v not found No top level modules, and no -s ...
dev0419's user avatar
  • 35
1 vote
1 answer
747 views

Cannot perform a part select on array error

I'm trying to read a file and use its data as inputs to my design. The file looks like this: ...
temp1445's user avatar
2 votes
1 answer
181 views

My test bench in VHDL is always showing U for all values

I am learning VHDL for a University course. My code: ...
Nour Samir's user avatar
1 vote
1 answer
79 views

Simulation waveform differs from testbench delay specification

I'm running the following Verilog code, and I got the image below as a result. I'm curious why the dout and start signal transitions don't coincide with the delays definitions on the testbench. Does ...
Jorge Johanny Sáenz Noval's user avatar
1 vote
1 answer
196 views

Problem with testing verilog instances using random vectors

I have a set of test vectors saved in a csv file and formatted as follows: 0010,1000,1010 1110,0101,0001 1001,0001,0000 These are randomly generated and can be of ...
engineer1155's user avatar
1 vote
1 answer
299 views

Parameter binding error in Icarus Verilog

I am trying to design a shift register that can have both serial and parallel outputs. My implementation is posted below: ...
temp1445's user avatar
1 vote
1 answer
2k views

Problem with reading a .csv file into a Verilog module

I was trying to read a .csv file and use its contents. The csv is formatted as: 0001,1010,1110 0101,1100,1001 My code is: ...
engineer1155's user avatar
1 vote
1 answer
543 views

SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
blackblade's user avatar
1 vote
1 answer
1k views

SystemVerilog ring oscillator simulation with different delays

I am currently encountering issues with my ring oscillator simulation in SystemVerilog, which I cannot explain. Toolchain: ...
starvin_m4rvin's user avatar
1 vote
1 answer
262 views

SystemVerilog - clk not toggling in verification

I'm testing an AES encryption machine that's written in Verilog. I know that the DUT is perfect because I created a Verilog testbench. When I simulate in VCS, the clk stays at 0 the whole time and the ...
Kirsten Olsen's user avatar
0 votes
1 answer
2k views

Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
gyuunyuu's user avatar
  • 2,103
1 vote
1 answer
209 views

MAX134 and MAX3001E Troubleshooting

This is going to be a long question because I plan to include a lot of context that I feel is important to grasp the full scope of my issue. I am currently a senior year university student hard at ...
Jacob Sillman's user avatar
0 votes
1 answer
158 views

Test/programming rig with spring-loaded probes/connectors

I have ESP32-CAM module with two rows of 0.1" male pins. The pins are 0.22" high. Here is a picture: I would like to trim them, so they are too short to mate with the corresponding female ...
Paul Jurczak's user avatar