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Electrical Engineering

Questions tagged [testbench]

The tag has no usage guidance.

35 questions
Info Newest Frequent Votes Active Unanswered
1
vote
0answers
71 views

VHDL - rand*real(2**32-1) : can this cause an overflow issue?

I'm studying VHDL implementations of multipliers: I found this one and i'm trying to modify it. Default word size is 8 bit and the design is working (both simulation and synthesis) for any size up to ...
0
votes
1answer
42 views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...
2
votes
2answers
100 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
0
votes
1answer
47 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
votes
1answer
425 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
0
votes
0answers
54 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
0
votes
0answers
88 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
-1
votes
1answer
177 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...
0
votes
1answer
37 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...
-1
votes
1answer
409 views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
0
votes
1answer
66 views

Electrical gremlins under high Amp draws

I'm new here so I hope all goes well! I have used an ATX PSU to create a power bench tester for testing automotive headlights. HID in particular which draw around 8-10amps on startup. I have noticed ...
0
votes
1answer
456 views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
votes
1answer
44 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
-1
votes
1answer
384 views

getting outputs in simulation as all high impedance. topic: restoring algorithm for binary division

I am getting outputs of my hardware as all high impedance (ZZZZZ). i tried synthesizing the code and got these warnings. I think there might be a problem in the test bench i am trying to run. ...
0
votes
1answer
305 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...
0
votes
0answers
94 views

Adding of frequency divider causes no output VHDL

I'm trying to get the output from this code. The output is not showing after adding the frequency divider. Before the frequency divider, the code worked well and display the output. This is my code <...
0
votes
0answers
115 views

Multiple VHDL testbench for Single entity

I have VHDL design of Clock generator entity which require 8 input parameters and as per parameters generates single clock output. I have tested using single VHDL testbench and simulated in Modelsim. ...
-1
votes
1answer
267 views

Error: illegal Verilog output port specification

I am having problems with my verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times but I cannot ...
1
vote
1answer
142 views

VHDL Algorithm state machine output

...
1
vote
4answers
373 views

Usage of “initial” in Verilog module description

I'm writting a code and I have 2 dumb questions: 1- Is it a bad practice to use "initial" in the module description? I'm asking this because I have a frequency divider with 2 signals (clk_in and ...
-1
votes
1answer
210 views

Output internal reg to a .txt in Verilog

I would like to write an internal reg to a txt file. I have tried something like: ...
3
votes
1answer
123 views

What options exist to verify Avalon-MM slave component?

I am writing an Avalon-MM slave. It shall connect to Nios II as master device. What options exist to write testbench for it? I must be sure that an Avalon-MM master can correctly read/write it. I ...
0
votes
1answer
286 views

problem with verilog testbench

I have problem with clock signal in Verilog test bench. I've tried almost every possible ways to create clock, but in the waveform it's U meaning "Unknown". Here is my code for clock (...
11
votes
3answers
1k views

How do I protect myself when testing a PCB that involves an AC line?

I have to test prototype PCBs that convert household AC into several DC voltage levels. I concern about my safety when working with AC and would like to know how to properly setup a testbench that, ...
0
votes
2answers
254 views

Load image into VHDL testbench

Is there a standard way to load an image into VHDL testbench so image processing logic output can be tested? Obviously there will be an output from the testbench, also an image that must be possible ...
0
votes
1answer
92 views

designing image debayer block, how should the testbench be written

A debayer block inputs image from a CCD Bayer filter and then estimates the missing color information for each pixel. The data comes from a camera. How should one go about writing a testbench for ...
-1
votes
1answer
269 views

Help needed with verilog testbench

could anyone explain, why the output signal in my verilog testbench isn't changing? I'm trying to build a module that does tasks on both posedge and negedge. For testing purposes, I've built a ...
0
votes
1answer
373 views

Verilog counter does not work!

I've written this code for a counter but I don't know why it doesn't work. Actually the output remains at zero and when I change load to 0, output changes to unknown. Would you please help me to ...
0
votes
2answers
128 views

Designing a testbench for a multi-cycle circuit?

Let's say I have a circuit that performs a function which takes 100 clock cycles to complete. My testbench feeds inputs into the circuit and then checks whether the output is correct. I'm unsure how ...
0
votes
2answers
2k views

VHDL: Using internal signals in testbench

I'm trying to use one of my design's internal signals in my testbench. I already know how I would do it in Verilog: ...
3
votes
1answer
211 views

Simulating a thermopile on the bench — is this a reasonable/reasonably accurate way to do it?

Primer Most people know about 24V HVAC control systems, as that's what's commonly found on furnaces, heat pumps, central air conditioners, and other such systems. If you have electric unit or ...
0
votes
1answer
284 views

How to model devices external to FPGA in a testbench?

FPGA could connect to lot of devices like memory devices (SRAM, SDRAM, DDR RAMs), data converters and various other complex ICs. Is it a normal practice to model them in a testbench to make ...
4
votes
2answers
2k views

Temporary PCB connections for testing

I want to be able to perform tests on assembled PCBs with a custom tool. the test would take seconds, and would be done manually by connecting a cable between the tool and PCB. My question is what ...
0
votes
1answer
82 views

I need to derive a lower frequency clock from the main clock and sample it in verilog

I have been successful in deriving the clock, but am unable to sample and check the results in the test bench. Attaching the code and the written test bench. Need to find a way to do away with the ...
5
votes
3answers
771 views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...