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Questions tagged [testbench]

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2answers
48 views

How to efficiently mux many signals to/from a climate chamber?

I am building a setup to measure various parameters across a temperature range from -55°C to +125°C. The devices under test will be placed in a climate chamber. There are around 10 signals from each ...
1
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0answers
42 views

Using an internal signal in a testbench

I am using HDL Designer and have a pretty large design I need to test. I have created a test bench by using HDL Designer itself and did not do it standalone. Like the title states, I want to know how ...
0
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1answer
44 views

Two questions about testing with HDL designer

I hope it's okay to ask about specific programs here. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through ...
0
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1answer
36 views

Verilog Testbench - wait for specific number of clock cycle edges

In my testbench, I want to wait for two events in sequence: one after 60000 clock cycles and next after additional 5000 clock cycles I know I can wait for clock edges using statement @(posedge clk), ...
0
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2answers
70 views

Ultracapacitor initial voltage drop during discharging

I've been building a test stand for ultracapacitors, with very simple schematic looking like this: simulate this circuit – Schematic created using CircuitLab The resistor on the bottom is to ...
7
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3answers
961 views

VHDL: What is correct way to model open collector output for FPGA?

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though. How should open collector output be defined in a VHDL for an FPGA? How should open collector ...
1
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0answers
101 views

VHDL - rand*real(2**32-1) : can this cause an overflow issue?

I'm studying VHDL implementations of multipliers: I found this one and i'm trying to modify it. Default word size is 8 bit and the design is working (both simulation and synthesis) for any size up to ...
0
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1answer
127 views

Variable frequency for sine wave in Verilog [duplicate]

I am trying to implement 4 different frequencies at which sine wave is going to be simulated in testbench. I am using a counter to do so. However, it can not toggle clk_out in simulation window. Not ...
2
votes
2answers
123 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
0
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1answer
110 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
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1answer
751 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
0
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0answers
58 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
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0answers
121 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
-1
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1answer
318 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...
0
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1answer
40 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...
-1
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1answer
708 views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
0
votes
1answer
68 views

Electrical gremlins under high Amp draws

I'm new here so I hope all goes well! I have used an ATX PSU to create a power bench tester for testing automotive headlights. HID in particular which draw around 8-10amps on startup. I have noticed ...
0
votes
1answer
664 views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
0
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1answer
54 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
-1
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1answer
451 views

getting outputs in simulation as all high impedance. topic: restoring algorithm for binary division

I am getting outputs of my hardware as all high impedance (ZZZZZ). i tried synthesizing the code and got these warnings. I think there might be a problem in the test bench i am trying to run. ...
0
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1answer
446 views

This model of a D-Flip flop with Enable not working as expected

This is a Verilog model of an array of D flip-flops with enable line along with a test bench used in ModelSim Altera: ...
0
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0answers
97 views

Adding of frequency divider causes no output VHDL

I'm trying to get the output from this code. The output is not showing after adding the frequency divider. Before the frequency divider, the code worked well and display the output. This is my code <...
-1
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1answer
330 views

Error: illegal Verilog output port specification

I am having problems with my verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times but I cannot ...
1
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1answer
153 views

VHDL Algorithm state machine output

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1
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4answers
517 views

Usage of “initial” in Verilog module description

I'm writting a code and I have 2 dumb questions: 1- Is it a bad practice to use "initial" in the module description? I'm asking this because I have a frequency divider with 2 signals (clk_in and ...
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1answer
254 views

Output internal reg to a .txt in Verilog

I would like to write an internal reg to a txt file. I have tried something like: ...
2
votes
1answer
203 views

What options exist to verify Avalon-MM slave component?

I am writing an Avalon-MM slave. It shall connect to Nios II as master device. What options exist to write testbench for it? I must be sure that an Avalon-MM master can correctly read/write it. I ...
0
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1answer
318 views

problem with verilog testbench

I have problem with clock signal in Verilog test bench. I've tried almost every possible ways to create clock, but in the waveform it's U meaning "Unknown". Here is my code for clock (...
11
votes
3answers
1k views

How do I protect myself when testing a PCB that involves an AC line?

I have to test prototype PCBs that convert household AC into several DC voltage levels. I concern about my safety when working with AC and would like to know how to properly setup a testbench that, ...
0
votes
2answers
287 views

Load image into VHDL testbench

Is there a standard way to load an image into VHDL testbench so image processing logic output can be tested? Obviously there will be an output from the testbench, also an image that must be possible ...
0
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1answer
105 views

designing image debayer block, how should the testbench be written

A debayer block inputs image from a CCD Bayer filter and then estimates the missing color information for each pixel. The data comes from a camera. How should one go about writing a testbench for ...
-1
votes
1answer
315 views

Help needed with verilog testbench

could anyone explain, why the output signal in my verilog testbench isn't changing? I'm trying to build a module that does tasks on both posedge and negedge. For testing purposes, I've built a ...
0
votes
1answer
413 views

Verilog counter does not work!

I've written this code for a counter but I don't know why it doesn't work. Actually the output remains at zero and when I change load to 0, output changes to unknown. Would you please help me to ...
0
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2answers
134 views

Designing a testbench for a multi-cycle circuit?

Let's say I have a circuit that performs a function which takes 100 clock cycles to complete. My testbench feeds inputs into the circuit and then checks whether the output is correct. I'm unsure how ...
0
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2answers
3k views

VHDL: Using internal signals in testbench

I'm trying to use one of my design's internal signals in my testbench. I already know how I would do it in Verilog: ...
3
votes
1answer
240 views

Simulating a thermopile on the bench — is this a reasonable/reasonably accurate way to do it?

Primer Most people know about 24V HVAC control systems, as that's what's commonly found on furnaces, heat pumps, central air conditioners, and other such systems. If you have electric unit or ...
0
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1answer
309 views

How to model devices external to FPGA in a testbench?

FPGA could connect to lot of devices like memory devices (SRAM, SDRAM, DDR RAMs), data converters and various other complex ICs. Is it a normal practice to model them in a testbench to make ...
3
votes
2answers
2k views

Temporary PCB connections for testing

I want to be able to perform tests on assembled PCBs with a custom tool. the test would take seconds, and would be done manually by connecting a cable between the tool and PCB. My question is what ...
0
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1answer
96 views

I need to derive a lower frequency clock from the main clock and sample it in verilog

I have been successful in deriving the clock, but am unable to sample and check the results in the test bench. Attaching the code and the written test bench. Need to find a way to do away with the ...
5
votes
3answers
882 views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...