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Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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1answer
45 views

How to use/create a real time clock to use with specialized? [closed]

I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will ...
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1answer
76 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
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36 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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1answer
64 views

What's the difference between a LM3302N, TLC373CP, and LT1101CN8?

So I’ve got an LM3302N (IC COMPARATOR QUAD DIFF 14-DIP), LT1011CN8 (IC VOLTAGE COMPARATOR 5-V 8-DIP), and a TLC373CP (IC DUAL DIFF COMP 8-DIP) and I want to build a circuit inspired of the “1 minute ...
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1answer
40 views

Transistor activation / deactivation voltage in

The capacitor was allowed to discharge completely when the transistor was activated with the 3.4 V. The capacitor is allowed to charge again when the conduction from the 5 V line through the ...
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3answers
191 views

When using PWM, what is the purpose of having two complimentary square waves on the same channel?

I'd like to use the PWM I/O on the SAMA5D2 Series Microprocessor (Microchip).What I'm confused about is why each PWM channel has a high and low output pin. The datasheet specifies Each channel ...
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1answer
47 views

Verilog: Posedge sensitivity vs. If statement in Always block

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these ...
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1answer
80 views

Do front and back porches for digtal video really matter?

I am developing an LCD controller, and some of the code for my (third-party) timing generator includes horizontal and vertical front/back porch and vsync/hsync pulse time information for a different ...
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1answer
64 views

How to understand these 8086 bus cycle timing diagrams

Please see the two diagrams below. In the first diagram, each state (T1, T2, ...) seems to begin with the clock low. In the second diagram - with the clock high. If we look at the DR/R' signal - in ...
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1answer
53 views

Op-Amp settling time in bits

I was reading through this and was a bit confused. What do they mean by "took forever to settle to 10-bits (0.1%)"? How is 10-bits = 0.1%
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1answer
41 views

Any side effects of Initialisation and de-initialisation of STM32F0 MCU I2C pin frequently? [closed]

I have one port on my MCU and want to re-define its functionality. Is it possible that something wrong/strange happens if I do it in my main() function? I regularly ...
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1answer
51 views

Mapping two buttons press as a 3rd button

I got a cheap controller with only 5 buttons. I thought about soldering a few more in parallel so that pressing any of the additional buttons would trigger some other two buttons simultaneously. Then ...
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1answer
117 views

How can I delay a digital signal

I am generating a video signal using an AD724 and a microcontroller, which is genlocked to another video signal from a camera, and am using an SN74lVC2G53 analog switch to switch between signals. I'm ...
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2answers
43 views

Clock Generation from Oscillator

Is there specific standard ways to generate clocks from oscillators? Referring to generating a square-wave clock from a sinusoidal oscillator output. I can think of a few circuits involving diodes as ...
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0answers
162 views

Interfacing OV7670 camera with STM32F4 (no FIFO)

I have to interface my STM32F401RE with an OV7670 camera module without external AL422. I followed some of the many tutorials for Arduino, and I was able to capture images using Arduino UNO. ...
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1answer
60 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...
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0answers
73 views

What are the Bluetooth (low energy) scan settings of smartphones

My challenge: I'm trying to find out the best timings for a complex bluetooth low energy (BLE) system, where a central station shall be able to connect to smartphones (=scanner) as well as to coin-...
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1answer
69 views

Time taken by power supply to reach output voltage

My question is regarding programmable power supplies. If I send a SCPI command to the power supply using USB/RS-232 or some other serial communication, how do i know the time taken by the power supply ...
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2answers
54 views

Should a D Flip Flop store its input on clock rise?

I've seen conflicting descriptions and conflicting implementations of D Flip Flops, when it comes to how the Flip Flop behaves when its input value changes at the same time the clock rises. ...
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1answer
54 views

Timing constraints with real clocks

I am new with FPGA and timing constraints, so I apologize if the question will sound stupid. I try to understand timing constraints usage with FPGA. I have found the following description (in https://...
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3answers
140 views

How can calculate the turn-off time of an LDO?

This is the datasheet of TPS7A8101 LDO I am analyzing. In the datasheet, start-up time of the LDO is given as 80 ms for given conditions. My question is, how can I calculate the turn-off time of the ...
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3answers
2k views

Why am I Seeing A Weird “Notch” on the Data Line For Some Logical 1s?

I'm attempting to build a Z80 homebrew computer for some retrocomputing fun and to teach myself the basis of electronic design. For proof-of-concept, I've already assembled a basic system on ...
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1answer
48 views

PIC 12F675 with wrong timing

I have designed an assembler program for PIC 12F675, but it gives wrong timing. Datasheet says that internal oscillator is 4 MHz, and its instruction cycle is 4 clocks. Thus single instruction ...
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1answer
114 views

Which input of NAND is preferred and why? [duplicate]

Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the ...
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0answers
47 views

Register timing violation due to output enable operation

I have relatively complex device filling almost 100% after compilation. Fitter has to perform relatively hard task to route the signals. Everything works fine, except one state machine. The frequency ...
2
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1answer
109 views

How do I interpret the setup/hold time on this RMII interface?

I'm coding the FPGA (MAC) side of an RMII interface between an Altera FPGA and LAN8720 device. Page 72 of the datsheet (pdf) shows the relevant timing diagram for this interface. The input setup/hold ...
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2answers
134 views

FPGA Max PWM Frequency

Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps". Being new in FPGA, I quite could not quite figure out how to extract this ...
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1answer
119 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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1answer
61 views

Timing two parallel lines on FPGA [Beginner]

So let's suppose I want to do certain action based on certain signal. I have signal "nx"; if it's 1, I want to "NOT" an X input(16bit) and if it isn't, I want the X unchanged. My idea was to do both ...
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1answer
82 views

Use Cellphone Vibrating motor in Mouse; on for 3sec off for 3 minutes

I have electronic maintenance experience but it dates to 1985 (last use). I can still solder well but I have forgotten all the electronic theory I once new except for VERY basic stuff. So assume I'm ...
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2answers
47 views

Comparison of 1G123 to 4538

I am designing the edge detection circuit with predefined output pulse duration. Pulse width will be 18.33 ms, supply power is 5V. Error tolerable is +-1 ms. There're a number of designs already ...
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2answers
84 views

Hold-time Violation and timing diagrams [duplicate]

I was wondering what the output of capturing flop looks like, if there is a hold time violation from capture flop. Can anyone explain with a timing diagram?
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0answers
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Can I generate following voltage waveform with single PWM FET?

I am designing power supply which must output following voltages at a maximum of 1.5 A stepped down from a 24 V DC supply. 24 V 13-15 V 0-5 V Waveform for one of the inputs requires following ...
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1answer
71 views

Power-down sequencing with a “hard” power switch (stepper driver)

I'm designing a stepper motor controller and would like to have some advice on sequencing the shutdown process with a "hard" power switch. The Toshiba TB6560 driver that I'm using requires a specific ...
2
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2answers
510 views

How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my ...
2
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1answer
95 views

Order of write and read in Microprocessor interfaced with ADC

An ADC is interfaced with a microprocessor as shown in the figure. All signals have been indicated with typical notations. Acquisition of one new sample of the analog input signal by the ...
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1answer
125 views

Timing capacitor and resistors -Reg

I have this IC - Advance regulating PWM I would like to understand how does the timing resistor and capacitor section works. Sorry for the beginner question but I am unable to understand this section....
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2answers
196 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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1answer
59 views

Rising edge duration of a low to high pulse

In a device I am using, I see the following in the description... "At start-up, the module requires an ON_OFF pulse sent from the host. A second pulse sent from the host will re-enter hibernate mode. ...
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2answers
138 views

GPSDO in firmware?

There are numerous designs online for hardware GPSDO (GPS-disciplined Oscillators). I'm failing to find any firmware-only implementations. I wonder if my Google foo is weak or if these are impractical ...
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1answer
71 views

Question about SR latch timing

I have a question about how SR latches work: To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
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2answers
64 views

Difference between low signal and no signal for a SR latch?

I am struggling to understand how the SR latch works. When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
0
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1answer
160 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
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1answer
240 views

How to turn off 555 Timer for a period of time after Vout signal passes through

I have a single-shot 555 Timer. After triggering, output goes high for a period of time. What I would like to do now: After Vout goes high and then low again, I want to disable the 555 timer for a ...
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0answers
123 views

How to measure SD card data timing vs. clock

I'm doing EVT testing of our product and I want to measure the SD card data vs. clock timing to make sure we're inside the specs. We're using LS1043A that boots Linux (via U-Boot) from an SD card ...
2
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1answer
148 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
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2answers
568 views

Questions about DMX512 protocol/STM

I want to make a DMX512 transmitter with a STM32F103 using HAL, CubeMX. I found some documentation like here about the protocol: Lighting-Control-using-DMX512-protocol-on-STM32. Sadly it does not ...
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2answers
86 views

Where to apply manual delay in character LCD

I went to http://www.elm-chan.org/docs/lcd/hd44780_e.html in an attempt to find out how to make an LCD module work with the shortest timings. While the site does help with the initialization of the ...
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1answer
321 views

SDRAM: Why CAS latency is configurable

I've seen a couple of very similar questions but the answers don't answer my question: DDR2 CAS Latency - is it fixed to clock-cycles or time? What limits the lower bound of DRAM CAS latency In my ...
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2answers
68 views

time counting at -50°C

I'm designing a small slow control system with ATMEGA2560. This board needs to measure temperature, voltage(0~4V), magnetic field using sensors, and monitor the digital status(High or Low) of some ...