Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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Repair advice for an LG 49UH620V with flickering picture (repost) [closed]

After changing channel, the picture on my LG 49UH620V television started doing this flicker. I tried reseting the software to factory settings, then tried leaving it unplugged over night, and still no ...
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2 answers
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Synthesis of Blocking Statements in Verilog - time required for circuit to complete

This question is purely about synthesized verliog, not simulated. I have read that blocking assignments are executed in order, but also that blocking assignments assign values to the RHS immediately. ...
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14 votes
3 answers
542 views

Why specify a maximum pulse width for reset pin?

A colleague and I are working with the Analog Devices AD74413R ADC for 4-20 mA current loop communications. On pages 15 and 16 of the datasheet, timing characteristics are presented. We encountered an ...
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Trouble understanding length matching requirements

I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY. My ...
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1 vote
1 answer
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How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there ...
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Why does metastability occur if data changes during setup and hold time?

I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
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ADC sampling and serial communication

Probably a rookie question and I'm overthinking it. If I have an 8 bit ADC on a microcontroller sampling at 20 MHz, and the ADC operates at a 132 MHz clock, the voltage isn't communicated every period ...
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3 answers
135 views

Driving GPIO outputs with FPGA: How to guarantee outputs of pins are set at same time

I was recently asked a question by an interview. We were discussing a hypothetical device that needed to drive 8 GPIO outputs of the FPGA. I was asked how to reduce the influence of propagation delay ...
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Using a level triggered latch as a negative edge trigger for negative logic

I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
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1 vote
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Reading timing diagram correctly?

I have the following timing diagram of a SPI communication. Am I calculating total time T for receiving 24 bits correctly? Diagram:
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DS3231SN RTC -- timing between 1Hz SQW and clock seconds?

I don't think this is addressed in the DS3231SN datasheet but I may be missing something. When the SQW output is programmed to output a 1Hz signal, is there a known / fixed phase relationship between ...
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How can the RMW instructions on PIC14 take a single cycle?

According to the PIC16F886 datasheet (pdf warning), an instruction like bcf takes a single cycle. It's also described as a read-modify-write instruction, i.e., it ...
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VHDL timing confusion and possible metastability risk?

Timing, especially in sequential logic, confuses me a lot. I devised an example and drew a timing diagram and I would like to ask some question regarding it; all of them are about the same issue. Here ...
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How to increase setup time of a reg wired to an EBR FIFO? (Lattice FPGA)

I'm using the built-in EBR FIFO of a Lattice FPGA: ...
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3 answers
149 views

In which clock edge does the I2C slave write?

I'm trying to implement an I2C master - slave example in an FPGA (Verilog). As the I2C protocol specifies, the master must make sure that it writes the next bit enough time before the clock signal ...
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When buying parts with serial interfaces is it useful to check timing requirements?

When buying parts with serial interfaces is it useful to check timing requirements? I'm especially curious about something like I2C; is it generally enough to see that a component is capable of ...
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VHDL: input signal timing variations

VHDL newbie here; I am trying to solve a problem with an existing CPLD project (based on a Xilinx XC95144XL). The project in question is an plug-in cartridge for a vintage home computer, adding ...
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Hold time constraint equation

I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint Hold time ...
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1 vote
2 answers
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Delaying a square wave by 1 us

This is a continuation of my previous question - Delaying a signal using LTC69942 - Some pulses missing at the output. I have a square wave with below specifications: I need to delay it by 1 us. I am ...
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Delaying a signal using LTC69942 - Some pulses missing at the output

I want to delay a square wave by 1us to 30us. I am using a LTC6994-2 for this purpose. Currently, I provided a delay of 1us. What I can see is some pulses of the input are missing at the output. ...
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3 votes
1 answer
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Wrong data clocked in when using direct daisy chains of 594/595 shift-registers

I was a bit surprised to find this question and its answer. simulate this circuit – Schematic created using CircuitLab When daisy chaining several HC595 or HC594 shift registers, with shared ...
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Standart Retiming circuit with two D type Flip Flops

I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ

I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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2 votes
1 answer
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How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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1 vote
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Panasonic MN39470PT CCD Sensor Timing

The datasheet for the MN39470PT CCD sensor seems to be missing some details regarding the timing needed to drive the sensor. For this reason I'm very confused on how I'd drive the sensor particularly ...
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1 answer
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Max clock frequency when cascading several 74HC for Address Decoding

I'm building a 6502 (WDC 65C02S) computer, for now on a breadboard (maybe later will I hopefully learn and move to a PCB). In my Address Decoding Logic I'm using several NAND and 4-input NAND gates (...
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2 votes
1 answer
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DDR3 DQS "preamble"

I'm building a small testbench for a DDR3 memory controller and would like to verify that my unterstanding of DQS and DQ sampling points is correct. The line state before the transmission is undefined ...
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2 answers
64 views

Syncing microcontroller timer interrupts with slower external clock

I have been working on a data logger project that requires very accurate timestamps and intervals for reading data. I have been able to generate a timestamp by syncing a timer with a pulse per second ...
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11 votes
10 answers
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Is there a microcontroller with zero interrupt jitter?

I know that interrupt latency depends on what the CPU is doing when the interrupt takes place (arm interrupt latency guide). This effect is called interrupt jitter. For my application I need an MCU ...
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0 votes
3 answers
164 views

The Mean Time Between Failure (MTBF) Quantity

It is the amount of time a system is operational i.e. MTTF plus the amount of time to repair it MTTR. I am considering repairable systems only. I know that it helps in scheduling maintenance, safety ...
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subcircuits powering (predetermined time delay, ~8 seconds)

In order to control inrush current, and also to make sure some subcircuits and modules are OK on startup, I need a predetermined time delay between delivering power to these subcircuits. (Automatic ...
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2 votes
1 answer
90 views

Different output delays for internal to output and input to output path

I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY. The timing constraints from internal ...
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3 votes
1 answer
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Issues when outputting to every single pin on an FPGA

I am using a Lattice ECP5U FPGA (lfe5u-25f-6BG256). I am using Diamond Lattice software with the included Synplify synthesizer. I am writing a code to toggle every single pin (or most of them) on an ...
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0 answers
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Trying to Understand How Honda Ignition Timing Works

So, I know this isn't an automotive group (per say), but I think that is exactly what I need. In the most simple terms, I've been dissecting my 2001 Honda Accord (3.0 V6 for what it's worth) to ...
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3 votes
2 answers
451 views

Cascaded flip-flops and shift register timing

In the D-flip flop at the edge triggering of the clock, \$Q(t+1)=D\$. In the figure below, shift-register using cascaded flip flops, why don't we assume that at clock edge triggering \$Q_1(t+1)=D_1\$ ...
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1 answer
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What is the setup/hold time of the RMII receive interface of the TI DP83630 phy chip?

I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the ...
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4 votes
2 answers
354 views

ADC Chip Timing Question

When is the best time to read the bit out of a serial data output 12-bit ADC chip. The chip is a AD7476A, and here is the datasheet AD7674A Datasheet. Going by the timing diagram, when is the best ...
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3 votes
1 answer
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SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
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1 answer
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Modbus acquisition timings

Part 1 What is the standard timing method for bits acquisition for a receiver using Modbus RTU? For example, for UART: "Communicating UARTs have no shared timing system apart from the ...
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1 vote
1 answer
380 views

FPGA Timing Constraints

I am fairly new to FPGA design and I am working on a project where the FPGA is the SPI Slave. Are there supposed to be constraints on the Master Clock input signal/ MOSI / Chip select? What is the ...
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0 votes
3 answers
117 views

Ways to reduce Vgs range of Logic Level MOSFET

I try to control two MOSFETs from one microcontroller pin, where one MOSFET shall turn on 400 ms after the first one. The second MOSFET is switching on a relay coil. My idea was just to use a RC ...
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Timing when clocking MCU off of A/D

I'd like to try interfacing a fast (80 MHz) ADC with a microcontroller system. The ADC (ADC12DL080) connects to a buffer flip flop (SN74LVTH162374) which then drives the MCU data pins about 6 cm away ...
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If an IC has an external resistor for timing, can that be replaced with an analog voltage out from another IC?

Specifically, I want to control the sample rate of an ISP1820 with an analog out from an Arduino. I know I could drop-in a digital pot but I don't have one and that seems like needless complexity if I ...
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Segments not totally off when multiplexing 7 segments display with CD4051BE

I'm trying to make a display with several 7 segment displays so I decided to use multiplexing to make it work. I use CD4051BE to do that. The circuit is as follow: Circuit of the multiplexing The ...
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SPI Timing of WIZ850io

I can't understand the SPI timing diagram, I had search through various websites for timing diagram but I have no idea how to interpret this timing diagram of WIZ850io. I am currently trying to form a ...
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3 votes
2 answers
182 views

How to prevent short circuit between output pins

I am trying to hack some signals coming from an old computer going to a Floppy drive using an ATtiny1614 microcontroller. Normally the computer has full control of the signal lines but at some window ...
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5 votes
1 answer
330 views

Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...
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1 vote
0 answers
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How to create timing waveforms for an H-Bridge Inverter

This is my first question on Stack Exchange. I am in the process of simulating a wireless charger coil setup on LTSpice. I have tried a Royer/Baxandall oscillator to provide the necessary sinusoidal ...
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1 vote
0 answers
94 views

GPS PPS Signal Duty Cycle? [duplicate]

just like the title says, I'm trying to figure out the duty cycle of a GPS's Pulse Per Second Signal. This post and accompanying answers seem to indicate something like a 10% duty cycle: GPS PPS ...
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0 votes
1 answer
95 views

Switching from full to half wave rectification

The Context: Multiple manufacturers of electro-magnetic brakes offer rectifier modules to switch their DC brakes with an AC feed. This can often be tied to the same phases turning the motor, so that ...
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