Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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FPGA DDR timing constraints

I have EMMC master for FPGA. Please tell me how to write constraints on ports in DDR mode? I tried to write constraints but I doubt the correctness Specification: JEDEC Standard No. 84-B51 P.S. Here ...
strontiuman's user avatar
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1 answer
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Optimizing Incandescent Traffic Light Design

I'm currently working on designing an incandescent traffic light system and could use some guidance on extending and optimizing my design. Initially, I've successfully implemented the required ...
Zipho Lunika's user avatar
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2 answers
661 views

STM32 writing to SD card using FATFS sometimes takes longer than normally

I am using nucleo-f401re board for my project and I want to write sensor data to SD card. I am writing data when sensor interrupts occur, and that happens at 408 Hz, so I have around 2 ms to write ...
Dominykas's user avatar
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Would this boot select button design work?

So, I'm back with the need for more advice. This post ties in with my previous post here. I recommend you read the previous post because most of the information that I'll be referring to is found ...
Gigoiy's user avatar
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3 answers
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How to interpret maximum risetime on I²C communication timing specification

I am using a ICM-42605 IMU in conjunction with a GNSS module, which has a blackbox firmware that realizes the communication with the IMU via I²C. I can see signs that the communication works fine, and ...
Yordan Aleksandrov's user avatar
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Are same row pixels exposed simultaneously for rolling shutter sensor in ERS mode?

I know that each pixel row in a rolling shutter sensor running in ERS mode (Electronic Rolling Shutter) are exposed for the same duration but at different points in time. But what about each pixel in ...
mola's user avatar
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Driving Gate from MCU (using 6N136 and TC4431)

This is my first time trying to use this optocoupler (6N136) I'm trying to control a MOSFET gate with the least switching delays (rise and fall timings) possible, while making the MCU isolated from ...
Bikay's user avatar
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1 answer
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FPGA output timing explained

As a hardware designer you have consider the timing constraints of both the input and output device. Input devices specify a setup and hold time reference to the clock (the time in which the data ...
Dukel's user avatar
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Horizontal Blanking Interval (Idling Time) optimization

I have questions regarding the time slot in-between two frames of video stream, i.e. Horizontal Blanking Interval (let's say HBI in the following), seen as Idling Time sometimes. Considering a CMOS ...
AirconBento's user avatar
2 votes
0 answers
113 views

Z80 interfacing, address decoding logic produces noisy signals

I really would like to have suggestions and feedback from someone. It's about digital logic, in detail, the Z80 interfacing. In this design, I used a 74HC30 which is a 8-input NAND Gate. I'm using it ...
ozw1z5rd's user avatar
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Timing parameters of sequential circuit - digital electronic

Problem Determine the timing parameters (\$T_\text{cQ,bb}, T_\text{su,bb}, T_\text{h,bb}\$) for the black box logic circuit seen below: - Attempt \$T_\text{cQ,bb}\$ is the time it takes for the ...
Carl's user avatar
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3 votes
6 answers
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Synchronization of handshake channel with different clock domains

My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø. On page 156 he talks about synchronizing a handshake protocol between a ...
Carl's user avatar
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Struggling with the design for a simple logic circuit [closed]

I'm working on a circuit that would store 4 bits and flash them on an LED. These would be stored on a 4 bit register, and should be outputted when a button is pressed. My goals is to take my 4 outputs ...
BarryTheLad's user avatar
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1 answer
149 views

A 555 timer changes time when you touch it?

I designed a simple 555 astable 50% duty cycle square wave generator, assembled in China on SMT PCB. It works well: Except when you touch it, or even put your fingers near it, the timing changes ...
SRobertJames's user avatar
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Erratic and confusing I2C behavior between ATSAMD21G18 and A89307 through ISO1644 isolator

I'm working on a BLDC driver using Allegro's A89307 controlled by an isolated ATSAMD21G18 via TI's ISO1644 I2C digital isolator. The simplified I2C connection is shown below, I omitted all the bypass ...
Jess S.'s user avatar
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ADC Timing Problems in FPGA design

I am using a Xilinx Kintex UltraScale FPGA (AXKU040 development board) and an ADC board (FL9616 board). I would like to have a design that provides the ADC data as a data stream inside the FPGA. The ...
Saeed Jazaeri's user avatar
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1 answer
172 views

The timing issue with FPGA, after synthesizing this code, the total hold slack is a negative number [closed]

...
dodo_123's user avatar
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How to write I2C protocol timing constraints?

How do you normally write clock timing cons for I2C? Assuming 1 SDA line, 1 SCL line, 1 APB reference CLK called PCLK. Q. What are the relation of PCLK to SCL in this protocol? Does it matter if it is ...
vaibhav sharma's user avatar
3 votes
1 answer
70 views

Best practice to constrain dynamically tuned FPGA->DAC data path

Data is moved from the Zynq 7010 to AD9779A DAC using parallel SDR link at 155.52MHz. This DAC generates DATACLK clock that is used to clock data out of the FPGA (see picture for the relevant FPGA ...
Oleg Skydan's user avatar
0 votes
2 answers
85 views

Why does increasing the period of a signal compensate for clock skew?

My textbook gives the following circuit: simulate this circuit – Schematic created using CircuitLab Where both registers are positive-edge triggered D-Type flip-flops. It describes a how a race ...
BSTKR's user avatar
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1 answer
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How to write clock process triggering hold and reset pulses in VHDL?

I am attempting to write VHDL for generating control signals to operate a switched integrator circuit. I'd like to create a 20us 50% duty cycle hold signal and a 5us reset signal when the hold signal ...
redExcalibur's user avatar
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216 views

ESP32 - Speeding up connection to WiFi AP and REV.3 chip woes

Esp-IDF 5.0, ESP32 Devkit1 Chip REV.3 Even with the official "station" example stripped to the minimum of code (wifi-related only), connecting to the AP with ESP32 takes 2-3 seconds. That is ...
Noideas's user avatar
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1 vote
1 answer
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Measure time between trigger events

I want to measure the arrival time of three seperate digital pulses with respect to a global trigger. The longest arrival time is expected to be <10ms and it would need to be able to determine the ...
Flemingjp's user avatar
3 votes
2 answers
547 views

Maintain accurate timing on 1pps 'heartbeat' signal

I have an application where I need to provide a 1 pulse per second 'heartbeat' signal with a very good accuracy over an extended period of time (1 second between pulse edges ± approx. 200 μs for ...
droseman's user avatar
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0 answers
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Serial communication - previously sent information incorrectly stored in image buffer arrays

https://github.com/StonedEdge/Retro-Lite-CM4-Dock/tree/main Hi everyone, I am trying to read in some image data over serial communications, which is done on the trigger after receiving some characters ...
StonedEdge's user avatar
2 votes
0 answers
80 views

Analog Timing Circuit with DIAC

I am currently trying to come up with an analog timing circuit to use within a solar tracker. I know using a 555 timer would be relatively easy to do here but I wanted to see if I could come up with a ...
pointy's user avatar
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2 answers
388 views

Clock direction in MII and RMII Interface

I know that in the MII interface, the clock is always sent from PHY to MAC irrespective of TX or RX? Can someone explain me on why TX and RX, the PHY should send the clocks? Like for the RX ...
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0 answers
342 views

Circuit for Read/Write RAM Control Signals

I have the following architecture of an 8-bit bus / RAM interface where the bus can read from and write to the SRAM: There are two 74LS245 8-bit bi-directional buffers, with there direction input ...
David777's user avatar
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0 votes
3 answers
968 views

How to determine the horizontal pixel count out of a HSync and VSync signal

I have a project where I want to read the HSync and VSync signal from a VGA cable into an microcontroller and calculate the pixel clock. Calculation: Pixel clock = Horizontal Pixel Count * Vertical ...
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1 answer
71 views

How to measure time between incoming packages on an FPGA?

For measuring the speed of incoming data packages on an FPGA, would you use a clock that is connected to a counter and each time a package is detected, it would store the time? And if there would be a ...
jikki plikki's user avatar
2 votes
1 answer
222 views

Skew in half-bridge dead time generator in LMG5200EVM

The eval board for the GaN half bridge module LMG5200 (datasheet) contains the following circuit to generate dead time from a single PWM input. The half-bridge module itself has good propagation ...
tobalt's user avatar
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2 votes
1 answer
99 views

How to solve for relay specifications?

I'm working with an unknown brand of relay and I need to know its specifications - most important is the minimum On current at approximately 42vDC, other values would be appreciated if possible. Does ...
David Stosser's user avatar
1 vote
0 answers
54 views

Trying to get a 10uS pulse width to fire an SCR using a PIC16F884

I have the circuit built and running but I need to shorten the pulse width of the SCR. I am using a PIC16F884 running at 16MHz. I am using a half wave to control a device. When I use a for next loop, ...
Dorato's user avatar
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0 votes
2 answers
124 views

74HC93 produces a different signal when the frequency is increased

I'm trying to produce a signal using a 74HC93 that pulses high every 8th bit while the "SELECTOR" signal is low. The "SELECTOR" signal is 24 clock cycles. It works fine at 4 MHz, ...
red's user avatar
  • 49
1 vote
1 answer
35 views

Syncronize 2 digital signals

I have 2 digital signals, and I want them to synchronize. the lower frequency yellow signal takes 32 clock cycles. the higher frequency blue signal takes 8 clock cycles. I need the lower frequency ...
yellowsub's user avatar
4 votes
7 answers
3k views

Are there any microcontrollers that do not require an external clock source?

I've seen a microcontroller (don't remember the exact part number at the moment,) that doesn't have XTAL pins. It was an 8-pin MCU - it didn't have any clock input pins on the device. How do those ...
user avatar
2 votes
1 answer
378 views

FPGA-centric timing constraints

I have designed an MMC slave on an FPGA that will interface with many different MMC masters with many different trace lengths, etc. Most of the timing constraint documentation on how to constrain ...
huskerwr38's user avatar
0 votes
0 answers
53 views

Optimal use of a timing pulse

I have an indicator module that uses an ATTiny85 to switch an array of LEDs based on an RS-485 signal delivered by SoftwareSerial and a MAX485 IC. The indicator can be Off, On, or Flashing. All power ...
Jamie's user avatar
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0 votes
1 answer
130 views

Optocoupler + MOSFET PWM amplifier timing issue

I want to drive a 12V, 1.5A valve from a microprocessor and also provide some isolation. The MCU outputs 3.3V logic, and I have this output going into a common source amp & also have a resistor in ...
jonnyd42's user avatar
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2 votes
1 answer
432 views

UART to RS-485 communication between two Arduinos

I'm learning how to use a MAX485 or MAX487 IC to create a half-duplex RS-85 communication between two Arduino s. Each Arduino has an LED that turns ON/OFF by receiving a command from the other Arduino....
a2640's user avatar
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0 votes
0 answers
90 views

SPI interfacing a sensor doesn't seem to work

I'm trying to get a feeling for how the SPI protocol works. I built this cirucit using Proteus simulator. simulate this circuit – Schematic created using CircuitLab And then according to the ...
Ait-Gacem Nabil's user avatar
0 votes
2 answers
263 views

1/60 Hz Counter/Divider

I have a fairly precise 1 Hz square wave that I would like to divide down to 1/60 Hz (1 pulse per minute). I want a one-chip solution and I am not having a lot of luck with this. I do not want a ...
Austin Fox's user avatar
0 votes
2 answers
252 views

Synthesis of Blocking Statements in Verilog - time required for circuit to complete

This question is purely about synthesized verliog, not simulated. I have read that blocking assignments are executed in order, but also that blocking assignments assign values to the RHS immediately. ...
user2704336's user avatar
15 votes
3 answers
701 views

Why specify a maximum pulse width for reset pin?

A colleague and I are working with the Analog Devices AD74413R ADC for 4-20 mA current loop communications. On pages 15 and 16 of the datasheet, timing characteristics are presented. We encountered an ...
JYelton's user avatar
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-1 votes
1 answer
305 views

Trouble understanding length matching requirements

I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY. My ...
mooshoomatt's user avatar
1 vote
1 answer
353 views

How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there ...
Polynomial's user avatar
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0 votes
2 answers
173 views

Why does metastability occur if data changes during setup and hold time?

I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
penguin99's user avatar
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0 votes
1 answer
345 views

ADC sampling and serial communication

Probably a rookie question and I'm overthinking it. If I have an 8 bit ADC on a microcontroller sampling at 20 MHz, and the ADC operates at a 132 MHz clock, the voltage isn't communicated every period ...
bchang32's user avatar
  • 111
0 votes
3 answers
768 views

Driving GPIO outputs with FPGA: How to guarantee outputs of pins are set at same time

I was recently asked a question by an interview. We were discussing a hypothetical device that needed to drive 8 GPIO outputs of the FPGA. I was asked how to reduce the influence of propagation delay ...
Bob John's user avatar
0 votes
1 answer
98 views

Using a level triggered latch as a negative edge trigger for negative logic

I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
user1958698's user avatar

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