Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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22 views

What is the setup/hold time of the RMII receive interface of the TI DP83630 phy chip?

I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the ...
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2answers
324 views

ADC Chip Timing Question

When is the best time to read the bit out of a serial data output 12-bit ADC chip. The chip is a AD7476A, and here is the datasheet AD7674A Datasheet. Going by the timing diagram, when is the best ...
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1answer
88 views

SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
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35 views

Modbus acquisition timings

Part 1 What is the standard timing method for bits acquisition for a receiver using Modbus RTU? For example, for UART: "Communicating UARTs have no shared timing system apart from the ...
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1answer
84 views

FPGA Timing Constraints

I am fairly new to FPGA design and I am working on a project where the FPGA is the SPI Slave. Are there supposed to be constraints on the Master Clock input signal/ MOSI / Chip select? What is the ...
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82 views

Ways to reduce Vgs range of Logic Level MOSFET

I try to control two MOSFETs from one microcontroller pin, where one MOSFET shall turn on 400 ms after the first one. The second MOSFET is switching on a relay coil. My idea was just to use a RC ...
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1answer
75 views

Timing when clocking MCU off of A/D

I'd like to try interfacing a fast (80 MHz) ADC with a microcontroller system. The ADC (ADC12DL080) connects to a buffer flip flop (SN74LVTH162374) which then drives the MCU data pins about 6 cm away ...
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1answer
65 views

If an IC has an external resistor for timing, can that be replaced with an analog voltage out from another IC?

Specifically, I want to control the sample rate of an ISP1820 with an analog out from an Arduino. I know I could drop-in a digital pot but I don't have one and that seems like needless complexity if I ...
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43 views

Timing issue about DSP Parallel I/O

I want to use DSP's parallel I/O to communicate with FPGA synchronously but find an issue with the timing. In this design, DSP writes data to FPGA through its parallel IO. The CLKOUT is generated from ...
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34 views

Segments not totally off when multiplexing 7 segments display with CD4051BE

I'm trying to make a display with several 7 segment displays so I decided to use multiplexing to make it work. I use CD4051BE to do that. The circuit is as follow: Circuit of the multiplexing The ...
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1answer
36 views

SPI Timing of WIZ850io

I can't understand the SPI timing diagram, I had search through various websites for timing diagram but I have no idea how to interpret this timing diagram of WIZ850io. I am currently trying to form a ...
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2answers
97 views

How to prevent short circuit between output pins

I am trying to hack some signals coming from an old computer going to a Floppy drive using an ATtiny1614 microcontroller. Normally the computer has full control of the signal lines but at some window ...
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1answer
200 views

Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each ...
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How to create timing waveforms for an H-Bridge Inverter

This is my first question on Stack Exchange. I am in the process of simulating a wireless charger coil setup on LTSpice. I have tried a Royer/Baxandall oscillator to provide the necessary sinusoidal ...
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0answers
42 views

GPS PPS Signal Duty Cycle? [duplicate]

just like the title says, I'm trying to figure out the duty cycle of a GPS's Pulse Per Second Signal. This post and accompanying answers seem to indicate something like a 10% duty cycle: GPS PPS ...
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1answer
55 views

Switching from full to half wave rectification

The Context: Multiple manufacturers of electro-magnetic brakes offer rectifier modules to switch their DC brakes with an AC feed. This can often be tied to the same phases turning the motor, so that ...
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53 views

FPGA packaging and performance

I would like begin a new custom FPGA design and I am considering buying a dev kit for experimentation. When the design has finished, I intend to design a dedicated PCB board. If I change the packaging ...
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1answer
438 views

What does it mean “positive” or “negative” polarity in VGA's HSynch and Vsynch?

I have been trying to study how VGA signals work and I stumbled upon this this page with all the different VGA timings. What isn't clear to me is what it means by "polarity horizontal sync pulse ...
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22 views

Timer not having output after initial powering

DGM TIMER RELAY BOARD 12V 1S-1HR Time Delay ON or OFF 12V Relay Board with jumper settings and 8 Time Ranges selectable from 0.1s up to 1 hour accessing loads 250VAC 10A or 30VDC 10A I believed this ...
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4answers
1k views

Rigol DS1074 oscilloscope shows very wrong timing

I have an inverted RS232 signal with 5 baud (200 ms per bit) which is sending the byte 0x33. (The first "Low" is the start bit) When I configure my oscilloscope to 200 ms per unit it shows ...
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42 views

Time to Digital Converter using FPGA with Coarse Counter in Verilog

I am currently using Verilog to program an FPGA and create a time-to-digital converter. What I am trying to do is measure the time interval when a square wave is high and then convert this to a binary ...
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44 views

voltage monitor using tps3897 - understanding

Although I have some experience with circuitry it is mainly analog experience. therefore I can't solve the question i have been given in interview. I have been asked what does the next circuit do: ...
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1answer
115 views

FT2232H - FT245 Synchronous FIFO mode read timing

I'm trying to understand the read timing diagram of the FT2232H in FT245 Synchronous FIFO mode so that I can properly configure the state machine of the FPGA attached to it. Here's the datasheet page ...
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1answer
42 views

Microcontroller internal Clock frequency tolerances [duplicate]

I am having this microcontroller - S32K142 64 Pin 5V Core voltage Microcontroller Reference Manual I want to use the FIRC and want to see the frequency tolerance of the FIRC. Can someone help to find ...
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1answer
42 views

Off delay timing function for a relay, using a Arduino [closed]

Heres my following circuit: https://imgur.com/a/qTV8zgR Here's the timing function I want to implement; https://www.google.com/search?q=off+delay&client=opera&hs=bme&sxsrf=...
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Lattice MachXO2 EFB Timer/Counter timing specification missing

Searching through Lattice FPGA-DS-02056 (MachXO2 Family Data Sheet) and TN1205 (Using User Flash Memory and Hardened Control Functions in MachXO2 Devices), I couldn't find a detailed specification of ...
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2answers
70 views

Timing specifications in a communication protocol

I am having this I2C EEPROM Chip from Onsemi - CAT24C In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period. My questions : Not ...
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3answers
84 views

Solar powered mini water pump: how to turn it on/off automatically

I have acquired a mini water pump (5V 1.0A) and several solar panels (each: 5V 200mA). What I try to achieve is to pump water from a container above a vertical hydroponic system and let it flow down ...
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3answers
92 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
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0answers
370 views

Is there a faster alternative to the HT12E / HT12D IC?

I am looking for a quicker alternative to the HT12E encoder IC. This IC lets you encode 8 bits of adresse and 4 bits of data. Once the bits are encoded, it outputs a frame containing all those bits ...
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1answer
191 views

Setting HSYNC and VSYNC registers

I am using the FT801 (datasheet) to drive a Newhaven 4.3" TFT display (datasheet). The TFT datasheet specifies the normal timing parameters (hsync/vsync peroid, front porch, back porch) on page 6. ...
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0answers
40 views

I require a simple circuit to create a 3v output pulse then drop to zero volts then back to 3v every 3 seconds (time adjustablevwould be good)

I am trying to simulate a flow meter, it’s output is 3v every 3 seconds it alternates between 3v and 0 v continuous. I have basic circuit knowledge, and can create simple pcn circuits. I don’t want to ...
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1answer
234 views

Measuring pulse durations with microsecond precision or better

Problem I'll be receiving pulses and want to know the relative times of pulse start/end with microsecond precision (or better). Pulse characteristics: pulse frequency: probably 1Hz to 10Hz pulse ...
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0answers
72 views

Poor low frequency response of CD4060 IC

I have a question that involves a CD4060 ripple counter. My project is to design a counting circuit that turns off a relay after two hours. This can be done simply using an Arduino, but no ...
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2answers
523 views

How to reduce Worst Negative Slack and Total Negative Slack in my design?

I have an I2S transmitter with an AXI-Stream interface. AXIS_I2S ...
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3answers
110 views

How to get signal dependencies from RTL verilog?

How can I find out if a signal B has any combinational dependency on a signal A without manually examining the verilog source code? (Question edited to try and make the reason/background more clear) ...
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1answer
979 views

Where to place hall sensors (BLDC motor)?

I have a BLDC hub motor (out runner type; 3 phase wires) for my electric bike. It currently has 1 set of hall sensors (3 pieces) and I would like to install a second set (3 more) for spare (in case ...
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3answers
57 views

What is the typical delay relative to to the maximum delay?

I have a board with a number of ICs, an FPGA, and some flash and RAM devices. The board is designed based on worst case conditions, as it should be. The critical combinatoric path has a maximum ...
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1answer
50 views

How to use/create a real time clock to use with specialized? [closed]

I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will ...
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1answer
129 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
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1answer
182 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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1answer
129 views

What's the difference between a LM3302N, TLC373CP, and LT1101CN8?

So I’ve got an LM3302N (IC COMPARATOR QUAD DIFF 14-DIP), LT1011CN8 (IC VOLTAGE COMPARATOR 5-V 8-DIP), and a TLC373CP (IC DUAL DIFF COMP 8-DIP) and I want to build a circuit inspired of the “1 minute ...
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1answer
78 views

Transistor activation / deactivation voltage in

The capacitor was allowed to discharge completely when the transistor was activated with the 3.4 V. The capacitor is allowed to charge again when the conduction from the 5 V line through the ...
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3answers
464 views

When using PWM, what is the purpose of having two complimentary square waves on the same channel?

I'd like to use the PWM I/O on the SAMA5D2 Series Microprocessor (Microchip).What I'm confused about is why each PWM channel has a high and low output pin. The datasheet specifies Each channel ...
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1answer
783 views

Verilog: Posedge sensitivity vs. If statement in Always block

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these ...
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1answer
112 views

Do front and back porches for digtal video really matter?

I am developing an LCD controller, and some of the code for my (third-party) timing generator includes horizontal and vertical front/back porch and vsync/hsync pulse time information for a different ...
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1answer
133 views

How to understand these 8086 bus cycle timing diagrams

Please see the two diagrams below. In the first diagram, each state (T1, T2, ...) seems to begin with the clock low. In the second diagram - with the clock high. If we look at the DR/R' signal - in ...
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1answer
78 views

Op-Amp settling time in bits

I was reading through this and was a bit confused. What do they mean by "took forever to settle to 10-bits (0.1%)"? How is 10-bits = 0.1%
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1answer
42 views

Any side effects of Initialisation and de-initialisation of STM32F0 MCU I2C pin frequently? [closed]

I have one port on my MCU and want to re-define its functionality. Is it possible that something wrong/strange happens if I do it in my main() function? I regularly ...
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1answer
68 views

Mapping two buttons press as a 3rd button

I got a cheap controller with only 5 buttons. I thought about soldering a few more in parallel so that pressing any of the additional buttons would trigger some other two buttons simultaneously. Then ...

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