Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

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37 views

FT2232H - FT245 Synchronous FIFO mode read timing

I'm trying to understand the read timing diagram of the FT2232H in FT245 Synchronous FIFO mode so that I can properly configure the state machine of the FPGA attached to it. Here's the datasheet page ...
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25 views

Microcontroller internal Clock frequency tolerances [duplicate]

I am having this microcontroller - S32K142 64 Pin 5V Core voltage Microcontroller Reference Manual I want to use the FIRC and want to see the frequency tolerance of the FIRC. Can someone help to find ...
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1answer
35 views

Off delay timing function for a relay, using a Arduino [closed]

Heres my following circuit: https://imgur.com/a/qTV8zgR Here's the timing function I want to implement; https://www.google.com/search?q=off+delay&client=opera&hs=bme&sxsrf=...
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Lattice MachXO2 EFB Timer/Counter timing specification missing

Searching through Lattice FPGA-DS-02056 (MachXO2 Family Data Sheet) and TN1205 (Using User Flash Memory and Hardened Control Functions in MachXO2 Devices), I couldn't find a detailed specification of ...
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2answers
36 views

Timing specifications in a communication protocol

I am having this I2C EEPROM Chip from Onsemi - CAT24C In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period. My questions : Not ...
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3answers
77 views

Solar powered mini water pump: how to turn it on/off automatically

I have acquired a mini water pump (5V 1.0A) and several solar panels (each: 5V 200mA). What I try to achieve is to pump water from a container above a vertical hydroponic system and let it flow down ...
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3answers
75 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
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109 views

Is there a faster alternative to the HT12E / HT12D IC?

I am looking for a quicker alternative to the HT12E encoder IC. This IC lets you encode 8 bits of adresse and 4 bits of data. Once the bits are encoded, it outputs a frame containing all those bits ...
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1answer
46 views

Setting HSYNC and VSYNC registers

I am using the FT801 (datasheet) to drive a Newhaven 4.3" TFT display (datasheet). The TFT datasheet specifies the normal timing parameters (hsync/vsync peroid, front porch, back porch) on page 6. ...
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40 views

I require a simple circuit to create a 3v output pulse then drop to zero volts then back to 3v every 3 seconds (time adjustablevwould be good)

I am trying to simulate a flow meter, it’s output is 3v every 3 seconds it alternates between 3v and 0 v continuous. I have basic circuit knowledge, and can create simple pcn circuits. I don’t want to ...
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1answer
133 views

Measuring pulse durations with microsecond precision or better

Problem I'll be receiving pulses and want to know the relative times of pulse start/end with microsecond precision (or better). Pulse characteristics: pulse frequency: probably 1Hz to 10Hz pulse ...
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62 views

Poor low frequency response of CD4060 IC

I have a question that involves a CD4060 ripple counter. My project is to design a counting circuit that turns off a relay after two hours. This can be done simply using an Arduino, but no ...
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2answers
70 views

How to reduce Worst Negative Slack and Total Negative Slack in my design?

I have an I2S transmitter with an AXI-Stream interface. AXIS_I2S ...
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3answers
101 views

How to get signal dependencies from RTL verilog?

How can I find out if a signal B has any combinational dependency on a signal A without manually examining the verilog source code? (Question edited to try and make the reason/background more clear) ...
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25 views

understanding NAND ONFI interface and timing

In this question im trying to understand how NAND interface ONFI 1.0 works going to compare (code, datasheets) from ready ASF framework example (microchip) the development board : SAM4E XPlained Pro ...
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1answer
184 views

Where to place hall sensors (BLDC motor)?

I have a BLDC hub motor (out runner type; 3 phase wires) for my electric bike. It currently has 1 set of hall sensors (3 pieces) and I would like to install a second set (3 more) for spare (in case ...
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3answers
54 views

What is the typical delay relative to to the maximum delay?

I have a board with a number of ICs, an FPGA, and some flash and RAM devices. The board is designed based on worst case conditions, as it should be. The critical combinatoric path has a maximum ...
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34 views

ADC conversion using PIC18

Simple code written for PIC18F24k40 as below. I could able get ADC analog output But when converted to time range selection above 4.15V and below 5 v i used to get display value as negative. i ...
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1answer
47 views

How to use/create a real time clock to use with specialized? [closed]

I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will ...
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1answer
89 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
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1answer
73 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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1answer
85 views

What's the difference between a LM3302N, TLC373CP, and LT1101CN8?

So I’ve got an LM3302N (IC COMPARATOR QUAD DIFF 14-DIP), LT1011CN8 (IC VOLTAGE COMPARATOR 5-V 8-DIP), and a TLC373CP (IC DUAL DIFF COMP 8-DIP) and I want to build a circuit inspired of the “1 minute ...
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1answer
50 views

Transistor activation / deactivation voltage in

The capacitor was allowed to discharge completely when the transistor was activated with the 3.4 V. The capacitor is allowed to charge again when the conduction from the 5 V line through the ...
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3answers
236 views

When using PWM, what is the purpose of having two complimentary square waves on the same channel?

I'd like to use the PWM I/O on the SAMA5D2 Series Microprocessor (Microchip).What I'm confused about is why each PWM channel has a high and low output pin. The datasheet specifies Each channel ...
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1answer
118 views

Verilog: Posedge sensitivity vs. If statement in Always block

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these ...
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1answer
91 views

Do front and back porches for digtal video really matter?

I am developing an LCD controller, and some of the code for my (third-party) timing generator includes horizontal and vertical front/back porch and vsync/hsync pulse time information for a different ...
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1answer
89 views

How to understand these 8086 bus cycle timing diagrams

Please see the two diagrams below. In the first diagram, each state (T1, T2, ...) seems to begin with the clock low. In the second diagram - with the clock high. If we look at the DR/R' signal - in ...
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1answer
60 views

Op-Amp settling time in bits

I was reading through this and was a bit confused. What do they mean by "took forever to settle to 10-bits (0.1%)"? How is 10-bits = 0.1%
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1answer
41 views

Any side effects of Initialisation and de-initialisation of STM32F0 MCU I2C pin frequently? [closed]

I have one port on my MCU and want to re-define its functionality. Is it possible that something wrong/strange happens if I do it in my main() function? I regularly ...
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1answer
60 views

Mapping two buttons press as a 3rd button

I got a cheap controller with only 5 buttons. I thought about soldering a few more in parallel so that pressing any of the additional buttons would trigger some other two buttons simultaneously. Then ...
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1answer
177 views

How can I delay a digital signal

I am generating a video signal using an AD724 and a microcontroller, which is genlocked to another video signal from a camera, and am using an SN74lVC2G53 analog switch to switch between signals. I'm ...
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2answers
48 views

Clock Generation from Oscillator

Is there specific standard ways to generate clocks from oscillators? Referring to generating a square-wave clock from a sinusoidal oscillator output. I can think of a few circuits involving diodes as ...
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0answers
285 views

Interfacing OV7670 camera with STM32F4 (no FIFO)

I have to interface my STM32F401RE with an OV7670 camera module without external AL422. I followed some of the many tutorials for Arduino, and I was able to capture images using Arduino UNO. ...
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1answer
82 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...
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0answers
187 views

What are the Bluetooth (low energy) scan settings of smartphones

My challenge: I'm trying to find out the best timings for a complex bluetooth low energy (BLE) system, where a central station shall be able to connect to smartphones (=scanner) as well as to coin-...
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1answer
75 views

Time taken by power supply to reach output voltage

My question is regarding programmable power supplies. If I send a SCPI command to the power supply using USB/RS-232 or some other serial communication, how do i know the time taken by the power supply ...
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2answers
68 views

Should a D Flip Flop store its input on clock rise?

I've seen conflicting descriptions and conflicting implementations of D Flip Flops, when it comes to how the Flip Flop behaves when its input value changes at the same time the clock rises. ...
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1answer
66 views

Timing constraints with real clocks

I am new with FPGA and timing constraints, so I apologize if the question will sound stupid. I try to understand timing constraints usage with FPGA. I have found the following description (in https://...
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3answers
195 views

How can calculate the turn-off time of an LDO?

This is the datasheet of TPS7A8101 LDO I am analyzing. In the datasheet, start-up time of the LDO is given as 80 ms for given conditions. My question is, how can I calculate the turn-off time of the ...
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3answers
2k views

Why am I Seeing A Weird “Notch” on the Data Line For Some Logical 1s?

I'm attempting to build a Z80 homebrew computer for some retrocomputing fun and to teach myself the basis of electronic design. For proof-of-concept, I've already assembled a basic system on ...
2
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1answer
51 views

PIC 12F675 with wrong timing

I have designed an assembler program for PIC 12F675, but it gives wrong timing. Datasheet says that internal oscillator is 4 MHz, and its instruction cycle is 4 clocks. Thus single instruction ...
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1answer
144 views

Which input of NAND is preferred and why? [duplicate]

Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the ...
2
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1answer
191 views

How do I interpret the setup/hold time on this RMII interface?

I'm coding the FPGA (MAC) side of an RMII interface between an Altera FPGA and LAN8720 device. Page 72 of the datsheet (pdf) shows the relevant timing diagram for this interface. The input setup/hold ...
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2answers
181 views

FPGA Max PWM Frequency

Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps". Being new in FPGA, I quite could not quite figure out how to extract this ...
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1answer
131 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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1answer
65 views

Timing two parallel lines on FPGA [Beginner]

So let's suppose I want to do certain action based on certain signal. I have signal "nx"; if it's 1, I want to "NOT" an X input(16bit) and if it isn't, I want the X unchanged. My idea was to do both ...
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1answer
115 views

Use Cellphone Vibrating motor in Mouse; on for 3sec off for 3 minutes

I have electronic maintenance experience but it dates to 1985 (last use). I can still solder well but I have forgotten all the electronic theory I once new except for VERY basic stuff. So assume I'm ...
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2answers
58 views

Comparison of 1G123 to 4538

I am designing the edge detection circuit with predefined output pulse duration. Pulse width will be 18.33 ms, supply power is 5V. Error tolerable is +-1 ms. There're a number of designs already ...
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2answers
111 views

Hold-time Violation and timing diagrams [duplicate]

I was wondering what the output of capturing flop looks like, if there is a hold time violation from capture flop. Can anyone explain with a timing diagram?
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0answers
54 views

Can I generate following voltage waveform with single PWM FET?

I am designing power supply which must output following voltages at a maximum of 1.5 A stepped down from a 24 V DC supply. 24 V 13-15 V 0-5 V Waveform for one of the inputs requires following ...

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