Questions tagged [timing]
This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.
331
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Measure time between trigger events
I want to measure the arrival time of three seperate digital pulses with respect to a global trigger.
The longest arrival time is expected to be <10ms and it would need to be able to determine the ...
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2
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Maintain accurate timing on 1pps 'heartbeat' signal
I have an application where I need to provide a 1 pulse per second 'heartbeat' signal with a very good accuracy over an extended period of time (1 second between pulse edges ± approx. 200 μs for ...
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Serial communication - previously sent information incorrectly stored in image buffer arrays
https://github.com/StonedEdge/Retro-Lite-CM4-Dock/tree/main
Hi everyone,
I am trying to read in some image data over serial communications, which is done on the trigger after receiving some characters ...
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Analog Timing Circuit with DIAC
I am currently trying to come up with an analog timing circuit to use within a solar tracker. I know using a 555 timer would be relatively easy to do here but I wanted to see if I could come up with a ...
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Clock direction in MII and RMII Interface
I know that in the MII interface, the clock is always sent from PHY to MAC irrespective of TX or RX?
Can someone explain me on why TX and RX, the PHY should send the clocks?
Like for the RX ...
user220456
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Circuit for Read/Write RAM Control Signals
I have the following architecture of an 8-bit bus / RAM interface where the bus can read from and write to the SRAM:
There are two 74LS245 8-bit bi-directional buffers, with there direction input ...
- 1,506
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76
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How to properly set timing constraint for SPI slave interface
I have designed a slave SPI interface using VHDL and synthesized it using DC. According to the datasheet attached below, how can I set the timing constraint related to the SLAVE SPI. I already have ...
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3
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204
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How to determine the horizontal pixel count out of a HSync and VSync signal
I have a project where I want to read the HSync and VSync signal from a VGA cable into an microcontroller and calculate the pixel clock.
Calculation: Pixel clock = Horizontal Pixel Count * Vertical ...
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58
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How to measure time between incoming packages on an FPGA?
For measuring the speed of incoming data packages on an FPGA, would you use a clock that is connected to a counter and each time a package is detected, it would store the time?
And if there would be a ...
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1
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Skew in half-bridge dead time generator in LMG5200EVM
The eval board for the GaN half bridge module LMG5200 (datasheet) contains the following circuit to generate dead time from a single PWM input.
The half-bridge module itself has good propagation ...
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How to solve for relay specifications?
I'm working with an unknown brand of relay and I need to know its specifications - most important is the minimum On current at approximately 42vDC, other values would be appreciated if possible.
Does ...
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Trying to get a 10uS pulse width to fire an SCR using a PIC16F884
I have the circuit built and running but I need to shorten the pulse width of the SCR. I am using a PIC16F884 running at 16MHz. I am using a half wave to control a device. When I use a for next loop, ...
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74HC93 produces a different signal when the frequency is increased
I'm trying to produce a signal using a 74HC93 that pulses high every 8th bit while the "SELECTOR" signal is low. The "SELECTOR" signal is 24 clock cycles.
It works fine at 4 MHz, ...
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Syncronize 2 digital signals
I have 2 digital signals, and I want them to synchronize.
the lower frequency yellow signal takes 32 clock cycles.
the higher frequency blue signal takes 8 clock cycles.
I need the lower frequency ...
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Are there any microcontrollers that do not require an external clock source?
I've seen a microcontroller (don't remember the exact part number at the moment,) that doesn't have XTAL pins.
It was an 8-pin MCU - it didn't have any clock input pins on the device.
How do those ...
user220456
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Low propagation delay pulse extender
I have a 100 ns, 5 V pulse which I need to extend to be over 2 μs. Is there a way to do this with <100 ns propagation delay? (Other factors are not important.)
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FPGA-centric timing constraints
I have designed an MMC slave on an FPGA that will interface with many different MMC masters with many different trace lengths, etc.
Most of the timing constraint documentation on how to constrain ...
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Optimal use of a timing pulse
I have an indicator module that uses an ATTiny85 to switch an array of LEDs based on an RS-485 signal delivered by SoftwareSerial and a MAX485 IC. The indicator can be Off, On, or Flashing. All power ...
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Optocoupler + MOSFET PWM amplifier timing issue
I want to drive a 12V, 1.5A valve from a microprocessor and also provide some isolation. The MCU outputs 3.3V logic, and I have this output going into a common source amp & also have a resistor in ...
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199
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UART to RS-485 communication between two Arduinos
I'm learning how to use a MAX485 or MAX487 IC to create a half-duplex RS-85 communication between two Arduino s.
Each Arduino has an LED that turns ON/OFF by receiving a command from the other Arduino....
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SPI interfacing a sensor doesn't seem to work
I'm trying to get a feeling for how the SPI protocol works. I built this cirucit using Proteus simulator.
simulate this circuit – Schematic created using CircuitLab
And then according to the ...
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2
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139
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1/60 Hz Counter/Divider
I have a fairly precise 1 Hz square wave that I would like to divide down to 1/60 Hz (1 pulse per minute). I want a one-chip solution and I am not having a lot of luck with this. I do not want a ...
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Synthesis of Blocking Statements in Verilog - time required for circuit to complete
This question is purely about synthesized verliog, not simulated.
I have read that blocking assignments are executed in order, but also that blocking assignments assign values to the RHS immediately. ...
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Why specify a maximum pulse width for reset pin?
A colleague and I are working with the Analog Devices AD74413R ADC for 4-20 mA current loop communications. On pages 15 and 16 of the datasheet, timing characteristics are presented.
We encountered an ...
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Trouble understanding length matching requirements
I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY.
My ...
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How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there ...
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Why does metastability occur if data changes during setup and hold time?
I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
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236
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ADC sampling and serial communication
Probably a rookie question and I'm overthinking it.
If I have an 8 bit ADC on a microcontroller sampling at 20 MHz, and the ADC operates at a 132 MHz clock, the voltage isn't communicated every period ...
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3
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441
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Driving GPIO outputs with FPGA: How to guarantee outputs of pins are set at same time
I was recently asked a question by an interview. We were discussing a hypothetical device that needed to drive 8 GPIO outputs of the FPGA. I was asked how to reduce the influence of propagation delay ...
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Using a level triggered latch as a negative edge trigger for negative logic
I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
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Reading timing diagram correctly?
I have the following timing diagram of a SPI communication.
Am I calculating total time T for receiving 24 bits correctly?
Diagram:
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35
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DS3231SN RTC -- timing between 1Hz SQW and clock seconds?
I don't think this is addressed in the DS3231SN datasheet but I may be missing something.
When the SQW output is programmed to output a 1Hz signal, is there a known / fixed phase relationship between ...
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How can the RMW instructions on PIC14 take a single cycle?
According to the PIC16F886 datasheet (pdf warning), an instruction like bcf takes a single cycle. It's also described as a read-modify-write instruction, i.e., it ...
- 406
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158
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VHDL timing confusion and possible metastability risk?
Timing, especially in sequential logic, confuses me a lot. I devised an example and drew a timing diagram and I would like to ask some question regarding it; all of them are about the same issue.
Here ...
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How to increase setup time of a reg wired to an EBR FIFO? (Lattice FPGA)
I'm using the built-in EBR FIFO of a Lattice FPGA:
...
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368
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In which clock edge does the I2C slave write?
I'm trying to implement an I2C master - slave example in an FPGA (Verilog).
As the I2C protocol specifies, the master must make sure that it writes the next bit enough time before the clock signal ...
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When buying parts with serial interfaces is it useful to check timing requirements?
When buying parts with serial interfaces is it useful to check timing requirements? I'm especially curious about something like I2C; is it generally enough to see that a component is capable of ...
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VHDL: input signal timing variations
VHDL newbie here; I am trying to solve a problem with an existing CPLD project (based on a Xilinx XC95144XL). The project in question is an plug-in cartridge for a vintage home computer, adding ...
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330
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Hold time constraint equation
I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint
Hold time ...
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Delaying a square wave by 1 us
This is a continuation of my previous question - Delaying a signal using LTC69942 - Some pulses missing at the output.
I have a square wave with below specifications:
I need to delay it by 1 us. I am ...
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Delaying a signal using LTC69942 - Some pulses missing at the output
I want to delay a square wave by 1us to 30us. I am using a LTC6994-2 for this purpose.
Currently, I provided a delay of 1us.
What I can see is some pulses of the input are missing at the output. ...
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369
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Wrong data clocked in when using direct daisy chains of 594/595 shift-registers
I was a bit surprised to find this question and its answer.
simulate this circuit – Schematic created using CircuitLab
When daisy chaining several HC595 or HC594 shift registers, with shared ...
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Standart Retiming circuit with two D type Flip Flops
I am trying to build a button(for adjusting the clock) syncroniser circuit for a seven segment clock. The button signals are of course async inputs so there needs to be retiming to make sure it goes ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ
I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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158
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How does Asynchronous DRAM perform self-timing
The original question was deemed lack of focus. This post is specifically about dram chip.
When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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Panasonic MN39470PT CCD Sensor Timing
The datasheet for the MN39470PT CCD sensor seems to be missing some details regarding the timing needed to drive the sensor. For this reason I'm very confused on how I'd drive the sensor particularly ...
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132
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Max clock frequency when cascading several 74HC for Address Decoding
I'm building a 6502 (WDC 65C02S) computer, for now on a breadboard (maybe later will I hopefully learn and move to a PCB).
In my Address Decoding Logic I'm using several NAND and 4-input NAND gates (...
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1
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DDR3 DQS "preamble"
I'm building a small testbench for a DDR3 memory controller and would like to verify that my unterstanding of DQS and DQ sampling points is correct.
The line state before the transmission is undefined ...
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Syncing microcontroller timer interrupts with slower external clock
I have been working on a data logger project that requires very accurate timestamps and intervals for reading data. I have been able to generate a timestamp by syncing a timer with a pulse per second ...
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Is there a microcontroller with zero interrupt jitter?
I know that interrupt latency depends on what the CPU is doing when the interrupt takes place (arm interrupt latency guide). This effect is called interrupt jitter. For my application I need an MCU ...
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