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Questions tagged [timing]

This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.

1
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2answers
81 views

FPGA Max PWM Frequency

Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps". Being new in FPGA, I quite could not quite figure out how to extract this ...
-1
votes
1answer
91 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
5
votes
1answer
58 views

Timing two parallel lines on FPGA [Beginner]

So let's suppose I want to do certain action based on certain signal. I have signal "nx"; if it's 1, I want to "NOT" an X input(16bit) and if it isn't, I want the X unchanged. My idea was to do both ...
-1
votes
1answer
76 views

Use Cellphone Vibrating motor in Mouse; on for 3sec off for 3 minutes

I have electronic maintenance experience but it dates to 1985 (last use). I can still solder well but I have forgotten all the electronic theory I once new except for VERY basic stuff. So assume I'm ...
0
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2answers
39 views

Comparison of 1G123 to 4538

I am designing the edge detection circuit with predefined output pulse duration. Pulse width will be 18.33 ms, supply power is 5V. Error tolerable is +-1 ms. There're a number of designs already ...
0
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2answers
48 views

Hold-time Violation and timing diagrams [duplicate]

I was wondering what the output of capturing flop looks like, if there is a hold time violation from capture flop. Can anyone explain with a timing diagram?
2
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0answers
46 views

Can I generate following voltage waveform with single PWM FET?

I am designing power supply which must output following voltages at a maximum of 1.5 A stepped down from a 24 V DC supply. 24 V 13-15 V 0-5 V Waveform for one of the inputs requires following ...
1
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1answer
50 views

Power-down sequencing with a “hard” power switch (stepper driver)

I'm designing a stepper motor controller and would like to have some advice on sequencing the shutdown process with a "hard" power switch. The Toshiba TB6560 driver that I'm using requires a specific ...
2
votes
2answers
151 views

How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my ...
2
votes
1answer
58 views

Order of write and read in Microprocessor interfaced with ADC

An ADC is interfaced with a microprocessor as shown in the figure. All signals have been indicated with typical notations. Acquisition of one new sample of the analog input signal by the ...
0
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1answer
45 views

Timing capacitor and resistors -Reg

I have this IC - Advance regulating PWM I would like to understand how does the timing resistor and capacitor section works. Sorry for the beginner question but I am unable to understand this section....
0
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0answers
17 views

doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
2
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2answers
128 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
0
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1answer
51 views

Rising edge duration of a low to high pulse

In a device I am using, I see the following in the description... "At start-up, the module requires an ON_OFF pulse sent from the host. A second pulse sent from the host will re-enter hibernate mode. ...
0
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2answers
81 views

GPSDO in firmware?

There are numerous designs online for hardware GPSDO (GPS-disciplined Oscillators). I'm failing to find any firmware-only implementations. I wonder if my Google foo is weak or if these are impractical ...
0
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1answer
60 views

Question about SR latch timing

I have a question about how SR latches work: To my understanding the real-world implication is that one of the two gates will receive power first and produce an output signal, and they aren't going ...
0
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2answers
44 views

Difference between low signal and no signal for a SR latch?

I am struggling to understand how the SR latch works. When an input has designation 0, this means "low signal" correct? Is this completely different than "no signal"? Doesn't a logic gate need some ...
0
votes
1answer
82 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
0
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1answer
92 views

How to turn off 555 Timer for a period of time after Vout signal passes through

I have a single-shot 555 Timer. After triggering, output goes high for a period of time. What I would like to do now: After Vout goes high and then low again, I want to disable the 555 timer for a ...
1
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0answers
66 views

How to measure SD card data timing vs. clock

I'm doing EVT testing of our product and I want to measure the SD card data vs. clock timing to make sure we're inside the specs. We're using LS1043A that boots Linux (via U-Boot) from an SD card ...
2
votes
1answer
78 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
0
votes
2answers
200 views

Questions about DMX512 protocol/STM

I want to make a DMX512 transmitter with a STM32F103 using HAL, CubeMX. I found some documentation like here about the protocol: Lighting-Control-using-DMX512-protocol-on-STM32. Sadly it does not ...
0
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2answers
52 views

Where to apply manual delay in character LCD

I went to http://www.elm-chan.org/docs/lcd/hd44780_e.html in an attempt to find out how to make an LCD module work with the shortest timings. While the site does help with the initialization of the ...
3
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1answer
250 views

SDRAM: Why CAS latency is configurable

I've seen a couple of very similar questions but the answers don't answer my question: DDR2 CAS Latency - is it fixed to clock-cycles or time? What limits the lower bound of DRAM CAS latency In my ...
0
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2answers
68 views

time counting at -50°C

I'm designing a small slow control system with ATMEGA2560. This board needs to measure temperature, voltage(0~4V), magnetic field using sensors, and monitor the digital status(High or Low) of some ...
0
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2answers
77 views

Timing control within a loop - Sending data at exact intervals [closed]

We have a program where we are sending data wirelessly through GPRS. We retrieve values from ADCs, do our calculations, display it on the screen and also send it to remote servers. The loop can be ...
2
votes
2answers
115 views

Timing a circuit's 'on-cycle' after a push button switch is pressed

First off, thank you for reading all of this - you are the part of the internet that gives me hope for mankind. I’m looking for a circuit that I would think is relatively straightforward, but has a ...
0
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1answer
51 views

DDRx timing analysis

I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write ...
1
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3answers
334 views

I2C slave not ACK'ing quickly enough

I am programming a microcontroller to talk with a slave device via I2C. My I2C transactions always get NACK'd, but I believe the slave is ACK'ing the transaction, just a little bit too late and my ...
0
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0answers
207 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
2
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0answers
73 views

How to properly constrain ethernet phy

I am trying to use the ethernet PHY on my Nexys4-DDR. The manual for the phy gives the following timing constraints for the RMII ports. I am getting confused as to what exactly the constraints for ...
4
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2answers
778 views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
0
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1answer
91 views

Two phase latch max delay constraint [closed]

In this timing diagram, why am I not including tcpq, i.e. the latch clock to Q propagation delay?
2
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4answers
188 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
1
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1answer
142 views

Is signal elaboration in VHDL an event?

I know a signal initialisation in VHDL is an event. But, what about a signal elaboration without assigning an initial value?
0
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3answers
390 views

RS-422 Signal Confusion

I am interfacing two RS422 devices but failing to do so. I started to monitor my device signals and fell into confusion. Please help me understand a few things. I am attaching snap 01 of my device (...
0
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1answer
160 views

Ethernet MII Timings MAC<->PHY

I am a student working on my graduation project, which will need an Ethernet interface. For such job I choose a microcontroller with built in MAC (STM32F777BIT) and for the PHY, the LAN 8740. I have ...
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0answers
150 views

Help with timing diagram

I have to complete this timing diagram but i couldn't figure out how to as there are 3 flip flops connected to each other it made me confused.
0
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0answers
52 views

How to find out T1H, T1L, T0H and T0L for ledstrip WS2813?

I have bought a led strip WS2813 from AliExpress. It does not have a decent datasheet with all details, neither does the seller knows about. I tried different settings (for what I could find at some ...
0
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1answer
181 views

How to draw a timing diagram for CSE 120 class

I've never done a timing diagram before. So I basically have no idea what I'm doing or what the question is asking. I would appreciate any help! Thank you.
1
vote
3answers
771 views

Controlling spotwelder timer with 555

I want to use the 555 time to control the timing on the power pulse of a spot-welder using a foot switch. I have seen a few 555 mono-stable circuits, but am having trouble finding the values of the ...
0
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0answers
253 views

Interrupt on falling edge PIC16F877

The PIC is supplied at 3.3V and clocked at 16kHz. For this part of the design I need the external interrupt to trigger on the falling edge of a 100Hz square wave signal on RB0 and toggle the state of ...
0
votes
1answer
56 views

SPI timing on CS5480

Good day folks :) i just want to know if i'm understanding it right? i read the datasheet and i saw the start-up row in the switching characteristics. Does every time - let's say i execute a command ...
1
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0answers
60 views

Migrating from C18 to XC8 ADC Conversion Issue

I'm working with Pic18f6622 and migrating my program into XC8 compiler. Before I'm using the C18 compiler ADC conversion was working just fine, but in new compiler ADC returns me 11 bits value and the ...
8
votes
3answers
516 views

How can I implement a very simple asynchronous DRAM controller?

I'd like to know how to build a bare bones asynchronous DRAM controller. I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. ...
0
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0answers
436 views

STMF4 ADC conversion seems slow

I'm using an STM32F4 to do some 12 bit conversions. I see from here that I should have hopes of getting somewhere around 1us per conversion, and since I'm doing 2 conversions, I would expect ...
0
votes
1answer
172 views

How is the trigger pulse of the 555 timers generated? [closed]

I would like to connect an operational amplifier to the trigger circuit which then generates the pulse that starts the timing of the timer almost always connected to the clock generator. Since 555 ...
7
votes
3answers
562 views

Why is there a maximum time for length of write pulse to write on an EEPROM?

I am still just learning about electronics on my own, so please bear with me. The EEPROMs that I have come across (for example this one where the t_wp max is 1000 ns.) all have a time limit for the ...
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1answer
290 views

Timing Diagram in Microprocessor

Though i know what is undergoing the microprocessor looking at the timing diagram, what confused me is: What is the amount of time period taken to complete the operation. What are the ...
0
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0answers
74 views

Calculate DRAM latency

I am trying to make some performance on a memory centric network which has one cpu and multiple memory cubes.(HMC) I want to calculate the intra HMC latency which means the latency between sending a ...