Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

0
votes
0answers
14 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
0
votes
1answer
37 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
0
votes
0answers
57 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
0
votes
0answers
23 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
0
votes
2answers
50 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
0
votes
0answers
85 views

Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
1
vote
0answers
33 views

Relationship between clock skew (For Reg-Reg path) and minimum clock pulse width requirement for capture Flop

I am hoping if some expert in timing analysis could answer on this topic. Here is the question: I am creating a liberty timing file for an IP block using ETM (Extracted Timing Model) method. ...
1
vote
0answers
23 views

Data path in logic circuit

In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3? Thanks.
3
votes
1answer
92 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
0
votes
0answers
19 views

doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
2
votes
3answers
133 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
2
votes
2answers
135 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
0
votes
1answer
52 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
1
vote
1answer
90 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
0
votes
1answer
94 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
2
votes
1answer
340 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
2
votes
2answers
390 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
0
votes
1answer
61 views

EEPROM 25LC1024 issue with PIC32MX OLIMEX board

I am trying to read the status register for the EEPROM following the instructions in this Application Note. I wanted to have the opinion of the community on the signals I am getting. They don't seem ...
0
votes
1answer
224 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
4
votes
2answers
883 views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
1
vote
0answers
85 views

Intel/Altera FPGA bidirectional DQS timing constraint

I have a DDR controller implemented in an FPGA using Altera/Intel/Quartus, and I'm trying to get the constraints correct for the bidirectional DQS pin. This pin is a data strobe pin that the DDR ...
0
votes
1answer
130 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
0
votes
2answers
182 views

Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
0
votes
1answer
32 views

Is post fit simulation using timing netlists necessary although design meets setup-hold time requirements?

In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are ...
2
votes
4answers
197 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
0
votes
0answers
87 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
0
votes
1answer
99 views

Thoughts on this circuit

Here I have a design ( Vcc = 12V ) where relay gets activated whenever reed switch gets closed. I want to activate the relay after a delay of about 2 to 3 seconds from the instant reed switch gets ...
1
vote
1answer
117 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
4
votes
3answers
204 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
1
vote
2answers
258 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
0
votes
2answers
177 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
3
votes
1answer
436 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
1
vote
0answers
254 views

Vivado timing constraints wizard

I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock. A defined INCLK TXCLK and clk_sys as primary clocks in ...
0
votes
1answer
164 views

What are minimum requirements to start of with STA [closed]

What are the minimum requirements to start with static timing analysis. I know usage of FPGAs and VHDL. Will that be enough? Are there any free tools for STA pls.?
0
votes
2answers
185 views

Timing the change mode (Read/Write) on SD card

I'm currently working on a device which connects a SD card to a FPGA. I have to find out how much time the SD card takes to switch between the reading and writing modes. I have already searched the ...
1
vote
1answer
220 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
2
votes
2answers
599 views

How to calculate latency of a circuit?

Lets say we have this circuit: tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns First I want to check this circuit for hold-...
0
votes
6answers
171 views

FPGA: intentional delays through manual placement/routing

In my FPGA design, I have some input signals that need to be delayed considerably before they reach the first clocked register. There are delay elements near the pins for exactly that purpose, but ...
2
votes
1answer
885 views

how to get the timing report register to register and input to output in STA?

I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths. Input to register Register to register Register to output Input to output Practically, I want to ...
-1
votes
2answers
240 views

How to measure FPGA execution time of combinationals blocks [on hold]

I have written a combinational block which makes some math operations. What's the best way to calculate the time elapsed in that block? Thanks in advance!
0
votes
2answers
264 views

FPGA Internal Timing constraint failing

I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely ...
0
votes
2answers
3k views

SR latch timing diagram or waveform with delay, help!

I'm having trouble solving these two problems (my solution and general solution showed): What I did was follow the truth table and based on the combination on the graph draw the appropriate state ...
5
votes
2answers
188 views

Synchronize Outputs of Separate FPGAs Within 1ns

Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution. I'm trying to ...
4
votes
1answer
399 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
1
vote
1answer
67 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
0
votes
0answers
501 views

Drawing a timing diagram for a circuit showing X, Y, and Z. What is Z doing?

I'm looking over the following question: I have the answer, and for the most part, I think I understand the logic: y = z' and z = xy. There's a 15ns delay (10 from the AND gate and 5 from the ...
0
votes
0answers
38 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
4
votes
3answers
240 views

Help understanding practical transistor considerations?

So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance. It seems like everything I've been taught so far in classes about transistors ...
0
votes
0answers
147 views

Syncronized reset timing (vivado)?

I have reset synchronizer in my top block (attached file). In my project I have blocks which get 125_clk, and others 250_clk. In addition I have srstn_sm block which its output is input for srstn ...
1
vote
2answers
235 views

Typical vs. min/max timing and voltages

I'm currently reading through the datasheet for the 74HC165 8-bit asynchronous parallel-to-serial shift register, and I've a handful of questions about the static and dynamic characteristics described ...