Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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313 views

Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a ...
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1answer
45 views

How to use/create a real time clock to use with specialized? [closed]

I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will ...
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1answer
28 views

Testing QSPI Setup time and Hold time

I am having a QSPI Interface (operated in SDR mode) from this QSPI chip to MCU chip. QSPI lines : QSPI CLK QSPI CS QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_1O3 VSS VDD I am trying to validate the QSPI Setup ...
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1answer
76 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
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1answer
76 views

Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
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1answer
36 views

Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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1answer
48 views

Missing contamination delay specification for a component

If IIUC: contamination delay (\$t_{cd}\$) is the time where the signal level on the output of a component starts to change in response to a change on the component's input, while the propagation delay ...
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3answers
95 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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2answers
44 views

Path analysis D-FLIP-FLOP - what is SET?

I have to calculate the clock paths in a circuit and I have a 2 dual positive-edge-triggered D-TYPE FLIP-FLOP with clear and reset called DFF1 and DFF2. Data sheet: http://www.ti.com/lit/ds/symlink/...
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4answers
190 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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1answer
70 views

Can we use long wires with ultrasonic module HC-SR04

I want to use Ultrasonic module HC-SR04 as ranging sensor but my MCU board is approx 80 ft away from the place where I have to put the US module. These are its pin-outs and descriptions: My ranging ...
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1answer
53 views

Timing constraints with real clocks

I am new with FPGA and timing constraints, so I apologize if the question will sound stupid. I try to understand timing constraints usage with FPGA. I have found the following description (in https://...
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47 views

How to calculate BER and sweep time from eye diagram?

I am iterating the SI simulation for the traces of the USB and LPDDR3 interfaces with processor. Is there any method to calculate the BER and sweep values from the eye diagram?
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1answer
105 views

What will be the real voltage along the line with a voltage source and a capacitor?

Take the following circuit: If I do a simulation of this circuit I get this graph: The strange thing is that in the simulator it gives the same voltage sine wave in the circuit, near the voltage ...
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36 views

FPGA Timing Constraint for 2 Combinational paths to take the same time

I am trying to do a simple asynchronous FPGA design where I have 2 inputs and 2 outputs, and assign the outputs to the inputs. I need the delay of both assign's to be near identical. What timing ...
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1answer
102 views

Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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29 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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1answer
39 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
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32 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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2answers
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Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...
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Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
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48 views

Relationship between clock skew (For Reg-Reg path) and minimum clock pulse width requirement for capture Flop

I am hoping if some expert in timing analysis could answer on this topic. Here is the question: I am creating a liberty timing file for an IP block using ETM (Extracted Timing Model) method. ...
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Data path in logic circuit

In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3? Thanks.
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1answer
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
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doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
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3answers
229 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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2answers
192 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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56 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
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1answer
142 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
159 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
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1answer
939 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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2answers
617 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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1answer
68 views

EEPROM 25LC1024 issue with PIC32MX OLIMEX board

I am trying to read the status register for the EEPROM following the instructions in this Application Note. I wanted to have the opinion of the community on the signals I am getting. They don't seem ...
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1answer
440 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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2answers
1k views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
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1answer
208 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
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289 views

Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
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1answer
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Is post fit simulation using timing netlists necessary although design meets setup-hold time requirements?

In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are ...
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4answers
286 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
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124 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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1answer
106 views

Thoughts on this circuit

Here I have a design ( Vcc = 12V ) where relay gets activated whenever reed switch gets closed. I want to activate the relay after a delay of about 2 to 3 seconds from the instant reed switch gets ...
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1answer
184 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
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3answers
374 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
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2answers
360 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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2answers
333 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
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1answer
644 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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0answers
320 views

Vivado timing constraints wizard

I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock. A defined INCLK TXCLK and clk_sys as primary clocks in ...
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1answer
247 views

What are minimum requirements to start of with STA [closed]

What are the minimum requirements to start with static timing analysis. I know usage of FPGAs and VHDL. Will that be enough? Are there any free tools for STA pls.?