Questions tagged [timing-analysis]
Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.
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Timing constraints for external ADC for clock generated by FPGA
I am using an FPGA to generate a 100 MHz clock to an external 8-bit ADC.
The external ADC is the ADC08100 and the valid sample window is -1.5ns to 4.4ns in regards to the rising edge of the clock. I ...
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Calculating timing constraings for interfacing with sdram
I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them.
My understanding so far:
To calculate the set_output_delay ...
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Timings constraints when interfacing an external ADC with an FPGA
I am currently using a Trion T8 FPGA to receive and store data from an external ADC, the ADC08100. The FPGA uses the internal PLL to generate a 100 MHz (10 ns period) clock signal, and its logic runs ...
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How to write I2C protocol timing constraints?
How do you normally write clock timing cons for I2C? Assuming 1 SDA line, 1 SCL line, 1 APB reference CLK called PCLK.
Q. What are the relation of PCLK to SCL in this protocol? Does it matter if it is ...
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Pin inductance vs pin capacitance in determining rise and fall times
I am a beginner in digital electronics and VLSI.
I know that pin capacitance is an important parameter in determining the rise and fall times of logic gates and ICs.
This is supported by my intuition ...
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How to minimize slack for mod in numerical package?
Here is the snippet of the code in VHDL.
I mean this IEEE.numeric_std.all
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Debuging verilog SDRAM controller
I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
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How to properly set timing constraint for SPI slave interface
I have designed a slave SPI interface using VHDL and synthesized it using DC. According to the datasheet attached below, how can I set the timing constraint related to the SLAVE SPI. I already have ...
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Timing constrain the ADC to FPGA data path
An ADC uses 12 single ended CMOS signals to transfer data to an FPGA. Both of them share 120 MHz source on the PCB. However, the PCB delay from the oscillator to the clock pin of each component is ...
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Asynchronous read memory causing hold violations in an FPGA
I have a pipelined CPU design in Verilog that uses a memory block whose reads are asynchronous. I have usually had separated memory for instructions and data and everything worked fine, but recently I ...
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Vivado constraints wizard suggests a lot of nonsense generated clocks
I'm trying to apply timing analysis to a RISC-V MCU I have designed in SystemVerilog, in Vivado, for a Basys 3 board.
My design contains several generated clocks, which are made by dividing the system ...
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How to write to a Hitachi HM628128A SRAM?
I'm working with a Hitachi HM628128A SRAM chip.
According with the datasheet, the function table is
How do I write data in the chip? Must I execute "write cycle (1)" and then "write ...
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Basys 3 FPGA 7 segment display output delay
I have an FPGA design for my Basys 3 that drives the board's 7 segment display to display some numbers. I'm using Vivado.
When I do the timing analysis, the constraint wizard asks me to set the output ...
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Don't understand why this clock interaction is unsafe
I'm starting with static timing analysis. I have a very simple Verilog design that has clock interaction problems, and I don't see why. It just has a counter whose LSB is sent to an LED. Could I get ...
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Hold violation in clock divider in an FPGA
I have a Verilog design for a Basys 3 in which I display a number increasing by 1 each half second in a 7 segment display.
I'm running the timing analysis in Vivado, and I get a hold time violation ...
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In an FPGA, is the input port delay related to the output port delay in the previous block?
Consider the following circuit in an FPGA:
Let's say the output port O1 is constrained to have a min/max delay of 1 and 3 ns respectively. That means the circuit will be optimized for allowing a max. ...
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Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
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Why don't 2 flip-flop synchronizers have a reset?
This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily".
So, my question is:
Why do almost all of ...
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Why is a reset with asynchronous assert safe?
As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
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FPGA-centric timing constraints
I have designed an MMC slave on an FPGA that will interface with many different MMC masters with many different trace lengths, etc.
Most of the timing constraint documentation on how to constrain ...
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CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?
Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current?
Example: let's assume for this argument ...
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Timing Async Reset with Sync Deassert
I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my ...
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Does synthesis/ PnR tool need create_generated_clock constraint for clock MUX output?
Does Synthesis/PnR tool need a create_generated_clock constraint for clock MUX output ? If yes, why does the tool need such constraint?
My previous understanding is that we only need ...
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STA timing closure for asynchronous FIFO
I have implemented an asynchronous FIFO
However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.
Both read_clk and ...
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create_generated_clock quartus for derived clock
I am working in a design that creates a 1Hz clock from 20MHz PLL out.
For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000.
That 1Hz clock is used as ...
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Carry bypass adder delay higher than expected with timing analysis
Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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Why does metastability occur if data changes during setup and hold time?
I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
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How to properly implement an n-FF synchronizer in Lattice FPGAs?
Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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How to constrain a source-synchronous FPGA input?
I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information:
fmax = 300 MHz (single data rate)
tsetup = ...
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Variation in Tphl of MOS nand gate due to input patterns
I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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Frequency of a sequential circuit
I'm reading the book Digital Design and Computer Architecture. I came across this exercise:
From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?
In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
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What's the criterion to move from only having CDC for the control lines to include the data buses?
I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals.
I'm, however, wondering what the criteria is to add synchronization to the data bus ...
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Constraining combinatorial path delays in Intel Cyclone-V FPGA
I am working on a design with a Cyclone-V FPGA.
I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother.
4 DFFs running on each of these respective ...
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does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?
In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device.
Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ
I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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Is "transition time" the same as "contamination delay"? If not, what is equivalent to \$t_{cd}\$ in the datasheets?
In the CD4013B datasheet the following timing table (excluding clock related values) can be found:
According to the answer to this question, the contamination delay would be the minimum propagation ...
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Why does my counter appear to work if it fails timing closure?
I configured my FPGA (Artix-7, -1 speed grade) to run a clock at higher speeds than it is designed for (464MHz). Naturally, I received the below egregious timing errors when implementing a 12-bit ...
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What is the difference between "2 synchronize" and "metastability"?
As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below,
cross clock domain databus
But I came across about ...
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Constraining simple design
I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce.
Here's the simple code:
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Metastability in 3 or 2 flop synchronizer if input is valid for at least 2 clocks
In this image:
Figure 1: metastability in 2 or 3 flop synchronizer
If the metastability of first flop doesn't get resolved in 4th clock, is it possible that it may get resolved to '0' in 5th clock? ...
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How to correctly constrain a clock network with lots of mux branches?
Let me simplify a common clock network structure used in my company:
Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs).
Right at the beginning when these sources are &...
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Do more logic gates in series mean more slowing of the output result?
I heard that every logic gate has a propagation delay in nano scale.
As the digital signal propagates through the logic gates, the signal output result will have a delay.
Even though the delay is so ...
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Propagation and contamination delays with different delays for rising and falling edges
In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way:
The propagation delay \$t_{...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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Different output delays for internal to output and input to output path
I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY.
The timing constraints from internal ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?
There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How to calculate overall average propagation delay for digital circuit given
Using the circuit shown with 3 inputs {A,B,C}, and outputs {F1,F2,F3}, and using the average propagation shown below for each gate:
AND -> tpd = 9ns,
XOR -> tpd = 8ns,
OR -> tpd = 10ns
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Why Tcd and Tpd is different in combinational ckt?
In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons:
Different rising and falling delays,
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Counting no. of clock cycles
This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space.
Is there ...
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