Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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How NLDM(Non-Linear Delay Model) model works exactly? Like what is its internal algorithm?

I have been reading NLDM and CCS models, but everywhere, only its advantages and disadvantages are written. No one has described how NLDM has that disadvantage through its internal working algorithm? ...
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STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and ...
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create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...
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Carry bypass adder delay higher than expected with timing analysis

Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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Why does metastability occur if data changes during setup and hold time?

I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
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How to properly implement an n-FF synchronizer in Lattice FPGAs?

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
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Variation in Tphl of MOS nand gate due to input patterns

I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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Frequency of a sequential circuit

I'm reading the book Digital Design and Computer Architecture. I came across this exercise: From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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When is it safe to ignore clock-domain crossing results from Microchip (Microsemi) Libero SoC's CDC report?

Inside my design, I'm only adding synchronizers to the control signals traveling between two different clock domains. The data buses are aligned with a pretty simple handshake scheme and don't have ...
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?

In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
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What's the criterion to move from only having CDC for the control lines to include the data buses?

I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals. I'm, however, wondering what the criteria is to add synchronization to the data bus ...
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Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
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does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?

In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device. Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing ...
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Finding Elmore delay if S/D are shared, between two unequal transistors?

If W=3, and Cload = 10, How can we find output pull down delay? If there is no sharing of S/D then the problem is simple C_n=(2+W)C delay = (R/W)(C_n) + (R/W + R/2)(C_load) but when we are sharing S/D ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ

I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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Is "transition time" the same as "contamination delay"? If not, what is equivalent to \$t_{cd}\$ in the datasheets?

In the CD4013B datasheet the following timing table (excluding clock related values) can be found: According to the answer to this question, the contamination delay would be the minimum propagation ...
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Why does my counter appear to work if it fails timing closure?

I configured my FPGA (Artix-7, -1 speed grade) to run a clock at higher speeds than it is designed for (464MHz). Naturally, I received the below egregious timing errors when implementing a 12-bit ...
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What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...
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Constraining simple design

I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce. Here's the simple code: ...
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Metastability in 3 or 2 flop synchronizer if input is valid for at least 2 clocks

In this image: Figure 1: metastability in 2 or 3 flop synchronizer If the metastability of first flop doesn't get resolved in 4th clock, is it possible that it may get resolved to '0' in 5th clock? ...
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How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are &...
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Do more logic gates in series mean more slowing of the output result?

I heard that every logic gate has a propagation delay in nano scale. As the digital signal propagates through the logic gates, the signal output result will have a delay. Even though the delay is so ...
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Propagation and contamination delays with different delays for rising and falling edges

In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way: The propagation delay \$t_{...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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Different output delays for internal to output and input to output path

I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY. The timing constraints from internal ...
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Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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How to calculate overall average propagation delay for digital circuit given

Using the circuit shown with 3 inputs {A,B,C}, and outputs {F1,F2,F3}, and using the average propagation shown below for each gate: AND -> tpd = 9ns, XOR -> tpd = 8ns, OR -> tpd = 10ns ...
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Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
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Counting no. of clock cycles

This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space. Is there ...
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Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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Calculating how long it takes for a circuit to compute the output for a given set of inputs

I'm having trouble with analyzing a circuit with respect to time, given clock-to-q, setup, and delays of individual components. We are given that \$t_{clk-to-q} = 3ps\$ \$t_{setup}=4\$ \$t_{shifter}=...
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Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...
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Explanation of the filter timing analysis in FPGA

I have wrote a FIR filter in VHDL by using ISE design suit. In design summary I can get all information about the timing analysis. There is information about the max frequency. and I have also found ...
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Lattice iCECube2 cannot find clock in .sdc file

I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, ...
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How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)

The Xilinx Vivado's set_max_delay requires -from to be set. Basically I'd like to set max delay TO a register. Because there can ...
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SDC Constraint for reset synchronizer

I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the ...
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Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
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What timing constrains would I need to set for a handshake based clock transfer

I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations. Setup/hold violations and in addition some rule check ...
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Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.) I tried to analyze their behaviors at the clock edges. For D flip-flop 1,...
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How to use a CSV file from an oscilloscope for further analysis

I saved and opened this data from my oscilloscope: How to plot the real scale waveform data? Do I have to multiply it with vertical scale? And what about the time? What to do if I want to plot the ...
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T_hold and T_setup help me understand?

My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this. Giving the following circuit: And giving that both FF are connected to the ...
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D-Flip-Flop Hold and Setup Timing Requirements

Update: The answer is 28ns for sure Giving the following circuit and timing table: Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
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D-Flip-Flop Hold and Setup Timing

I am solving some question to prepare for my exam but got stuck on this one and need your help. Giving the following circuit: Where input x gets updated 10ns after ...
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Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...
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How does the loopback on a non-retriggerable monostable work?

I understand how to connect a monstable multivibrator to be in the non-retriggerable mode. Just loopback the /Q to the falling edge input or the Q to the rising edge output) as in the following ...
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IO clock pin far from design, reduce propagation delay

My design is deployed around a particular tile in the FPGA, mainly because of a gigabit transceiver that is located there. However one of the clocks needed for the gigabit transceiver has to come from ...
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Fastest possible memory copy between 2 12ns SRAM DIP chips

Electronics newbie here... I'm trying to build a retrocomputer, and learn digital electronics along the way. I decided to begin with the video generation part, with a fast memory copier, independent ...
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3 answers
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Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
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