Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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49 views

Different output delays for internal to output and input to output path

I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY. The timing constraints from internal ...
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55 views

Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
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1answer
85 views

How to calculate overall average propagation delay for digital circuit given

Using the circuit shown with 3 inputs {A,B,C}, and outputs {F1,F2,F3}, and using the average propagation shown below for each gate: AND -> tpd = 9ns, XOR -> tpd = 8ns, OR -> tpd = 10ns ...
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51 views

Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
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36 views

Counting no. of clock cycles

This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space. Is there ...
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49 views

Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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1answer
32 views

Calculating how long it takes for a circuit to compute the output for a given set of inputs

I'm having trouble with analyzing a circuit with respect to time, given clock-to-q, setup, and delays of individual components. We are given that \$t_{clk-to-q} = 3ps\$ \$t_{setup}=4\$ \$t_{shifter}=...
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1answer
76 views

Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...
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1answer
147 views

Explanation of the filter timing analysis in FPGA

I have wrote a FIR filter in VHDL by using ISE design suit. In design summary I can get all information about the timing analysis. There is information about the max frequency. and I have also found ...
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Lattice iCECube2 cannot find clock in .sdc file

I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, ...
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1answer
63 views

How to track down all the registers connected to a specific downstream register? (for set_max_delay's --from)

The Xilinx Vivado's set_max_delay requires -from to be set. Basically I'd like to set max delay TO a register. Because there can ...
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1answer
91 views

SDC Constraint for reset synchronizer

I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the ...
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37 views

Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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1answer
92 views

SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
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1answer
61 views

What timing constrains would I need to set for a handshake based clock transfer

I want to transfer a couple of bits between two clocks, so I build a small handshake logic, but my timing analyzer shows me some violations. Setup/hold violations and in addition some rule check ...
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372 views

Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.) I tried to analyze their behaviors at the clock edges. For D flip-flop 1,...
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2answers
163 views

How to use a CSV file from an oscilloscope for further analysis

I saved and opened this data from my oscilloscope: How to plot the real scale waveform data? Do I have to multiply it with vertical scale? And what about the time? What to do if I want to plot the ...
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1answer
76 views

T_hold and T_setup help me understand?

My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this. Giving the following circuit: And giving that both FF are connected to the ...
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2answers
218 views

D-Flip-Flop Hold and Setup Timing Requirements

Update: The answer is 28ns for sure Giving the following circuit and timing table: Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
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Timing diagram question of an EL-display

I am having a hard time interpreting this timing diagram of a Planar electroluminescent display; datasheet: Planar EL320.256-F6 pages 10-11 in the browser pdf viewer. If i read this correctly, it ...
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1answer
96 views

D-Flip-Flop Hold and Setup Timing

I am solving some question to prepare for my exam but got stuck on this one and need your help. Giving the following circuit: Where input x gets updated 10ns after ...
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1answer
85 views

Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...
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64 views

How does the loopback on a non-retriggerable monostable work?

I understand how to connect a monstable multivibrator to be in the non-retriggerable mode. Just loopback the /Q to the falling edge input or the Q to the rising edge output) as in the following ...
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2answers
48 views

IO clock pin far from design, reduce propagation delay

My design is deployed around a particular tile in the FPGA, mainly because of a gigabit transceiver that is located there. However one of the clocks needed for the gigabit transceiver has to come from ...
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61 views

How can we validate the MCP (multi cycle) settings in SDC if the design is huge?

Is there any standard method or tool available for validation of the multi cycle paths that are set as part of the SDC file during timing analysis. For small designs manual validation can be performed ...
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157 views

Fastest possible memory copy between 2 12ns SRAM DIP chips

Electronics newbie here... I'm trying to build a retrocomputer, and learn digital electronics along the way. I decided to begin with the video generation part, with a fast memory copier, independent ...
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3answers
97 views

Using too many Modules in Verilog affect timing?

I have a straightforward quest about HDL and FPGA design. If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top ...
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1answer
133 views

Application of set_clock_latency

I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using ...
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1answer
55 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
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Modelling effects of unbuffered library characterization cell outputs on timing constraint tables

Can someone explain to me or point me to a resource that will shed some light on how (instead of using a buffered library cell, we use a unbuffered library cell) including the effects of unbuffered ...
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3answers
57 views

What is the typical delay relative to to the maximum delay?

I have a board with a number of ICs, an FPGA, and some flash and RAM devices. The board is designed based on worst case conditions, as it should be. The critical combinatoric path has a maximum ...
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1answer
183 views

How to constrain delay in the circuit without a clock?

Background: The image below is, in essence, a simplified schematic of the, so called asynchronous state machine (AM_fsm.v). The design does not have any clock input signal. It contains many SR latches ...
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553 views

Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a ...
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How to use/create a real time clock to use with specialized? [closed]

I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will ...
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1answer
151 views

Testing QSPI Setup time and Hold time

I am having a QSPI Interface (operated in SDR mode) from this QSPI chip to MCU chip. QSPI lines : QSPI CLK QSPI CS QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_1O3 VSS VDD I am trying to validate the QSPI Setup ...
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1answer
153 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
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1answer
115 views

Clock domain crossing of a bus between related clocks

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned). The Xilinx Timing Closure User Guide ...
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1answer
250 views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
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40 views

Expected output of DFF_2 if DFF_1 has hold violation

I am trying to figure out the output of flop DFF_2 when If DFF_1 has hold violation. My answer - DFF_2(Q) = X If DFF_2 has hold violation. My answer - DFF_2(Q) = X I understand the FF's go to meta-...
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1answer
48 views

Missing contamination delay specification for a component

If IIUC: contamination delay (\$t_{cd}\$) is the time where the signal level on the output of a component starts to change in response to a change on the component's input, while the propagation delay ...
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3answers
105 views

Use condition from one clock with registers from another, synchronized clock

Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency? This works as expected in simulation:...
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2answers
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Path analysis D-FLIP-FLOP - what is SET?

I have to calculate the clock paths in a circuit and I have a 2 dual positive-edge-triggered D-TYPE FLIP-FLOP with clear and reset called DFF1 and DFF2. Data sheet: http://www.ti.com/lit/ds/symlink/...
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555 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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1answer
368 views

Can we use long wires with ultrasonic module HC-SR04

I want to use Ultrasonic module HC-SR04 as ranging sensor but my MCU board is approx 80 ft away from the place where I have to put the US module. These are its pin-outs and descriptions: My ranging ...
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1answer
87 views

Timing constraints with real clocks

I am new with FPGA and timing constraints, so I apologize if the question will sound stupid. I try to understand timing constraints usage with FPGA. I have found the following description (in https://...
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1answer
114 views

What will be the real voltage along the line with a voltage source and a capacitor?

Take the following circuit: If I do a simulation of this circuit I get this graph: The strange thing is that in the simulator it gives the same voltage sine wave in the circuit, near the voltage ...
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FPGA Timing Constraint for 2 Combinational paths to take the same time

I am trying to do a simple asynchronous FPGA design where I have 2 inputs and 2 outputs, and assign the outputs to the inputs. I need the delay of both assign's to be near identical. What timing ...
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371 views

Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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1answer
61 views

Why only shared resistances are taken into consideration while computing Elmore delay?

While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
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2answers
150 views

Why Static Time Analyzer (STA) Engine doesn't show fmax for Fast Model?

I'm working on Intel FPGA. The Timing Analyzer (STA Engine) gives Fmax summary for both slow Models but none for the fast model WHY?. I didn't find any setting for this in documentation or in GUI. (...