Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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Why don't 2 flip-flop synchronizers have a reset?

This is similar to this question, asking if a reset is needed in a 2 flip-flop synchronizer. The answer to that question was: "no, not necessarily". So, my question is: Why do almost all of ...
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1 answer
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FPGA-centric timing constraints

I have designed an MMC slave on an FPGA that will interface with many different MMC masters with many different trace lengths, etc. Most of the timing constraint documentation on how to constrain ...
2 votes
2 answers
59 views

Why is a reset with asynchronous assert safe?

As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
1 vote
1 answer
641 views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
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1 answer
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CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?

Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current? Example: let's assume for this argument ...
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1 answer
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Does synthesis/ PnR tool need create_generated_clock constraint for clock MUX output?

Does Synthesis/PnR tool need a create_generated_clock constraint for clock MUX output ? If yes, why does the tool need such constraint? My previous understanding is that we only need ...
2 votes
3 answers
871 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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4 answers
141 views

Is metastability not a concern in CDC if the signal in source clock is at least 3x wide as that of destination clock's period?

There are so much hype and concern over metastability in cross clock domain. If the goal as an ASIC/FPGA designer is to ensure that the signal in source clock get propagated to destination clock even ...
1 vote
1 answer
193 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
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1 answer
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Timing Async Reset with Sync Deassert

I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my ...
2 votes
1 answer
255 views

MT9M001 to FPGA input timing

MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The ...
2 votes
1 answer
109 views

create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...
4 votes
1 answer
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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1 answer
310 views

Testing QSPI Setup time and Hold time

I am having a QSPI Interface (operated in SDR mode) from this QSPI chip to MCU chip. QSPI lines : QSPI CLK QSPI CS QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_1O3 VSS VDD I am trying to validate the QSPI Setup ...
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How NLDM(Non-Linear Delay Model) model works exactly? Like what is its internal algorithm?

I have been reading NLDM and CCS models, but everywhere, only its advantages and disadvantages are written. No one has described how NLDM has that disadvantage through its internal working algorithm? ...
3 votes
2 answers
142 views

Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
-1 votes
1 answer
171 views

STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and ...
1 vote
1 answer
385 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
2 votes
1 answer
223 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
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1 answer
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Carry bypass adder delay higher than expected with timing analysis

Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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2 answers
57 views

Why does metastability occur if data changes during setup and hold time?

I understand that data needs to be valid during the setup and hold windows to prevent an unknown output or metastable condition. But what I don't understand is, why does this happen? Why is it that ...
0 votes
1 answer
168 views

Constraining simple design

I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce. Here's the simple code: ...
4 votes
1 answer
217 views

How to properly implement an n-FF synchronizer in Lattice FPGAs?

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
2 votes
2 answers
168 views

Variation in Tphl of MOS nand gate due to input patterns

I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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1 answer
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Frequency of a sequential circuit

I'm reading the book Digital Design and Computer Architecture. I came across this exercise: From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
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3 answers
1k views

How to use a CSV file from an oscilloscope for further analysis

I saved and opened this data from my oscilloscope: How to plot the real scale waveform data? Do I have to multiply it with vertical scale? And what about the time? What to do if I want to plot the ...
0 votes
3 answers
131 views

What is the difference between "2 synchronize" and "metastability"?

As far as I know, 2 synchronize used to be used in in asynchronous FIFO for preventing metastability in multi clock domain. as the below, cross clock domain databus But I came across about ...
5 votes
4 answers
880 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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When is it safe to ignore clock-domain crossing results from Microchip (Microsemi) Libero SoC's CDC report?

Inside my design, I'm only adding synchronizers to the control signals traveling between two different clock domains. The data buses are aligned with a pretty simple handshake scheme and don't have ...
2 votes
1 answer
306 views

How to calculate the number of required flip-flop stages needed for clock-domain crossing?

In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
0 votes
1 answer
69 views

What's the criterion to move from only having CDC for the control lines to include the data buses?

I've noticed that in most designs synchronized signals crossing clock domains are implemented for control signals. I'm, however, wondering what the criteria is to add synchronization to the data bus ...
0 votes
1 answer
158 views

does a 2-flip-flop synchronizer for clock domain crossing need a clear (reset) input signal?

In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device. Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing ...
1 vote
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Finding Elmore delay if S/D are shared, between two unequal transistors?

If W=3, and Cload = 10, How can we find output pull down delay? If there is no sharing of S/D then the problem is simple C_n=(2+W)C delay = (R/W)(C_n) + (R/W + R/2)(C_load) but when we are sharing S/D ...
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Is "transition time" the same as "contamination delay"? If not, what is equivalent to \$t_{cd}\$ in the datasheets?

In the CD4013B datasheet the following timing table (excluding clock related values) can be found: According to the answer to this question, the contamination delay would be the minimum propagation ...
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2 answers
116 views

Why does my counter appear to work if it fails timing closure?

I configured my FPGA (Artix-7, -1 speed grade) to run a clock at higher speeds than it is designed for (464MHz). Naturally, I received the below egregious timing errors when implementing a 12-bit ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ

I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
2 votes
1 answer
500 views

How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are &...
0 votes
2 answers
266 views

Metastability in 3 or 2 flop synchronizer if input is valid for at least 2 clocks

In this image: Figure 1: metastability in 2 or 3 flop synchronizer If the metastability of first flop doesn't get resolved in 4th clock, is it possible that it may get resolved to '0' in 5th clock? ...
1 vote
2 answers
222 views

Do more logic gates in series mean more slowing of the output result?

I heard that every logic gate has a propagation delay in nano scale. As the digital signal propagates through the logic gates, the signal output result will have a delay. Even though the delay is so ...
4 votes
3 answers
588 views

Propagation and contamination delays with different delays for rising and falling edges

In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way: The propagation delay \$t_{...
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1 answer
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
2 votes
1 answer
109 views

Different output delays for internal to output and input to output path

I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY. The timing constraints from internal ...
0 votes
1 answer
264 views

Cyclone V data corruption at high frequency

I'm currently trying to implement a FPGA design using a 325 MHz clock, which writes to the SDRAM Controller of a Cyclone V 5CSEBA6U23I7 (Speed Grade 7). When running my IP Core with 2 MHz everything ...
10 votes
5 answers
3k views

Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns....
2 votes
1 answer
309 views

How to calculate overall average propagation delay for digital circuit given

Using the circuit shown with 3 inputs {A,B,C}, and outputs {F1,F2,F3}, and using the average propagation shown below for each gate: AND -> tpd = 9ns, XOR -> tpd = 8ns, OR -> tpd = 10ns ...
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1 answer
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Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
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Counting no. of clock cycles

This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space. Is there ...
3 votes
1 answer
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Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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1 answer
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Calculating how long it takes for a circuit to compute the output for a given set of inputs

I'm having trouble with analyzing a circuit with respect to time, given clock-to-q, setup, and delays of individual components. We are given that \$t_{clk-to-q} = 3ps\$ \$t_{setup}=4\$ \$t_{shifter}=...
0 votes
1 answer
786 views

Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...