Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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Fixing Setup and hold timing violations in FPGA's and ASIC designs

I have basic knowledge in static timing analysis. I understand concepts about setup and hold time of bistables and that failure to meet these two timing constraints can lead to metastability where ...
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1answer
1k views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
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2answers
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Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
3
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1answer
5k views

Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...