Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

30 questions with no upvoted or accepted answers
Filter by
Sorted by
Tagged with
5 votes
2 answers
4k views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
fhw72's user avatar
  • 151
4 votes
0 answers
1k views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
mkrieger1's user avatar
  • 143
2 votes
0 answers
305 views

How does the loopback on a non-retriggerable monostable work?

I understand how to connect a monstable multivibrator to be in the non-retriggerable mode. Just loopback the /Q to the falling edge input or the Q to the rising edge output) as in the following ...
Francis Poirier's user avatar
2 votes
2 answers
298 views

MT9M001 to FPGA input timing

MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The ...
Adam Trhon's user avatar
1 vote
0 answers
77 views

Timing constraints for external ADC for clock generated by FPGA

I am using an FPGA to generate a 100 MHz clock to an external 8-bit ADC. The external ADC is the ADC08100 and the valid sample window is -1.5ns to 4.4ns in regards to the rising edge of the clock. I ...
Ricardo Falcão's user avatar
1 vote
1 answer
133 views

Frequency of a sequential circuit

I'm reading the book Digital Design and Computer Architecture. I came across this exercise: From what I've learned so far, the frequency of a circuit is the reciprocal of the clock period. Since we ...
G. Ajello's user avatar
1 vote
0 answers
242 views

Lattice iCECube2 cannot find clock in .sdc file

I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock. How do I specify the .sdc file to see the output of baudgeninst, ...
Sonicsmooth's user avatar
1 vote
1 answer
1k views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
Nazar's user avatar
  • 3,172
1 vote
0 answers
78 views

Relationship between clock skew (For Reg-Reg path) and minimum clock pulse width requirement for capture Flop

I am hoping if some expert in timing analysis could answer on this topic. Here is the question: I am creating a liberty timing file for an IP block using ETM (Extracted Timing Model) method. ...
ECEVLSI's user avatar
  • 29
1 vote
0 answers
122 views

Data path in logic circuit

In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3? Thanks.
user138602's user avatar
1 vote
0 answers
415 views

Vivado timing constraints wizard

I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock. A defined INCLK TXCLK and clk_sys as primary clocks in ...
the dude's user avatar
  • 119
1 vote
1 answer
275 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
Jerrin George Mathew's user avatar
1 vote
0 answers
229 views

Timing Analysis of Asynchronous Interface

I have performed timing analysis for synchronous interfaces using clock signal. But how do we do timing of asynchronous interfaces where there is no clock?? To be precise, I am using P2020 from NXP &...
Oshi's user avatar
  • 591
1 vote
0 answers
841 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
burnpanck's user avatar
  • 133
1 vote
0 answers
1k views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be through ...
user872342's user avatar
0 votes
0 answers
41 views

How to set I/O constraints when the device is clocked by the FPGA

What is the proper way of setting I/O constraints when the device is clocked by the FPGA? As an example schematic is given below: The ADC is clocked from the FPGA. I have generated_clock constraints ...
Ras's user avatar
  • 1
0 votes
0 answers
53 views

Calculating timing constraings for interfacing with sdram

I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them. My understanding so far: To calculate the set_output_delay ...
TimSch's user avatar
  • 209
0 votes
0 answers
53 views

Timings constraints when interfacing an external ADC with an FPGA

I am currently using a Trion T8 FPGA to receive and store data from an external ADC, the ADC08100. The FPGA uses the internal PLL to generate a 100 MHz (10 ns period) clock signal, and its logic runs ...
Ricardo Falcão's user avatar
0 votes
0 answers
199 views

How to write I2C protocol timing constraints?

How do you normally write clock timing cons for I2C? Assuming 1 SDA line, 1 SCL line, 1 APB reference CLK called PCLK. Q. What are the relation of PCLK to SCL in this protocol? Does it matter if it is ...
vaibhav sharma's user avatar
0 votes
0 answers
206 views

Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ

I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
Berkaj's user avatar
  • 1
0 votes
0 answers
116 views

Counting no. of clock cycles

This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space. Is there ...
MAJID AHMAD's user avatar
0 votes
1 answer
257 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
Prasanna Shanbhogue's user avatar
0 votes
0 answers
40 views

FPGA Timing Constraint for 2 Combinational paths to take the same time

I am trying to do a simple asynchronous FPGA design where I have 2 inputs and 2 outputs, and assign the outputs to the inputs. I need the delay of both assign's to be near identical. What timing ...
Eric Johnson's user avatar
0 votes
1 answer
156 views

EEPROM 25LC1024 issue with PIC32MX OLIMEX board

I am trying to read the status register for the EEPROM following the instructions in this Application Note. I wanted to have the opinion of the community on the signals I am getting. They don't seem ...
Mehdi Sabwat's user avatar
0 votes
1 answer
77 views

Is post fit simulation using timing netlists necessary although design meets setup-hold time requirements?

In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are ...
quantum231's user avatar
  • 11.8k
0 votes
0 answers
65 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
drC1Ron's user avatar
  • 125
0 votes
0 answers
77 views

Max10 LVCMOS input setup and hold timing

I am struggling to find the minimum setup and hold timings for single-ended 3.3V LVCMOS inputs in the datasheet. I'm especially puzzled that the datasheet and handbook differentiate between low-speed ...
Arne's user avatar
  • 1,825
0 votes
0 answers
572 views

Mealy vs. Moore implications for timing closure

I am developing a pipeline block for inclusion in an ASIC. I want to decide between designing the block as a Mealy machine or as a Moore machine. Does this choice have implications for timing ...
Brent Bradburn's user avatar
0 votes
1 answer
839 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
Curiosity's user avatar
  • 171
-2 votes
1 answer
568 views

STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and ...
kevin's user avatar
  • 497