Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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566 views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
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530 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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Relationship between clock skew (For Reg-Reg path) and minimum clock pulse width requirement for capture Flop

I am hoping if some expert in timing analysis could answer on this topic. Here is the question: I am creating a liberty timing file for an IP block using ETM (Extracted Timing Model) method. ...
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Data path in logic circuit

In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3? Thanks.
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113 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
142 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
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293 views

Vivado timing constraints wizard

I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock. A defined INCLK TXCLK and clk_sys as primary clocks in ...
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1answer
69 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
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177 views

Timing Analysis of Asynchronous Interface

I have performed timing analysis for synchronous interfaces using clock signal. But how do we do timing of asynchronous interfaces where there is no clock?? To be precise, I am using P2020 from NXP &...
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347 views

Mealy vs. Moore implications for timing closure

I am developing a pipeline block for inclusion in an ASIC. I want to decide between designing the block as a Mealy machine or as a Moore machine. Does this choice have implications for timing ...
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701 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
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1k views

STM32 FSMC Timing Computation

I'm working on FSMC protocol of STM32 micro controller The formula for calculate FSMC timing is below, but I have a hard time understanding it. From ST Application Note Can someone walk be through ...
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How to calculate BER and sweep time from eye diagram?

I am iterating the SI simulation for the traces of the USB and LPDDR3 interfaces with processor. Is there any method to calculate the BER and sweep values from the eye diagram?
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36 views

FPGA Timing Constraint for 2 Combinational paths to take the same time

I am trying to do a simple asynchronous FPGA design where I have 2 inputs and 2 outputs, and assign the outputs to the inputs. I need the delay of both assign's to be near identical. What timing ...
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23 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
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28 views

Synopsys Technology File (STF)

I am using a memory IP block from STM. The manuals of the memory IP has talked a lot about Synopsys Technology File (STF), though, with no info on how and where to use it. Among all files related to ...
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137 views

Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
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doubt regarding max/min value of clock skew component in setup time equation

Kindly help me to out with the following questions asked in a recent interview: Theoretical Max and min value of clk skew in the equation of the setup time? Practical Max and min value of clk skew ...
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1answer
62 views

EEPROM 25LC1024 issue with PIC32MX OLIMEX board

I am trying to read the status register for the EEPROM following the instructions in this Application Note. I wanted to have the opinion of the community on the signals I am getting. They don't seem ...
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1answer
33 views

Is post fit simulation using timing netlists necessary although design meets setup-hold time requirements?

In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are ...
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How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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223 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
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560 views

Drawing a timing diagram for a circuit showing X, Y, and Z. What is Z doing?

I'm looking over the following question: I have the answer, and for the most part, I think I understand the logic: y = z' and z = xy. There's a 15ns delay (10 from the AND gate and 5 from the ...
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What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
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Max10 LVCMOS input setup and hold timing

I am struggling to find the minimum setup and hold timings for single-ended 3.3V LVCMOS inputs in the datasheet. I'm especially puzzled that the datasheet and handbook differentiate between low-speed ...
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124 views

Setup and Hold Time: A general method to find whether a block satisfies the constraints

How to determine whether setup and hold time constrains are satisfied in a digital block? I encountered a question on the same, and it would be really helpful to know a general way to determine the ...
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Syncronized reset timing (vivado)?

I have reset synchronizer in my top block (attached file). In my project I have blocks which get 125_clk, and others 250_clk. In addition I have srstn_sm block which its output is input for srstn ...