Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns....
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Ghosting in VGA signal generation

So, I'm generating a 1280x1024 (native screen resolution) VGA signal using a Lattice HX8K > Yosys, according to these timings, and a PLL of 107.812Mhz of Pixel Frequency. I then pass it through a ...
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Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.) I tried to analyze their behaviors at the clock edges. For D flip-flop 1,...
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Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...
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Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
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Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
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How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
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Synchronize Outputs of Separate FPGAs Within 1ns

Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution. I'm trying to ...
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Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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Attack and Release times of the Automatic Gain Control

What is Attack and Release times of the AGC? I couldn't find any understandable pdf on this.
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Help understanding practical transistor considerations?

So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance. It seems like everything I've been taught so far in classes about transistors ...
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Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
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Fixing Setup and hold timing violations in FPGA's and ASIC designs

I have basic knowledge in static timing analysis. I understand concepts about setup and hold time of bistables and that failure to meet these two timing constraints can lead to metastability where ...
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Propagation and contamination delays with different delays for rising and falling edges

In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way: The propagation delay \$t_{...
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Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
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How to properly implement an n-FF synchronizer in Lattice FPGAs?

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
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Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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Constraining combinatorial path delays in Intel Cyclone-V FPGA

I am working on a design with a Cyclone-V FPGA. I have a PLL that generates 4 clocks of equal frequency but with 90 degree phase shift from eachother. 4 DFFs running on each of these respective ...
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Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
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Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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3 votes
1 answer
592 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...
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1 answer
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Encounter: Hold time violation on clkgate

I'm trying to get rid of a clkgate timing violation. I have two of them and those are really big violations as you can see in this report: ...
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Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
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1 answer
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What will be the real voltage along the line with a voltage source and a capacitor?

Take the following circuit: If I do a simulation of this circuit I get this graph: The strange thing is that in the simulator it gives the same voltage sine wave in the circuit, near the voltage ...
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2 answers
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Variation in Tphl of MOS nand gate due to input patterns

I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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1 answer
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?

In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper ...
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2 answers
556 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
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2 votes
1 answer
651 views

SDC Constraint for reset synchronizer

I have a reset bridge in VHDL which is based on a multi-FF synchronizer chain as depicted below. This reset bridge is used in various instances throughout my design. I want to properly constrain the ...
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2 votes
2 answers
690 views

D-Flip-Flop Hold and Setup Timing Requirements

Update: The answer is 28ns for sure Giving the following circuit and timing table: Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
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3 answers
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Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
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2 votes
4 answers
592 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
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1 answer
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Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
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2 votes
1 answer
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Xilinx FPGA Input data timing constraint

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral. From FPGA to the peripheral, I have these SPI related signals: spi clk spi data (mosi) - ...
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2 votes
2 answers
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Why is a reset with asynchronous assert safe?

As far as I understand, a reset with asynchronous assert, synchronous de-assert is considered absolutely safe. I understand that this prevents metastability at the output of a flip-flop using that ...
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1 answer
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create_generated_clock quartus for derived clock

I am working in a design that creates a 1Hz clock from 20MHz PLL out. For that purpose, I have created a counter that switches its out when its value arrives to 10 000 000. That 1Hz clock is used as ...
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2 votes
1 answer
223 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
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Different output delays for internal to output and input to output path

I am trying to get correct timing constraints for a ULPI interface, where the PHY is an external chip and the link is an FPGA. The clock is generated by the PHY. The timing constraints from internal ...
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2 votes
2 answers
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How to calculate latency of a circuit?

Lets say we have this circuit: tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns First I want to check this circuit for hold-...
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3 answers
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Line Decoder Logic Race

I have a problem with this logic circuit I have designed: The intended behaviour is: when the clock comes high, the counter's state is latched and decoded What happens is: when the clock is high, ...
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2 votes
2 answers
4k views

FPGA SDC timing constraints, understanding output delay

I'm having a little bit of trouble understanding the timing convention of an SDC command: ...
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2 votes
1 answer
752 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
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