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Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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680 views

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...
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4answers
4k views

What is a ripple clock?

I am reading Chapter 12. Recommended Design Practices from the Quartus II Handbook Version 13.1 Volume 1: Design and Synthesis which states (p. 8): Ripple counters use cascaded registers, in which ...
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3answers
4k views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
5
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2answers
778 views

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
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2answers
188 views

Synchronize Outputs of Separate FPGAs Within 1ns

Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution. I'm trying to ...
5
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1answer
1k views

Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are ...
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2answers
1k views

Attack and Release times of the Automatic Gain Control

What is Attack and Release times of the AGC? I couldn't find any understandable pdf on this.
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3answers
240 views

Help understanding practical transistor considerations?

So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance. It seems like everything I've been taught so far in classes about transistors ...
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2answers
5k views

How to analyse timing report for Xilinx FPGA

I'm trying to learn FPGA programming, my test project is a 5 stage pipelined MIPS CPU, which works. Up until now I have been optimising for area utilisation, however this has caused a very slow clock ...
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3answers
205 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
4
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2answers
892 views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
4
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1answer
400 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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3answers
157 views

Line Decoder Logic Race

I have a problem with this logic circuit I have designed: The intended behaviour is: when the clock comes high, the counter's state is latched and decoded What happens is: when the clock is high, ...
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1answer
590 views

Encounter: Hold time violation on clkgate

I'm trying to get rid of a clkgate timing violation. I have two of them and those are really big violations as you can see in this report: ...
3
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1answer
996 views

Advantage of clock enable over clock division

I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
3
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1answer
592 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
3
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1answer
94 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
3
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1answer
440 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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2answers
1k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
3
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1answer
5k views

Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these ...
3
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1answer
151 views

MT9M001 to FPGA input timing

MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The ...
3
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2answers
1k views

FPGA SDC timing constraints, understanding output delay

I'm having a little bit of trouble understanding the timing convention of an SDC command: ...
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2answers
2k views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
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0answers
534 views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
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2answers
396 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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2answers
22k views

Fixing Setup and hold timing violations in FPGA's and ASIC designs

I have basic knowledge in static timing analysis. I understand concepts about setup and hold time of bistables and that failure to meet these two timing constraints can lead to metastability where ...
2
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2answers
135 views

How do you determine if a chip has either hold or setup violation after it has been manufactured?

Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
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3answers
257 views

Using register retiming to pipeline a module

From my reading I understand that modern synthesis tools are able to perform register retiming where registers are moved between combinational logic to meet timing constraints. So for example in your ...
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3answers
136 views

Multiple Reset Synchronization

I have two active low async resets (rst_na and rst_nb) and associated two clocks (clk_a and clk_b). Assume Block B required ...
2
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4answers
197 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
2
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1answer
491 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
2
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1answer
826 views

Xilinx FPGA Input data timing constraint

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral. From FPGA to the peripheral, I have these SPI related signals: spi clk spi data (mosi) - ...
2
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1answer
900 views

how to get the timing report register to register and input to output in STA?

I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths. Input to register Register to register Register to output Input to output Practically, I want to ...
2
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2answers
606 views

How to calculate latency of a circuit?

Lets say we have this circuit: tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns First I want to check this circuit for hold-...
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1answer
44 views

Typical PVT deratings?

I have an FPGA design that works ok in the lab, but timing analysis warns of some serious negative setup slack at worst case temperature and voltage. I'm curious, what might the derating be? It's ...
2
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1answer
1k views

Why won't the Xilinx block RAM in a Spartan-3E consistently return data in a single clock cycle?

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as ...
2
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1answer
605 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
2
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1answer
345 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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2answers
450 views

How do I delay MOSFET turn on without slowing down the rise time?

In a Half bridge MOSFET switching circuit, in order to prevent a "short" circuit through the high and low sides, I need to delay the turn on of the high/Low side until the Low/High side has turned off....
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1answer
1k views

TimeQuest Timing Analyzer: What is the difference between post fit and post map timing netlists?

When we wish to add timing constraints to our design in TimeQuest Timing Analyzer, we have two options. We can use either a post fit netlist or post map netlist. Post map netlist is available after ...
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2answers
237 views

Typical vs. min/max timing and voltages

I'm currently reading through the datasheet for the 74HC165 8-bit asynchronous parallel-to-serial shift register, and I've a handful of questions about the static and dynamic characteristics described ...
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3answers
90 views

Timing warnings for functional model

I am writing a controller for a low power/mobile DDR module on my FPGA. To allow debugging, I use a functional model written in Verilog. In it, the setup and hold time for some signal is set to 1.5 ns....
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1answer
3k views

What is the difference between worst hold slack and worst negative slack

I have been looking all over google and I can't find a clear answer for what is the difference between worst hold slack and worst negative slack in the timing summary in vivado. Right now I am ...
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1answer
313 views

Constraining synchronous clocks at different frequencies in VHDL

I have a design with a FPGA, a MCU, and other external peripherals connected together over a parallel peripheral bus. The whole system is clocked from two synchronous clocks. The clocks are a 32 Mhz ...
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1answer
221 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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1answer
114 views

AD7928 timing diagram question

I am working with an AD7928 (datasheet) and I am a bit confused by the timing diagram (page 25). I would expect to get my first bit off data from DOUT (ADD2) some time after the first falling edge of ...
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2answers
261 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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1answer
63 views

What does a double edge in a timing diagram indicate?

See the WE signal in the image below.
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1answer
110 views

SDRAM timing confusion

I'm looking at this data sheet: T67M-512Mb-Mobile-Lpddr-Sdram (targeting speed grade -75) and trying to understand the timing requirements for performing a read, specifically when to sample the DQ ...
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1answer
726 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...