Questions tagged [timing-analysis]

Timing analysis is the process of determining whether a circuit will meet its timing requirements, given the characteristics of the components in it.

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907 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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1answer
87 views

EEPROM 25LC1024 issue with PIC32MX OLIMEX board

I am trying to read the status register for the EEPROM following the instructions in this Application Note. I wanted to have the opinion of the community on the signals I am getting. They don't seem ...
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2answers
914 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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3k views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
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1answer
408 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
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440 views

Temperature and Voltage variation affects on Metastability

Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
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1answer
50 views

Is post fit simulation using timing netlists necessary although design meets setup-hold time requirements?

In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are ...
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4answers
405 views

Generation of non overlapping clocks on FPGA using VHDL

I am trying to implement switched capacitor circuits and I hence need to generate a two-phase non-overlapping clock. I have been trying to use an FPGA for the same. Unfortunately, my synthesis tool- ...
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1answer
113 views

Thoughts on this circuit

Here I have a design ( Vcc = 12V ) where relay gets activated whenever reed switch gets closed. I want to activate the relay after a delay of about 2 to 3 seconds from the instant reed switch gets ...
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1answer
301 views

Best practice for synchronizing VHDL stimuli with circuit

What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL? I am currently running only behavioral simulations, but I want to make sure my ...
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3answers
922 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
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2answers
555 views

Edge aligned Source synchronous outputs

This is a basic block diagram of source synchronous interface I found in altera document. Here This is how edge aligned source synchronous output looks like. They say the reciever will shift the ...
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583 views

Non-optimal clock IOB/BUFGMUX placement correctable in software or hardware?

I am getting this nasty error when synthesizing my design using ISE Studio for Spartan-6: ...
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1answer
956 views

Use of clock in SDC style IO constraints for FPGAs

Question on use of clock in SDC style IO delay constraints The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
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345 views

Vivado timing constraints wizard

I have an FPGA design that uses 2 outside clocks (INCLK and TXCLK) from an ADC to latch data also coming from an ADC (TXOUT) and a system clock. A defined INCLK TXCLK and clk_sys as primary clocks in ...
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1answer
318 views

What are minimum requirements to start of with STA [closed]

What are the minimum requirements to start with static timing analysis. I know usage of FPGAs and VHDL. Will that be enough? Are there any free tools for STA pls.?
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1answer
505 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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2k views

How to calculate latency of a circuit?

Lets say we have this circuit: tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns First I want to check this circuit for hold-...
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6answers
242 views

FPGA: intentional delays through manual placement/routing

In my FPGA design, I have some input signals that need to be delayed considerably before they reach the first clocked register. There are delay elements near the pins for exactly that purpose, but ...
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2answers
3k views

how to get the timing report register to register and input to output in STA?

I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths. Input to register Register to register Register to output Input to output Practically, I want ...
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2answers
535 views

FPGA Internal Timing constraint failing

I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer. The Verilog code pasted below produces a timing problem, namely ...
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2answers
7k views

SR latch timing diagram or waveform with delay, help!

I'm having trouble solving these two problems (my solution and general solution showed): What I did was follow the truth table and based on the combination on the graph draw the appropriate state ...
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2answers
303 views

Synchronize Outputs of Separate FPGAs Within 1ns

Edit: I have been able to achieve 560ps uncertainty in simulation by using external PLL feedback through the entire chip. Once I verify in real hardware I will post a complete solution. I'm trying to ...
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1answer
515 views

Timing Constraints

I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
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1answer
109 views

Negative slack while designing a feedback controller using Xilinx System Generator

I'm transforming the design of a feedback controller(PI controller) which was already in Simulink, to FPGA using Xilinx System Generator. The main design problem i'm facing is the negative slack time....
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761 views

Drawing a timing diagram for a circuit showing X, Y, and Z. What is Z doing?

I'm looking over the following question: I have the answer, and for the most part, I think I understand the logic: y = z' and z = xy. There's a 15ns delay (10 from the AND gate and 5 from the ...
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47 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
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3answers
259 views

Help understanding practical transistor considerations?

So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance. It seems like everything I've been taught so far in classes about transistors ...
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2answers
612 views

Typical vs. min/max timing and voltages

I'm currently reading through the datasheet for the 74HC165 8-bit asynchronous parallel-to-serial shift register, and I've a handful of questions about the static and dynamic characteristics described ...
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1answer
430 views

Static Timing Analysis for I2C

Could Anybody help in getting started on I2C signal Static Timing Analysis. I just wanted to start with 1 single master slave combination. I have MPC8343EA as Master and TMP100 as slave. I know the ...
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0answers
199 views

Timing Analysis of Asynchronous Interface

I have performed timing analysis for synchronous interfaces using clock signal. But how do we do timing of asynchronous interfaces where there is no clock?? To be precise, I am using P2020 from NXP &...
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1answer
468 views

Constraining synchronous clocks at different frequencies in VHDL

I have a design with a FPGA, a MCU, and other external peripherals connected together over a parallel peripheral bus. The whole system is clocked from two synchronous clocks. The clocks are a 32 Mhz ...
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3answers
401 views

Using register retiming to pipeline a module

From my reading I understand that modern synthesis tools are able to perform register retiming where registers are moved between combinational logic to meet timing constraints. So for example in your ...
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1answer
72 views

What does a double edge in a timing diagram indicate?

See the WE signal in the image below.
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1answer
209 views

MT9M001 to FPGA input timing

MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The ...
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65 views

Max10 LVCMOS input setup and hold timing

I am struggling to find the minimum setup and hold timings for single-ended 3.3V LVCMOS inputs in the datasheet. I'm especially puzzled that the datasheet and handbook differentiate between low-speed ...
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2answers
791 views

How do I delay MOSFET turn on without slowing down the rise time?

In a Half bridge MOSFET switching circuit, in order to prevent a "short" circuit through the high and low sides, I need to delay the turn on of the high/Low side until the Low/High side has turned off....
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1answer
858 views

Why is de-assertion of an asychronous reset a problem compared to its assertion?

"The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the issue. If ...
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2answers
921 views

How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop?

Does the async. and sync. reset signal follow the setup and hold time conditions of flip flop? If so how would they affect the output?
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3answers
173 views

Line Decoder Logic Race

I have a problem with this logic circuit I have designed: The intended behaviour is: when the clock comes high, the counter's state is latched and decoded What happens is: when the clock is high, ...
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2answers
2k views

Attack and Release times of the Automatic Gain Control

What is Attack and Release times of the AGC? I couldn't find any understandable pdf on this.
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2answers
3k views

FPGA SDC timing constraints, understanding output delay

I'm having a little bit of trouble understanding the timing convention of an SDC command: ...
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1answer
122 views

SDRAM timing confusion

I'm looking at this data sheet: T67M-512Mb-Mobile-Lpddr-Sdram (targeting speed grade -75) and trying to understand the timing requirements for performing a read, specifically when to sample the DQ ...
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1answer
433 views

Should we use asynchronous inputs in Moore blocks and synchronous in Mealy blocks?

Consider we have two n-bit counters CNT_A and CNT_B two n-bit unsigned comparators CMP_A, CMP_B and two n-bit binary numbers N1, N2. The counters have two inputs C, L for synchronous count and load ...
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1answer
172 views

Reading timing diagram of MBI5168

I am studying this little IC called MBI5168. It is serial-to-parallel LED driver. I don't get why OUT0, OUT1, and OUT7 are ON, when the 8 bit data latched in SDI shows 10100011b. Shouldn't this yield ...
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1answer
897 views

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design ...
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2answers
8k views

JK flip-flop timing diagram positive edge triggering

Welcome I would like to ask you for explain this timing diagrams. I got some assignments for reading timing diagrams and solved it but I am not sure if it is good. I have JK flip-flop which is ...
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3answers
125 views

Timing warnings for functional model

I am writing a controller for a low power/mobile DDR module on my FPGA. To allow debugging, I use a functional model written in Verilog. In it, the setup and hold time for some signal is set to 1.5 ns....
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1answer
129 views

Is it a bad idea to switch from using a quartz oscillator for my timing circuit to using a MEMS oscillator? [closed]

I've read MEMS oscillators offer improved performance including phase jitter less than 500fs and frequency stability down to +-0.1ppm. It's difficult to switch from quartz because it simply works and ...
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2answers
293 views

Calculating resistance for 50% duty cycle

I am planning for simple standalone LED flashers to fill the ceiling of a room. Planning to fix at least 60 of these and they will be flashing randomly at about once a second. I'm using this circuit. ...