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Questions tagged [uvm]

Universal Verification Methodology

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The quality of testbenches with UVM testing

This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied. So I come from a hardware engineering background, as I was discussing how ...
Lannan Jiang's user avatar
1 vote
1 answer
59 views

How to connect multiple TLM ports to UVM Sequencer?

There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
TSyi's user avatar
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1 vote
1 answer
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How to bind a module in system verilog, with parameters not from the target location

I would like to bind a module, and pass a parameter from the module I declared the bind in, rather than them all coming from the module I am binding to. ...
ET_FPGA's user avatar
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1 vote
2 answers
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How to use "question mark" in start method of UVM?

I am trying to modify the existing code using the start() method in UVM. Basic code is below: ...
Carter's user avatar
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1 vote
3 answers
463 views

Problem overridding parametrized UVM objects

In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
أحمد المحمودي's user avatar
1 vote
1 answer
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How to sample the read data from blocking logic safely by using the interface of SystemVerilog?

I'm trying to read data from combinational logic. module my_reg(; ... output reg [31:0] rdata; ) .... always @(data) rdata = 32'h18; and this dut's value ...
Carter's user avatar
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0 votes
1 answer
251 views

How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer. The monitor message should only appear when a command(...
Carter's user avatar
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1 vote
1 answer
217 views

Issue of reset value assignment in the UVM register model

I came across a register model example as below. Register ureg1_t looks like: ...
Carter's user avatar
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0 votes
1 answer
118 views

Has the user's guide for the UVM-IEEE-2020 framework been published yet? [closed]

I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020. There are of course resources posted at the Accellera's ...
nanoeng's user avatar
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1 vote
1 answer
162 views

How do I implement an access of register if it has the multiple access options in UVM IP-XACT?

I'm trying to understand the IP-XACT User Guide schema for making the RAL model. Especially, if I have a register called DEV_STAT as below, I understood that ...
Carter's user avatar
  • 607
1 vote
1 answer
389 views

How to print uvm_tlm_analysis_fifo properties with `uvm_info() in UVM?

I'm stuck on the print properties of uvm_tlm_analysis_fifo handle with `uvm_info(). I made a simple sequence item as below. <...
Carter's user avatar
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1 vote
1 answer
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How to finish the forever statement on run_phase in UVM?

I'm trying to understand forever statement in raise_objection()/drop_objection(). I thought that the ...
Carter's user avatar
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1 vote
1 answer
499 views

Auto Prediction Register model update Issue in RAL

I'm trying to understand the auto prediction concept in UVM RAL model, and I came across the Auto Prediction Register model update Issue in https://youtu.be/hrxhUE_RHyY?t=145. But, I didn't understand ...
Carter's user avatar
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1 vote
1 answer
2k views

How to setup a Backdoor Access within UVM RAL model?

I'm trying to understand Backdoor Access within UVM RAL mode example https://www.edaplayground.com/x/jy3U . In uvm_guide, it wrote that if HDL paths are used, the root HDL paths must be specified in ...
Carter's user avatar
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2 votes
1 answer
672 views

What is the new constructor's argument rule in UVM?

I'm wondering why some new constructor has been implemented with argument and some new constructor has been implemented with no ...
Carter's user avatar
  • 607
0 votes
1 answer
197 views

What is exactly a transaction initiator and executor in UVM port and export?

Screenshot from this video. Whereas in UVM, sequencer has an import/export and driver has a port. Sequencer seems to be the transaction initiator and driver as the executor (as it is finally ...
lousycoder's user avatar
1 vote
1 answer
829 views

How to print a created handle information in UVM?

I create an object handle in UVM usually with new or create to allocate memory. Is there any possible way to print about ...
Carter's user avatar
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1 vote
1 answer
589 views

How to partial port connect by using interface bundle?

I'm trying to connect DUT's port list with interface by using bundling. The current problem is that the DUT was implemented with lots of ports. It's almost 1500 more. I want to connect a partial ...
Carter's user avatar
  • 607
2 votes
1 answer
2k views

How to connect multiple interfaces within DUT in UVM?

I have two interfaces: virtual intf vif; virtual i2c_intf i2c_vif; I need to connect them at my top level. Currently, I am connecting it like below: ...
Carter's user avatar
  • 607
1 vote
1 answer
441 views

How to start task in virtual sequence from testcase?

I'd like to execute a virtual sequence's task as below: ...
Carter's user avatar
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