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Questions tagged [verification]

Assurance of satisfiability of all the expected requirements in either software or hardware systems.

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Possible GND Conflicts in My PCB

I have the following schematic as the verification and validation setup for our DC-DC converter: The idea is that by using a DAC, we can manipulate the output voltage. We plan to send commands to the ...
Andromeda's user avatar
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How can a designer be sure to authorize only legit ICs? How is performed? How are cloned ICs prevented to be activated?

The above diagram is from the IC Activation (locking/unlocking) slide of Fighting against theft, cloning and counterfeiting of integrated circuits by Lilian Bossuet Associate Professor, CNRS Chaire of ...
allexj's user avatar
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The quality of testbenches with UVM testing

This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied. So I come from a hardware engineering background, as I was discussing how ...
Lannan Jiang's user avatar
1 vote
1 answer
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How to connect multiple TLM ports to UVM Sequencer?

There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
TSyi's user avatar
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2 answers
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ESD Workstations in Manufacturing Facility

I am a manufacturing engineer for a company that just inherited a large electrical build. I am struggling to find ESD information for multiple workbenches. This is my last resort so I am hoping you ...
MDD's user avatar
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2 answers
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Ascertaining that a BGA's decoupling capacitance is good enough

BGA parts often have a large number of power pins in the middle of the package. It is of course important to ensure that the power rail has been sufficiently capacitively decoupled. How can one go ...
Rob Gilton's user avatar
1 vote
1 answer
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Transformer Design for a Series Resonant Converter

I am determining the Area-Product of the core required for a transformer to be used within a series resonant converter. The specifications are as follows: Switching frequency = 400 kHz Primary ...
Jonathan_the_seagull's user avatar
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Current values verification check without ammeter [closed]

Given the following circuit with my current directions (the ones I highlighted with red): So \$ I = - 2 A, I' = -1.5 A, I_x = \frac{1}{2} A , I_y = -1.5A , V_x = -1.5 A \$ Is this valid?
HellBoy's user avatar
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How to use "question mark" in start method of UVM?

I am trying to modify the existing code using the start() method in UVM. Basic code is below: ...
Carter's user avatar
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2 votes
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Error while trying to bind SystemVerilog module with properties module

I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this: ...
Kyriafinis Vasilis's user avatar
1 vote
3 answers
500 views

Problem overridding parametrized UVM objects

In the following UVM testbench, I needed to make the sequence item, and hence the rest of the UVM components parametrized because the DUT is parametrized. I define 2 sequences: the base sequence '...
أحمد المحمودي's user avatar
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When using Cocotb, should I be using FallingEdge to set and assert values?

I'm attempting to use Cooctb to verify a simple Verilog counter with a reset: ...
Dave Dribin's user avatar
1 vote
1 answer
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Verification of asynchronous FIFO

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings. The goal is to verify this design by using the Tb components, so no UVM at all. I ...
Giuseppe Trematerra's user avatar
1 vote
1 answer
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Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
Giuseppe Trematerra's user avatar
-2 votes
1 answer
2k views

Sign Extension in Verilog [closed]

what is the difference between the following 3 sign extensions ...
Aren dg's user avatar
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Is there a tool or method to list signals that have no reset in the HDL design for an FPGA?

I have to reuse an old VHDL draft design which was not fully verified and validated. The code is huge - it takes around 30k slices to be implemented on an FPGA. I see that some signals are forgotten ...
dsp_curious's user avatar
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Has the user's guide for the UVM-IEEE-2020 framework been published yet? [closed]

I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020. There are of course resources posted at the Accellera's ...
nanoeng's user avatar
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Please help to verify my explanation for the amplitude and help to explain why the amplitude diminishes over time

I have the circuit below which consists of a series resistor followed by a parallel LC circuit: It produces this output waveform: From the simulation, I know the waveform has a frequency of 10Khz ...
chuackt's user avatar
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Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
gyuunyuu's user avatar
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2 votes
1 answer
403 views

Resources for learning Open Source VHDL Verification Methodology (OSVVM) [closed]

I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following: Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based ...
Arvind Gupta's user avatar
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1 answer
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How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
Taher Anaya's user avatar
7 votes
1 answer
679 views

Why is BMC/k-induction used in RTL formal verification?

One popular approach for proving safety properties in formal verification of RTL designs is a combination of BMC and \$k\$-induction, which appears to stem from "Checking safety properties using ...
ferris's user avatar
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-2 votes
1 answer
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Formal verification and verification jobs [closed]

Im an EE student (second year), and I wanted to ask about verificarion jobs. Does "Formal verification" is the same as just "verification" ? Could not find the diiference
FreeZe's user avatar
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Confusion regarding BJT voltage gain

I learnt from youtube the gain from this circuit is as below where it just take $$A_v=\frac{r_c}{r_e'}$$ while today I doing my revision encountered this question and the answer provided as above. ...
chuackt's user avatar
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1 vote
3 answers
67 views

How are system level test requiring use of common lab bench equipment usually implemented?

Assume that a system level test setup needs to be created for a design. This shall require use of power supply with multiple outputs, signal sources that can output sinusoidal or arbitrary signals and ...
quantum231's user avatar
1 vote
1 answer
140 views

Test bench when design is pipelined

I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
Diego Ruiz's user avatar
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1 answer
744 views

SystemVerilog Assertions syntax error unexpected |-> [closed]

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
a_bet's user avatar
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6 answers
469 views

Is it possible to "hash" a circuit board?

I'll preface this by saying I'm a software engineer by trade and have very little EE knowledge. In the software world, one can take all the bits that make up a file and generate a hash for a file. ...
Sordid Alith's user avatar
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2 answers
489 views

TIVA TM4C123G check clock frequency with oscilloscope

I'm trying to configure system clock in the TIVA TM4C123g board. I'm aware that this clock signal goes to a pin called OSC0 which, according to this, is the pin ...
Martel's user avatar
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6 votes
1 answer
1k views

How does a non-designer understand a chipset's functionality?

I once met a person who told me as a part of his work he was testing and characterizing analog chips which include all sorts of components like ADCs, DACs, regulators ect. embedded in one chip. But he ...
floppy380's user avatar
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2 votes
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Can you use an FPGA / verilog to accelerate SAT / SMT solving?

I am aware that SAT and SMT are widely used in hardware verification. This would tell me intuitively that trying every input on a circuit is slower than porting the circuit to a solver. However, we ...
douggard's user avatar
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2 votes
2 answers
233 views

How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format. signal a should never be 2 until it attains the value 1 How can we do that?
vineeshvs's user avatar
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1 answer
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Generating unique values for multiple cyclic random variables

In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possible values (due to a constraint). So, I expect to get ...
أحمد المحمودي's user avatar
2 votes
2 answers
88 views

Transaction randomization succeeds, yet values do not meet constraints

In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value. Please note that ...
أحمد المحمودي's user avatar
1 vote
1 answer
505 views

Failed to randomize dynamic array using foreach in constraint

In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction: ...
أحمد المحمودي's user avatar
2 votes
1 answer
110 views

Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...
gyuunyuu's user avatar
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0 votes
2 answers
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How to verify a VHDL I2C master?

Once an I2C master has been written, the next step is verification. Provided that a BFM for the slave does not exist, how should one go about doing this? Also seeing how I2C is open collector in ...
quantum231's user avatar
3 votes
1 answer
136 views

Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
Krunal Desai's user avatar
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0 votes
2 answers
201 views

What could be the output current rating of the following shunt regulator?

I am trying to solve the 2013 paper set by ISRO for electrical engineers. I wanted to verify if my answer to Question no 18 is correct. So \$I_L\$ is being drawn out of the circuit shown. Since the ...
Aditya P's user avatar
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1 answer
87 views

Looking for a short range detection and identification

I am currently building a smart cat door. One of its functionalities is that it keeps the door locked until our cat comes close to it, then it unlocks the door. I tried using RFID, the RC522 because ...
MrAbdul's user avatar
3 votes
3 answers
4k views

How to test a CPU watchdog on board?

The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span. I want to be sure, that it is enabled and ...
Jonas Stein's user avatar
0 votes
1 answer
323 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
pavan sp's user avatar
0 votes
1 answer
121 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
user2077648's user avatar
1 vote
1 answer
575 views

System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations

Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
Greyspectre's user avatar
-1 votes
1 answer
818 views

ASIC verification of a FIFO with "n" unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
Verif_engg's user avatar
5 votes
2 answers
2k views

What is formal verification of hardware?

I read that testing and verification are different but in what way? I read that somebody writes theory to prove that the hardware is "correct" but how is that done? I tried reading Wikipedia and ...
Niklas Rosencrantz's user avatar
0 votes
1 answer
8k views

How to measure time difference between 2 signal changes in verilog?

There are two signals sig, enable - and I wanted to find the time difference after which enable toggles after sig falls. ( >Sig Low to Enable toggle< time) I understand that always@() block can't ...
Ambareesh Sr Ja's user avatar
0 votes
1 answer
69 views

Verification of this CMOS realisation

I have to make the CMOS-equivalent of this function: \$A'*B'+C'\$. I made this CMOS-circuit, but I'm not sure if it's correct: simulate this circuit – Schematic created using CircuitLab The ...
Pieter Verschaffelt's user avatar
6 votes
2 answers
1k views

Is there a "standard" way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
quantum231's user avatar
3 votes
0 answers
176 views

How can a IC (or transistors or diodes) design make it difficult for a malicious manufacturer to subvert it undetected? [closed]

Introduction This is a spin of from my question on security.se. To give more context: If I have a threat model where the adversary wants to corrupt computation or steal information ...
Gabriel Schulz's user avatar