Questions tagged [verification]

Assurance of satisfiability of all the expected requirements in either software or hardware systems.

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FPGA prototyping vs Formal Verification

FPGAs are used to prototype and test hardware architectures before ASICs are fabricated. Formal verification can also be used to verify the correctness of an RTL architecture or a netlist. Does this ...
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Has the user's guide for the UVM-ieee-2020 framework been published yet? [closed]

I was able to find the User's guide for the UVM-1.1 and UVM-1.2 frameworks, but I haven't been able to find the same document for UVM-IEEE-2020. There are of course resources posted at the Accellera's ...
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Please help to verify my explanation for the amplitude and help to explain why the amplitude diminishes over time

I have the circuit below which consists of a series resistor followed by a parallel LC circuit: It produces this output waveform: From the simulation, I know the waveform has a frequency of 10Khz ...
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Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
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Resources for learning Open Source VHDL Verification Methodology (OSVVM) [closed]

I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following: Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based ...
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How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
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7 votes
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Why is BMC/k-induction used in RTL formal verification?

One popular approach for proving safety properties in formal verification of RTL designs is a combination of BMC and \$k\$-induction, which appears to stem from "Checking safety properties using ...
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Formal verification and verification jobs [closed]

Im an EE student (second year), and I wanted to ask about verificarion jobs. Does "Formal verification" is the same as just "verification" ? Could not find the diiference
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Confusion regarding BJT voltage gain

I learnt from youtube the gain from this circuit is as below where it just take $$A_v=\frac{r_c}{r_e'}$$ while today I doing my revision encountered this question and the answer provided as above. ...
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How are system level test requiring use of common lab bench equipment usually implemented?

Assume that a system level test setup needs to be created for a design. This shall require use of power supply with multiple outputs, signal sources that can output sinusoidal or arbitrary signals and ...
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Test bench when design is pipelined

I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
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SystemVerilog Assertions syntax error unexpected |-> [closed]

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
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Is it possible to "hash" a circuit board?

I'll preface this by saying I'm a software engineer by trade and have very little EE knowledge. In the software world, one can take all the bits that make up a file and generate a hash for a file. ...
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TIVA TM4C123G check clock frequency with oscilloscope

I'm trying to configure system clock in the TIVA TM4C123g board. I'm aware that this clock signal goes to a pin called OSC0 which, according to this, is the pin ...
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How does a non-designer understand a chipset's functionality?

I once met a person who told me as a part of his work he was testing and characterizing analog chips which include all sorts of components like ADCs, DACs, regulators ect. embedded in one chip. But he ...
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Can you use an FPGA / verilog to accelerate SAT / SMT solving?

I am aware that SAT and SMT are widely used in hardware verification. This would tell me intuitively that trying every input on a circuit is slower than porting the circuit to a solver. However, we ...
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How to write 'a signal should never have certain value before it attains some other value' in SystemVerilog assertion?

I would like to write the following in SVA (SystemVerilog Assertion) format. signal a should never be 2 until it attains the value 1 How can we do that?
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Generating unique values for multiple cyclic random variables

In the following code, I have 2 cyclic random variables in a class. One (an enumerated type) takes 3 possible values, and the other takes 288 possibles values (due to a constraint). So, I expect to ...
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Transaction randomization succeeds, yet values do not meet constraints

In the following code, I attempt to randomize the transaction which contains a dynamic array 'PhyRB', with the constraint that each element in the array is less than 'ResBlks' value, please note that ...
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Failed to randomize dynamic array using foreach in constraint

In the following code, I force a random variable 'ResBlks' with a value (setting its rand_mode to 0), then attempt to randomize the transaction: ...
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2 votes
1 answer
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Verifying custom Qsys component?

A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also. These copies ...
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How to verify a VHDL I2C master?

Once an I2C master has been written, the next step is verification. Provided that a BFM for the slave does not exist, how should one go about doing this? Also seeing how I2C is open collector in ...
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3 votes
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Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
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What could be the output current rating of the following shunt regulator?

I am trying to solve the 2013 paper set by ISRO for electrical engineers. I wanted to verify if my answer to Question no 18 is correct. So \$I_L\$ is being drawn out of the circuit shown. Since the ...
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Looking for a short range detection and identification

I am currently building a smart cat door. One of its functionalities is that it keeps the door locked until our cat comes close to it, then it unlocks the door. I tried using RFID, the RC522 because ...
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3 answers
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How to test a CPU watchdog on board?

The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span. I want to be sure, that it is enabled and ...
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If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
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Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1 vote
1 answer
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System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations

Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
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-1 votes
1 answer
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ASIC verification of a FIFO with "n" unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
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4 votes
2 answers
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What is formal verification of hardware?

I read that testing and verification are different but in what way? I read that somebody writes theory to prove that the hardware is "correct" but how is that done? I tried reading Wikipedia and ...
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How to measure time difference between 2 signal changes in verilog?

There are two signals sig, enable - and I wanted to find the time difference after which enable toggles after sig falls. ( >Sig Low to Enable toggle< time) I understand that always@() block can't ...
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Verification of this CMOS realisation

I have to make the CMOS-equivalent of this function: \$A'*B'+C'\$. I made this CMOS-circuit, but I'm not sure if it's correct: simulate this circuit – Schematic created using CircuitLab The ...
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5 votes
2 answers
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Is there a "standard" way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
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3 votes
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How can a IC (or transistors or diodes) design make it difficult for a malicious manufacturer to subvert it undetected? [closed]

Introduction This is a spin of from my question on security.se. To give more context: If I have a threat model where the adversary wants to corrupt computation or steal information ...
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2 answers
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Some general question on verification from scratch

I'm not a huge expert on hardware verification, I mean I know what the purpose of verification is (basically check if the system what it is expected to do) and I've used some tools for verification, ...
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1 vote
1 answer
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What are the typical tasks of a Design Verification Engineer? [closed]

I'm quite confused on what should be the typical tasks of a Design Verification Engineer in ASIC Design. In my experience these were the things that I do: Create verification plan Create testbench ...
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Can the machine readable files for integrated circuits be verified by the manufacturer design team?

My question is simple if you take the chip design files (blue print files for the fabrication process) which are used by the fabrication process that the design engineer(s) have completed the files ...
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Is sytem level testcase different from block level testcase? And what is a test vector?

I usually see these terms. In the field of Digital IC Design or in Design Verification, is system level testcase different from a block level testcase? I mean I know they differ from the level of ...
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0 votes
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What does this sentence mean in this question (simulator can handle X inputs)?

In my book, one question requires me to find the verification sequence for a circuit. From what I understand, verification sequence must be such that every path is traversed. Then the book ...
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How can a manufacturer verify a circuit design? [closed]

Could anyone tell me what means (other than reversing) available to manufacturer of integrated circuits (latest Intel PC CPU's) that would allow them to verify that the actual design on die is ...
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How do you check your schematic before passing to layout [closed]

I am working with Altium. What verification do you particularly do when going from schematic to layout in terms of electronic and in terms of capture ?
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6 votes
3 answers
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Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
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19 votes
4 answers
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Electronics System Standards Compliance: Certification, Testing & Verification

Please note: this question has to do with the technical compliance aspects of the consumer electronics indsutry, and as such, I believe is within scope for this site. This question is about compliance,...
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Thevenin equivalent (verification of answer)

\$ R_{TH} = R1 + R2//R5 + R3//R4\$ Then considering the current source and the resistance R3 as a Norton circuit, one can convert it to Thevenin as follows \$V_I = -IR3\$. Then we have the voltage ...
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Power calculation of circuits

Please read on..... this looks long but is entry level and easy I have done many simple projects based on microcontrollers but have not considered power and required current(for circuit to work) ...
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4 votes
2 answers
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Circuit Testing, Verification & Certification Standards for Biomedical Devices

Please note: I would have posted this question on HealthIT.SE but they are apparently now closed for business, and I believe this site is the next most appropriate place to ask this. I believe this ...
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3 votes
1 answer
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Modelsim - Weird verification problem with DDR and Xilinx UNISIM

I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
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6 votes
3 answers
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EMC testing vs. EMI testing

What is the difference between EMC testing (Electromagnetic compatibility) and EMI testing (Electromagnetic interference)
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1 answer
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Verifying a Meier Crossfeed Build

I've built a "Bass Enhanced Crossfeed" from a kit, which I believe is based on Meier's Crossfeed design. I prototyped it first on a breadboard, forgot to ground the output jack because it wasn't ...
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