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Questions tagged [verification]

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26 views

Is it possible to assign a value to a signal in a systemverilog assertion? [on hold]

I have two sequences, s1 and s2. I have a property that checks these two sequences. for example, ...
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2answers
80 views

How to verify a VHDL I2C master?

Once an I2C master has been written, the next step is verification. Provided that a BFM for the slave does not exist, how should one go about doing this? Also seeing how I2C is open collector in ...
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1answer
46 views

Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
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0answers
22 views

Eagle PCB GND planes not show after ratsnest command

I poured my polygons on both TOP and BOTTOM layers ,but after i name them and click ratsnest the GND planes don't show up. The autorouter didn't want to route as it was stuck at 00.0% and finished ...
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2answers
46 views

What could be the output current rating of the following shunt regulator?

I am trying to solve the 2013 paper set by ISRO for electrical engineers. I wanted to verify if my answer to Question no 18 is correct. So \$I_L\$ is being drawn out of the circuit shown. Since the ...
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1answer
44 views

Looking for a short range detection and identification

I am currently building a smart cat door. One of its functionalities is that it keeps the door locked until our cat comes close to it, then it unlocks the door. I tried using RFID, the RC522 because ...
0
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0answers
42 views

How to verify a complete BOM complies a temp range?

I' verifying a board, which has about 300 components, and I would like to verify if all components comply with the -25° to 70° temp range. its a very time consuming task. I tried importing the BOM ...
3
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2answers
444 views

How to test a CPU watchdog on board?

The watchdog of an ATMEL ATXMega128 should have been enabled with fuses. It triggers a reset, if the timer was not reset within the configured time span. I want to be sure, that it is enabled and ...
0
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1answer
47 views

If constraints in SystemVerilog

I have a class of sequence item with rand variables: class my_seq_item extends uvm_sequence_item; rand bit a, b, c, d; I want to generate a random bit for 'd' ...
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0answers
61 views

How do I pre-tune and verify a receiver frontend?

In the design and implementation of an RF receiver, I'd like to build and verify it stage by stage, with particular attention to impedance matching, noise figure and gain. If I had access to a ...
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0answers
35 views

Need help verifying this design that transmits light signal via op-amps and diff amps

I designed a system where a light signal is detected by a photo detector and transmitted over a PCB to a microprocessor. The photo detector had an internal resistance of 1KΩ and could at most generate ...
0
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1answer
31 views

Fault modelling stuck at fault for combinational circuit

A circuit has n inputs and n outputs. It is implemented only using AND, OR and NOT gates. Further, there are no fan-out branches. What is the number of s-a faults that remain after fault collapsing? ...
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1answer
271 views

System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations

Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
0
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1answer
489 views

ASIC verification of a FIFO with “n” unique items

simulate this circuit – Schematic created using CircuitLab I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" ...
0
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1answer
425 views

What is “formal verification” of hardware?

I read that testing and verification are different but in what way? I read that somebody writes theory to prove that the hardware is "correct" but how is that done? I tried reading Wikipedia and ...
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1answer
2k views

How to measure time difference between 2 signal changes in verilog?

There are two signals sig, enable - and I wanted to find the time difference after which enable toggles after sig falls. ( >Sig Low to Enable toggle< time) I understand that always@() block can't ...
0
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1answer
51 views

Verification of this CMOS realisation

I have to make the CMOS-equivalent of this function: \$A'*B'+C'\$. I made this CMOS-circuit, but I'm not sure if it's correct: simulate this circuit – Schematic created using CircuitLab The ...
2
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1answer
200 views

Is there a “standard” way to verify HDL of a state machine?

State machines are a pattern that is used very often in writing synchronous designs. They serve as the controllers in the design. So, is there a standard way to verify them if they are written using ...
3
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0answers
169 views

How can a IC (or transistors or diodes) design make it difficult for a malicious manufacturer to subvert it undetected? [closed]

Introduction This is a spin of from my question on security.se. To give more context: If I have a threat model where the adversary wants to corrupt computation or steal information ...
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2answers
51 views

Some general question on verification from scratch

I'm not a huge expert on hardware verification, I mean I know what the purpose of verification is (basically check if the system what it is expected to do) and I've used some tools for verification, ...
1
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1answer
249 views

What are the typical tasks of a Design Verification Engineer? [closed]

I'm quite confused on what should be the typical tasks of a Design Verification Engineer in ASIC Design. In my experience these were the things that I do: Create verification plan Create testbench ...
0
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1answer
36 views

Can the machine readable files for integrated circuits be verified by the manufacturer design team?

My question is simple if you take the chip design files (blue print files for the fabrication process) which are used by the fabrication process that the design engineer(s) have completed the files ...
2
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1answer
32 views

Is sytem level testcase different from block level testcase? And what is a test vector?

I usually see these terms. In the field of Digital IC Design or in Design Verification, is system level testcase different from a block level testcase? I mean I know they differ from the level of ...
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1answer
41 views

What does this sentence mean in this question (simulator can handle X inputs)?

In my book, one question requires me to find the verification sequence for a circuit. From what I understand, verification sequence must be such that every path is traversed. Then the book ...
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2answers
133 views

How can a manufacturer verify a circuit design? [closed]

Could anyone tell me what means (other than reversing) available to manufacturer of integrated circuits (latest Intel PC CPU's) that would allow them to verify that the actual design on die is ...
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2answers
405 views

How do you check your schematic before passing to layout [closed]

I am working with Altium. What verification do you particularly do when going from schematic to layout in terms of electronic and in terms of capture ?
5
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3answers
801 views

Writing synthesizable testbenches

I'm just starting to learn SystemVerilog and work with FPGAs, and so far I haven't found a satisfactory way to test my code. I'm coming from a software background, and I have always been writing ...
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4answers
1k views

Electronics System Standards Compliance: Certification, Testing & Verification

Please note: this question has to do with the technical compliance aspects of the consumer electronics indsutry, and as such, I believe is within scope for this site. This question is about compliance,...
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2answers
93 views

Thevenin equivalent (verification of answer)

\$ R_{TH} = R1 + R2//R5 + R3//R4\$ Then considering the current source and the resistance R3 as a Norton circuit, one can convert it to Thevenin as follows \$V_I = -IR3\$. Then we have the voltage ...
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1answer
907 views

Power calculation of circuits

Please read on..... this looks long but is entry level and easy I have done many simple projects based on microcontrollers but have not considered power and required current(for circuit to work) ...
4
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2answers
116 views

Circuit Testing, Verification & Certification Standards for Biomedical Devices

Please note: I would have posted this question on HealthIT.SE but they are apparently now closed for business, and I believe this site is the next most appropriate place to ask this. I believe this ...
3
votes
1answer
156 views

Modelsim - Weird verification problem with DDR and Xilinx UNISIM

I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...
6
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3answers
3k views

EMC testing vs. EMI testing

What is the difference between EMC testing (Electromagnetic compatibility) and EMI testing (Electromagnetic interference)
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1answer
260 views

Verifying a Meier Crossfeed Build

I've built a "Bass Enhanced Crossfeed" from a kit, which I believe is based on Meier's Crossfeed design. I prototyped it first on a breadboard, forgot to ground the output jack because it wasn't ...
2
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2answers
330 views

Of what real, practical use is electronics certification?

I am brand new to EE/ECE and am aware that companies such as UL offer a gammit of services such as: Circuit verification (they verify your schematic does what its supposed to do and doesn't have any ...
5
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3answers
280 views

Testing paradigms for consumer electronics [closed]

I am brand new to EE/ECE (my background is software) and I am curious about how real-world electronics testing takes place. In software, there are many different types of tests that a piece of code ...
1
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1answer
903 views

Error Loading Design Unresolved Reference

Please help! DUT: AND gate module ANDgate(a, b, c); input a; input b; output c; assign c = a & b; endmodule TESTBENCH: Without task ...
1
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1answer
649 views

where should I instantiate the DUT object? In the testbench file or in the task?

I am making a testbench in Verilog where it will call different test cases from different modules, each module, one test case/task. I am a beginner in making testbench, can I know where should I ...
0
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1answer
104 views

What do the following terms mean for verification engineers?

When it comes to verification of digital circuits, what is the difference between the meaning of the following terms: What is the difference between specification and requirement? What is the ...
4
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1answer
1k views

How to convert Sequential circuit into a combinational circuit?

My question in general asks how to transform a sequential circuit/FSM into a combinational circuit. The reason why I'm asking is in SAT solving, we can use only combinational circuits. And so in ...
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1answer
2k views

Running UVM example on MODELSIM - ALTERA 10.1d

I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ...
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2answers
932 views

What do the terms code coverage and functional coverage refer to when it comes to digital design verification

It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
0
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2answers
82 views

How to write testbench for digital circuits that output video/audio signal

As far as I have seen, a testbench will provide some stimulus to a DUT and the output shall be compared with expected values. This is one way to verify. Many digial circuits however, may produce more ...
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6answers
12k views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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vote
1answer
246 views

Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields?

I'm working with vr_ad package for e. My question is: What is the difference between 2 following macros for modifying registers (suppose ...
3
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1answer
1k views

How exactly does SystemC/SystemVerilog make the verification flow less laborious task

Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design ...