Questions tagged [verification]

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4
votes
1answer
2k views

How to convert Sequential circuit into a combinational circuit?

My question in general asks how to transform a sequential circuit/FSM into a combinational circuit. The reason why I'm asking is in SAT solving, we can use only combinational circuits. And so in ...
-1
votes
1answer
3k views

Running UVM example on MODELSIM - ALTERA 10.1d

I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ...
1
vote
2answers
2k views

What do the terms code coverage and functional coverage refer to when it comes to digital design verification

It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
0
votes
2answers
92 views

How to write testbench for digital circuits that output video/audio signal

As far as I have seen, a testbench will provide some stimulus to a DUT and the output shall be compared with expected values. This is one way to verify. Many digial circuits however, may produce more ...
16
votes
8answers
15k views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
1
vote
1answer
273 views

Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields?

I'm working with vr_ad package for e. My question is: What is the difference between 2 following macros for modifying registers (suppose ...
4
votes
1answer
1k views

How exactly does SystemC/SystemVerilog make the verification flow less laborious task

Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design ...

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