Questions tagged [verilator]

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“Register is illegal in left-hand side of continuous assignment” in modelsim but not verilator

module foo (A, B, C, Y); input A, B, C; output Y; reg Y; assign Y = (A && B); endmodule ...
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Forcing verilator to take loop label given in RTL

I want to force the hierarchy of signal to take the loop names given in RTL written in System Verilog. Example: for (genvar i=0; i<4; i++) begin: GenLabel ...