Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Using a function to parameterize the length of port in SystemVerilog module
In SystemVerilog and in VHDL as well, we can parameterize the length of ports on modules/entities. This means that the bit length of a port can be changed by using a parameter/generic. The required ...
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Does SystemVerilog have (others=>'0') expression like VHDL?
In VHDL, we can set all bits of something a value by using (others=>'0'). It is also possible to use slice index e.g., ...
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I want to detect a sequence _CDD_DDD where D is any digit from 0 to 9 and is coming from memory. I want read signal to be enabled for one clk
`timescale 1ns/10ps
module detector(
input wire clk,
input wire reset,
input wire memory_status,
input wire [7:0] memory_data,
output reg read_data_enable,
...
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Verilog counter delay in task not working
I'm trying to generate different delays in multiple places using task WAIT in a synthesizable module, and the code is as follows:...
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I2C slave PWM Verilog problems
I have been trying to get this I2C slave controller to work and send PWM signals, but I still can not drive the PWM. I think that it is an issue with the testbench on maybe how the slave controller is ...
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1
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How to select a handshake and code examples in verilog [closed]
I'm new to Verilog, and I was taking a look into the ready-valid handshake. I saw that this is the most used handshake, as it is simple to understand. However, I couldn't find the disadvantages of ...
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Verilog: only run an edge triggered always loop once per edge change
I'm currently working on a simple up counter triggered by the negative edge of a push button. If the button is held while pressed down, the counter gets stuck in the always block and increments by ...
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Verilog error: cannot be driven by primitives or continuous assignment
Please someone explain why I am getting below error from this code:
...
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What is the meaning of "e" in this timing diagram?
https://hdlbits.01xz.net/wiki/Edgecapture
What is the meaning of "e" in this timing diagram?
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Why I am getting one clock cycle delay in Verilog case statement?
I have a Verilog code here:
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Under which situation must a signal be defined as a reg?
For example, in this code. The answer is none of the signals must be declared as reg. So, if this is truly the case, then what is the use of this code? I think the ...
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Defining vector in Verilog
Given the following code:
module add16 (input [15:0] a,b, output[15:0] sum, output court);
Are both input a and ...
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Why does it take so much time for compiling verilog HDL code in Quartus?
I am writing a verilog code in Quartus to encrypt AES-128bit.Every sub-module works well but when I compile the main module, it take more than 2 hours to complete with no error. Especially, when i ...
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1
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Verilog output register not changing
I have to use combinational logic to write Verilog for a circuit schematic. However, my output registers, CLK1 and CLK2, do not change and are stuck at the initial values. What is causing this bug? ...
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SPI read of MAX31856 in Verilog
I am trying to read the K-type thermocouple temperature with MAX31856 in Verilog.
Configured the configuration registers CR0 & CR1.
The conversion result is stored in the registers 0xC, 0XD, 0XE. ...
2
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1
answer
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Misunderstanding in sequential and combinational implementation, based on blocking or non-blocking behaviour
I have a very simple module that waits for the valid signal to become 1 and then sets the ...
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50
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1
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Designing a sorting network with an FSM as opposed to combinational logic
During this semester I have been spending a bit of time learning how to use Verilog. I took on a project to develop a sorting network for 1024 32-bit numbers and tried to develop the circuit by ...
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Is there a way to make the Verilog port declaration based on a macro value?
Basically, what I am trying to achieve is that,
There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized.
But I also want to create dedicated output ...
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1
answer
66
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Verilog variables updated only when assigned as an output
I am facing a strange issue, and I am not sure what is going on here:
assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]};
Where last 5-bits of output data ...
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2
answers
253
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Why does the waveform simulation go wrong using structural D flip flop in Verilog?
I am designing a state machine in Verilog HDL to identify a specific number sequence. I must make it in structural.
When I design the DFF with a behavioral style, everything is great, but with the ...
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1
answer
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Problem with getting data properly from memory using RoCC interface
I am using RoCC interface to communicate with Memory in chipyard.
The memory has the width of 64 bits, and I need to read the first 64 bits and put it in lower register and then read the next 64 bits ...
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Can anyone please take a look of this Verilog HDL code? Does it look strange by any means?
I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
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Verilog- Why is my state machine output arriving one clock cycle earlier?
I'm writing a Verilog code for a state machine with 4 states. state 0 is buffer time of 1 microsecond. state 1 is trig pulse for 10 microseconds. in state 2, the input is read. If the input is high ...
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1
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How to make a waveform simulation in Quartus II from testbench module
I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
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RTL viewer diagram shows no logic gates
I'm trying to write a Verilog gate-level description of this circuit:
My code is here. I compile it on Quartus II (there is no error):
...
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1
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Navigating race condition in Verilog using blocking assignment
If I want to create a pipelined flip-flop (FF) structure, where data from the input is at the output after 2 clock cycles.
This is a top-down blocking assignment code.
...
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1
answer
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My 1-bit ALU is not able to do subtraction [closed]
I am trying to make a 4-bit ALU in Verilog which can perform the following functions:
Add
Subtract
Compare (>,<,=)
AND
The approach I have taken is to make 4, 1-bit ALUs and connect them in ...
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2
answers
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Is it possible to pass random values into SystemVerilog module parameter?
I'm trying to pass a random value using $urandom into a parameter for a top level module in my testbench. I get the error:
...
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1
answer
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How to legally/properly run a Verilog file that needs other files?
I have written a simple ripple carry adder in Verilog (in a structural fashion), and I have defined the required half adder in a module in another file. When I run them (using ...
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Verilog simulation unexpected behaviour in a simple mux design (Using EDAPlayground and EPWave)
I am experimenting with EDAPlayground, and I have created a simple structural module that should take the MSBs from one input and merge it with the LSBs of the other and vice versa, using 2 input ...
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1
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Misunderstood in Verilog basics?
I'm quite new to Verilog. I have some code working, but from time to
time, I get some incomprehensible behavior, and I think I lack some knowledge in Verilog.
Here is a quick example of a more ...
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Why does this Verilog code work without "wire" statements?
My textbook (Brown and Vranesic) gives the following code for a simple 4-bit RCA implementation in Verilog:
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How do I easily create waveform for an expression having more than one signal inside an "if else" block in Vivado?
In a sample code where I have 2 net type variables, I want to plot a waveform for a conditional statement like this:
...
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My FIR filter inputs and outputs are either giving zero or xxx on Systemverilog
I am trying to design an FIR filter which reads very small 10 bit decimal fractions of 2 integer bits and 8 fractional bits as the input and coefficients. But anytime I run the testbench my ...
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Lattice Diamond timing errors in place and route with large registers
Is there a good way to generate a timer with at least 27bits of precision so the place and route doesn't fail? I've tried breaking up the timers into 4x8 bit timers, but it only makes the slack worse (...
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Dataflow operation on a variable is making it a don't care term (Verilog)
I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
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1
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Detect a 1 to 0 transition in an input in Verilog
I'm practicing Verilog using the HDLBits website, and I am trying to solve this problem where I have been given a 32-bit wide input signal and I have to detect whenever a ...
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2
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49
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Verilog Non-Blocking and IF statement mixed
always @(posedge clk)
begin
clk_counter <= clk_counter + 1;
if(clk_counter == divider)
clk_counter <= 0;
end
Will the ...
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1
answer
522
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Instantiating an array of modules in Verilog without using a loop
Let's say I have a module called mymodule. I need to call it 10 times in my top_module file. I have seen someone on ResearchGate ...
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2
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94
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Combinatorial circuit testing with Verilator
I have this very basic combinational logic in file tb_shift_right.v:
...
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Verilog/Xilinx Vivado Multidriven Net
I am trying to implement a TPU like SoC and seem to have a bug in one of my modules.
Here is the code for that module:
...
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2
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I am designing a Carry-Save Adder, but my output waveform is all StX
My CSA has ten 5-bit binary inputs, and one 9-bit output with a carry-out. I am trying to use full adder to realize the function. I have two 3 stages CSA to get two output sets (sum and count) and I ...
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I am designing a 4-bit Carry Look Ahead Adder, but it doesn't work correctly
I am new to Verilog. I am asked to write a gate-level design of a CLA adder. The equation is:
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Accessing all ram contents at the same time
So I want to access all my ram contents in the same time. As in I want to store my 16 ram contents in 16 reg variables and then pass them onto some functions and then insert back into the ram. I want ...
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My 4x4 parallel multiplier outputs are all x, just like the inputs
I'm new to Verilog and I am using ModelSim to compile and simulate.
Here is my code for code for PM:
...
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Shift and continue not changing value
I am trying to implement a Cyclic Redundancy Check algorithm in Verilog. The algorithm will take the data and then find the modulus with respect to the the quotient polynomial. My problem is that in ...
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3
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How to use variable wire data as an integer data for part select? [duplicate]
I am trying to control the width of data bus using part select.
But, the following error occurs:
r_count is not a constant.
Is there a way in which I can use the ...
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