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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target ...

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Verilog: MIDI receiver port fails when more than two keys are pressed at the same time

I'm designing a MIDI receiver port (using Altera CLPD MAX 7000S). The device samples the second byte it receives and outputs the binary value on an LEDs. The device works fine whenever I input MIDI ...
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19 views

TG and Reset waveform of a pixel in Verilog

I recently started reading on image sensors and have started with pixels. The basic thing which I think I should be able to figure out is how to get the TG and Reset signals as outputs in Verilog(I am ...
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2answers
45 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...
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0answers
23 views

verilog traffic light system verilog

i have this 4 way traffic light system FSM ...
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0answers
32 views

verilog traffic light system delay

I'm trying to create a traffic light controller using a FSM. I have a simple one working, but all I need to do is add in a delay so when the lights go from yellow to red, it doesn't change instantly. ...
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2answers
79 views

Verilog problem on Spartan 6 board

I'm planning to do a waveform generator using an FPGA board (spartan 6 board from diychips), however I am new to verilog so I am encountering a bit of a problem. I created a sine-wave sequence using ...
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1answer
51 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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1answer
44 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
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1answer
36 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...
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1answer
41 views

Debugging Gate-level Verilog Multiplexer

I've built a 4-1 multiplexer using three 2-1 multiplexers, but am having a lot of trouble debugging my code. I've tried using $display statements as rudimentary ...
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1answer
29 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
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29 views

how to read a dataset (one bit at a time) in verilog using serial in parallel out (SIPO) process?

I have a dataset of 16 bit wide and of length 5 and I need 1 bit at a time because my ...
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1answer
53 views

Error when trying to use Verilog from VHDL in Lattice Radiant

I'm trying to use an IP generated with the IP Catalog in Radiant, which was only available as Verilog, from my VHDL top level entity. I use it like this: ...
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50 views
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2answers
56 views

How to declare register values as an input in Verilog?

I have a data set consisting of 30 values and each of 16 bit wide. I tried to add these values as an input in my Verilog code in the following way: ...
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0answers
36 views

Value of register going to high impedance after reset in post synthesis simulation(Vivado 2016.4)

In the post synthesis simulation, the value of the register "state" is '0' when the reset signal is '1'. But, when the reset signal goes to zero, the value of register "state" goes to high impedance. ...
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1answer
57 views

skipping local signals declaration

I have some systemverilog codes built by other colleagues and running in hardware without problem. I can see there are some connections for two modules have no local signal declaration like this: <...
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0answers
16 views

Intel Quartus Nios 2 System not opening or saving

I'm currently trying to open an existing qsys file with Nios 2 so that I can edit it. However, the program would always close whenever I do File->open or Ctrl+O. Also, whenever I would try to save a ...
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0answers
38 views

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

I have a design which after synthesis at clock 500 picoseconds in dc_shell takes about 2 minutes to run the synthesized netlist against the testbench. The synthesized netlist worked as expected. ...
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1answer
29 views

How to design a module that counts logic 1s in multiple inputs in Verilog?

For example, I have two inputs, whose value can be either St1 or St0. The changes of states are synchronous to the same clock, say 1MHz of frequency. I want to design a Verilog module that counts how ...
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1answer
28 views

How to compare a re-writable 4 bit value to a given 4 bit input in Verilog?

The goal of this project to design a computational lock alarm in Verilog to be run on an Altera board (note on the board 0 is actually ON and 1 is OFF). Based on the design criteria I created a state ...
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1answer
38 views

Implementing circuit with d-flipflop in verilog

I'm fairly new to Verilog and I'm currently trying to do a structural implementation of a circuit that consists of an d flipflop, it has inputs x and y, x and y are exclusive or'd and that result is ...
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2answers
42 views

Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?

I have a board without Reset input for my design. But I need to reset at fpga startup. Is there a verilog solution to generate this pulse ?
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1answer
89 views

verilog code for 2bit * 2bit multiplier [closed]

There will be two 2 bit inputs (0 to 3 in binary), binary multiplication is to be done on these inputs, the output should be a 4-bit binary number, this output will be fed to a 7 segment display on an ...
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35 views

Variable input MUX in Verilog

What's the best way to make an N:1 multiplexer in Verilog (NOT SystemVerilog), where the maximum N is 64? Each input is 32-bits wide and there are N such inputs. Verilog doesn't allow two-dimensional ...
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1answer
42 views

Asynchronous FIFO in clock domain crossing

Clock domain crossing issue can be solved by using asynchronus FIFO with input frequency f1 is of the source domain and f2 is of the destination frequency. If the data is sent in bursts, depth can be ...
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1answer
70 views

Error (10028): Can't resolve multiple constant drivers for net “rf[7][XX]” at registerfile8x32.v

Hello Im making a register file 8x32 in verilog, the sim looks good but when I compile on quartus it makes Error (10028): Can't resolve multiple constant drivers for net "rf[7][31]" at ...
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1answer
72 views

At both posedge and negedge in Verilog?

In Verilog, I can use an always block and make it trigger on a positive or negative edge. Is it possible to trigger the block on both the positive and negative edge, and thus have it basically ...
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0answers
89 views

Unexpected behaviour of implication operator in SVA

There is an issue I face while using an implication operator in one of my code examples. This code can be found at https://www.edaplayground.com/x/4fVz Code Summary In my code, I have defined ...
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1answer
71 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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2answers
54 views

Verilog inout port

I have a doubt question. I know that I can use "inout ports" to connect to a pin, but can I use "inout ports" to connect internally 2 modules? I'm asking this because I have written an SRAM ...
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3answers
57 views

Clock domain cross and metastablilty problem

I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical, so we put another flip flop with no ...
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3answers
69 views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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1answer
123 views

2D convolution on 32x32 grayscale image on FPGA using verilog for inference of CNN

Hi I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 ...
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1answer
72 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
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1answer
39 views

Blocking and nonblocking statements for counter

Is there any difference between nonblocking and blocking assignment for the following counters? ...
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2answers
62 views

Verilog circuit not synchronous

I am new to Verilog and I was trying to make a Decade counter. I simply took the reference of an actual circuit that implements the decade counter using JK-Flip Flops. So I wrote a sub-module for JK-...
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41 views

How to convert verilog designs for Xilinx products to Quartus? [Beginner]

I am trying to run a complex design that uses both verilog and system verilog files in Quartus, but they do not work. Partly due to syntax errors (VHDL like assigning proper outputs with reg for use ...
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1answer
43 views

Unexpected indeterminate outputs from verilog conditional operator

I have the following combinatorial assignment in a verilog module: assign ififo_di = fetching_pc ? { 5'h02, 3'h7, 16'h8000 } : decoded_insn; where ...
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0answers
38 views

Issue with Booth multiplier

I coded a 4 bit booth multiplier in Verilog. It is working fine for Multiplicand Multiplier + 0 to 7 0 to +7 & -1 to -7 But it does not ...
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2answers
35 views

Easy way to define wire output multiplexers in Verilog

For the wire type in Verilog, I know that I can define a multiplexer as follows wire a; assign a = select ? 1'b0 : 1'b1; And for reg's, I can do it as follows <...
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3answers
100 views

How are blocking statements synthesised? - Verilog

I understand that with the following Verilog code ...
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1answer
67 views

How to write constraint file for the divided clock in Verilog?

I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
60 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
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2answers
988 views

Finite State Machine FSM

I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit, but what is the function of ROM here ?
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1answer
55 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
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2answers
23 views

Verilog :Range must be bounded by constant expression

I have one doubt..... The error is came like Range must be bounded by constant expression when Compile the below line X=in[i+2 : i] +1'b1; In[i]=-1; Please tell how to resolve it?
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1answer
80 views

Weird reset problem in FPGA Design

I'm facing a weird problem. I have written an UART and a FSM. This design just print some text on the screen automatically, just after loading the bitstream. The problem is: when I load the bitstream, ...
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1answer
58 views
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1answer
93 views

Vertical ghosting on 64x32 1/16 RGB LED matrix panel

I have been working at driving some of those generic LED matrix panels found all over the web for sale (such as this one), 64x32 I've struggled a lot with the lack of real documentation, but I've ...