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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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Signed representation of negative numbers in Verilog HDL by Samir Palnitkar

I'm reading about signed number representation and the book says -6'd3 // 8-bit negative number stored as 2's complement of 3 Is there a reason as to why a ...
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1answer
304 views

Is there a right way of implementing a T flip flop in verilog wrt using reset signal?

I made a t flip flop using structural modeling in verilog. ...
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1answer
34 views

Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: ...
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3answers
65 views

output is affected by the next clock period

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if ...
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1answer
92 views

Why am I getting a red wire for my out?

I am attempting to create an output that goes on for a certain amount of time an then goes low for a certain amount of time and my out simply won't simulate. Attached is my code, test bench, and ...
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1answer
89 views

Is there a free tool for finding the observability of signals in a Verilog or VHDL code? [on hold]

I want a free tool for finding the observability of signals in a VHDL or verilog code. Which tool do you know for this?
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1answer
64 views

ALU Design in verilog HDL

Below is my code for ALU which instantiates a 4:1 MUX and a 32 bit squarer modules. The port connections can be seen in module instantiations. However it is important to mention here that input of MUX'...
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1answer
49 views

sequence detector doesn't work expected

I am trying to write verilog code to do sequence detector the the state diagram below. Input is a 2-bit signals and there're 3 state variables as in the image. The goal is to detect the sequence (01)-...
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1answer
42 views

Calculating RPM from Angular Changes

For a project, I have to determine the RPM of a turning resolver. I can correctly read the angular position of the resolver as as a hex number via an RDC. This number is then converted into a 14-bit ...
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1answer
23 views

How to create continuously incrementing counter in structural modelling?

I made the below counter and stimulus/testbench and it works fine. ...
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1answer
44 views

Identify the problems in this Verilog snippet

I think that the code below is wrong because it uses blocking (=) instead of non-blocking (<=) assignments but since there is only one statement in the always block is this an issue? Also, it is ...
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0answers
44 views

Verilog code with delay problem [on hold]

I am trying to do the code below. And after synthesis, I got the circuit as in the image. I am worrying if the circuit works in real life because clock duty cycle is small (the high level duration ...
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2answers
79 views

verilog code with two falling edges

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling ...
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1answer
53 views

FSM sequence detector in Verilog

I'm designing a finite state machine (FSM) to detect the sequence "10001" in Verilog. I'm having a similar problem to that described in this question in that my FSM does not tick when the sequence ...
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1answer
37 views

Does a FIFO data buffer need to have the data be registered?

I'm trying to implement a 64 bit FIFO Data Buffer in Verilog. My design allows for data to be written at 4 bytes or 1 byte at a time, and I'm simply using two multiplexers with control signals for ...
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0answers
35 views

Adding debug changes chip behavior? Reg only updates if debug instantiated

I'm doing a simple seven segment display driver for class, using a MachXO3 dev board connected to 4 displays and 2 buttons on a breadboard. The 4 common-cathode displays have their anodes wired ...
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0answers
26 views

regarding bidirectional accessing of array in verilog

Accessing ram logic in Verilog with an initial block gives an error "cannot synthesize initialized RAM logic <name> " A part of the code will be as follows (...
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1answer
94 views

Removing Noise From an Image [closed]

Can anyone please help me with designing a verilog code for removing salt and pepper noise from an image.
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2answers
28 views

In SystemVerilog, must nets be declared with the **logic** data type?

I'm reading Sutherland's "RTL Modeling with SystemVerilog ..." book. On pages 77 and 79 he makes the following claims respectively: The data type must be the keyword logic, which can be specified ...
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1answer
54 views

How to use different 7-segment for different numbers in FPGA board?

I'm working working with NEXYS4DDR board which has two 4-digit 7 segment displays. Using the proper binary-bcd converter I can display numbers, the problem is... the same number is displayed in all ...
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1answer
21 views

SystemVerilog Code for a lock combination (Finite State Machines)

I am writing code for a door lock combination. My inputs are b0, b1, b2 and b3, which correspond to the buttons to enter the code to unlock a door. The code to unlock this particular door is b2 --> b2 ...
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1answer
44 views

Variable PMW generator using Verilog [closed]

I've made a code in Verilog for a variable duty-cycle digitally controlled PWM generator. I will be using it in a system I am designing for controlling a buck-boost converter that will regulate the ...
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1answer
42 views

Why does this file give syntax error in verilog?

My original file has the following ...
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1answer
21 views

How to assign a single output to different modules in Verilog?

I have designed a simple ALU using Floating Point IP Cores in Xilinx ISE. I have an adder, a subtractor, and a multiplier. The IP Core of addition does the subtraction too and we have only two modules ...
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3answers
99 views

Calculating rolling sum of array

I am trying to implement a rolling average of an array of 12 bit samples in SystemVerilog. New samples are generated and shift into an array via a clocked flip flop. The goal is to have a register ...
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2answers
91 views

Xilinx's ISE (GSR): The initial block adds a delay of 100 time units to simulation

I'm working on a lab assignment in which I'm supposed to simulate a sequential logic circuit (A ROM device). I'm using xilinx's ISE as IDE. My implementation works fine and the logic and the data is ...
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1answer
36 views

How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on ...
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1answer
55 views

Single Clock FIFO with Single Port RAM

I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
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1answer
36 views

Verilog `define macro delimiter

How does Verilog distinguish between the name and text when using the define macro? `define name text For instance, this is a ...
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1answer
31 views

outputs from Verilog finite state machine changing very late, possible reasons?

I am working on a finite state machine that is written in Verilog and being simulated in ModelSim. This FSM is for implementation of a SISC processor. In this implementation, we are using arithmetic ...
3
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1answer
733 views

What is the difference Verilog race condition, X's propagation and Metastability?

I'm trying to understand Verilog Race Condition X's propagation and Metastability with http:/...
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1answer
42 views

Best way to structure Verilog module to allow for simulation clocks

Quick question that I am likely missing an obvious solution for. I have a relatively simple Verilog design which I'll call taco, where the top-level design entity is taco_top (because I'm writing this ...
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3answers
99 views

How can I execute multiple for loops sequentially in Verilog?

I'm trying to turn on the LED lights on my FPGA Spartan board one at a time until all lights are on and then turn them off in the reverse order. I could easily do this in other OOP languages by making ...
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0answers
42 views

HDL implementation of Numerical Analysis Techniques

I am looking for open-source implementations of Numerical analysis techniques (specifically root-finding techniques like the secant method) on FPGA using any HDL. Would also appreciate if anyone could ...
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1answer
58 views

how to get a fixed clock frequency from range of clock frequency input in verilog [closed]

I am writing a code in Verilog(FPGA) which works with the input clock frequency of 128khz, for my assignment my Ip core should be parameterized to work with clock frequencies from 128kHz to 100MHz. in ...
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1answer
39 views

Verilog style: one large always block vs multiple small always blocks?

Say I have multiple registers set up to update on the same clock, based on different conditions. I could set this up as a series of multiple always blocks: ...
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1answer
67 views

error loading design - modelsim

I'm new to modelsim and Verilog and I have got an error in it: # Region: /seqdectorTB # Error loading design 1.3.v: ...
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1answer
76 views

Vivado: Reset signal flagged as primary clock by Timing Constraints Wizard?

I inherited an FPGA design (Avnet MicroZed PCB) that does not meet timing. I have found that many of the design constraints are missing, and I am in the process of trying to properly implement the ...
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1answer
33 views

Error with reference to scalar wire 'reset' is not a legal reg or variable lvalue

I'm getting an error in Verilog with an input parameter it's not recognized as a legal reg or a variable lvalue. I had the same problem with the output in the module however it was fixed by labeling ...
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1answer
66 views

Sequence of evaluation in the following non blocking code?

I have the following verilog code that I came across and trying to find the sequence of evaluation. What value does 'A' have at the end of a cycle and after 5 cycles, when the value of A is 'x' at ...
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2answers
96 views

How much time does it take to increment one bit in Verilog? [closed]

In my lab I'm supposed to write a program in Verilog that makes a timer which outputs a tick every second. A counter module could be used such that as the counter increments to a specific binary ...
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2answers
54 views

What is the purpose of this statement in Verilog?

I see syntax quit similar to this very frequently: 4'd0 Sometimes it is associated with an assign statement: assign S0 = 2'b00; I tried searching online however I could not find any sources.
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2answers
60 views

Place Design error when using if/else statements in verilog

I'm trying to do one of the exercises on the book I'm studying from. The idea is to turn on/off LEDS depending on switches. But I got a place design error when tried to run implementation (synthesis ...
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2answers
74 views

Interval measurement in Verilog

I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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2answers
57 views

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

This question explains how to use Verilog parameters to combine constants from different modules at compile time. I am wondering if it is also possible to use conditional statements to modify ...
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1answer
72 views

Verilog counter made of 32 bit adder (syntax error)

For a school assignment I have to make a counter, based on a 32-bit adder, that increments with 1 every clockcycle if 'enable = high' and 'reset = low'. When I try to use the adder in my counter ...
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1answer
62 views

How do I calculate constant values across several modules at compile time in Verilog?

I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
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1answer
40 views

Verilog Include Statement Error

I'm trying to teach myself Verilog. I have some previous experience using VHDL. I am using Lattice Diamond as my environment. I successfully created and simulated a full adder. I now want to use this ...
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0answers
56 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
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1answer
33 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...