Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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Verilog code for solving a logic gate has this error: Invalid module instantiation

I was going through a book, and there is this exercise that I need to solve with Verilog. I wrote this code, but it's giving me this error: ...
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How do you go about understanding/internalizing a fairly large Verilog design at say a new company you joined

I have just started a job as a digital design engineer at a new company and I'm getting familiar with their designs. I've been reading verilog code and running simulation with ncsim and looking at the ...
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Verilog blocking statements in always block [closed]

I need to perform an addition inside an always block (with clock) but one of the operands depends on the previous value, hence I cannot use non-blocking statements as all variables/registers/wires ...
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1 answer
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Why does this file give me "syntax error: I give up." in EDA Playground?

This is my original file saved as "design.v" ...
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Circuit element simulation using VerilogAMS or SystemVerilog [closed]

I’m trying to simulate the behaviour of a circuit element, for which I only have the VI characteristics (obtained experimentally). I’m fairly new to both Verilog-AMS and SystemVerilog, but my main ...
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0 answers
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Is Unified Power Format "UPF" applicable for FPGA? [closed]

I just want to reduce the power in my design which I use FPGA, I am aware of UPF, and my question is, can I use UPF in FPGA? if not, so, are there any techniques to reduce power dissipation in FPGA ...
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1 answer
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Multiple wire type objects declaration Verilog

I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring ...
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1 answer
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Verilog signed numbers representation

I am confused as to when the '-' sign is used and when 's' is used. This post is somewhat helping, although not entirely. Please correct if I am wrong: For example, to interpret 8'sd244, we write 244 ...
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How to get a reliable simulation of assignment delay in the always block (Xilinx Vivado)?

I am having trouble with simulation of the nonblocking assignment delay in the always block. A simple example: assignment of the input ...
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1 answer
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How do you interpret this in Verilog, when the repeat and posedge are written inside each other like this?

repeat(9)@(posedge clock); ref = ref_count +10; //posedge and repeat are used together repeat(ref)@(posedge ref_clk); repeat(3)@(posedge b_clk);
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External frequency as input to an FPGA [closed]

I want to take frequency generated by a function generator as input to an FPGA board (Nexys 3). I am trying to use a square pulse of 10 kHz as input to the FPGA. So to test how to take an input from ...
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2 answers
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Will FPGA synthesis tools ignore unused modules?

In a VHDL/Verilog design, is it a bad practice to define several (related) modules in the same file? Will the Vivado synthesis tool be 'smart' enough to not book FPGA resources for unused modules?
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Difference in synthesis between bitwise AND (&) and logical AND (&&)

Would these two code snippets synthesize the same way? I know this will be tool dependent because all synthesizers are slightly different. That being said, I think they probably tend to agree on this ...
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2 answers
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Why is the value of product (y) unknown?

I have tried simulating a multiplier which has a datapath and a control path as shown in the video. PFA the link https://www.youtube.com/watch?v=OWUFb2DZpQE&list=PLUtfVcb-iqn-EkuBs3arreilxa2UKIChl&...
1 vote
1 answer
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Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog

I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
1 vote
1 answer
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Verilog contention with I2C port stretching - how to detect clock being driven low by slave when master is driving clock high

I'm trying to implement I2C on an FPGA, but I couldn't seem to figure out a way to detect clock stretching without external circuits. Is there any way that I can detect the wire (I'm using ...
4 votes
1 answer
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Verilog always block -- testing which posedge occurred

I'm trying to understand an always block construct that I'm seeing a lot. This is all in the context of trying to synthesize some hardware in an FPGA, not ...
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What is Warning: Replacing memory \MEM with list of registers?

I have this little code that displays a binary count on LEDs: ...
2 votes
1 answer
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Verilog netlist module instance starts with \

I have a netlist exported from Innovus, and some module instance names start with \ . DFRRQ_3VX1 \cnt_reg_reg[0] (...) In the ...
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1 answer
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Why do I get an inferred latch error here?

I've been building a design in the simulator that uses a shift register. It has the following design goals: if reset_i, then set ...
2 votes
1 answer
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Verilog register declaration with "variable index"

I'm trying to create 8 16-bit registers in Verilog that will take 16-bit values from a 128-bit long shift register. Obviously, I have to make use of index variable such as "i" to make this ...
2 votes
0 answers
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Fast ADC interface with FPGA

I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC ...
3 votes
1 answer
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Verilog generate block error

I have a CORDIC module that I want to instantiate/generate 8 times, basically, I need 8 blocks of CORDIC. So, I have wrote the following statement block, but I get an error: Error: Syntax error near ...
1 vote
1 answer
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Why is my output showing X despite all inputs driven in my simulation? [duplicate]

This is a follow up to my previous question: Why is my output showing as X?. I implemented the Verilog code fix provided by the answer by making the proper signal connections. However, the simulation ...
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2 votes
1 answer
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Why is my output showing as X?

I have written a Verilog file for memory error correcting that takes an n-bit input and using certain logic, it would output an n-bit output that would possess the corrected code. Here are my modules ...
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2 answers
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How to run assembly code on Verilog CPU design?

Looking over the following Verilog CPU description, I have a question about how you would actually go about executing an assembly program on it. I know that Verilog defines the behaviour of the ...
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1 vote
1 answer
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Problem with testing verilog instances using random vectors

I have a set of test vectors saved in a csv file and formatted as follows: 0010,1000,1010 1110,0101,0001 1001,0001,0000 These are randomly generated and can be of ...
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1 answer
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What does the "#" in this Verilog module instantiation mean?

I saw the following instantiation in a Verilog testbench: `define width 8 ...... scale_mux #(`width) m1 (.out(out), .sel(sel), .b(b), .a(a)); I don't know ...
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1 answer
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Parameter binding error in Icarus Verilog

I am trying to design a shift register that can have both serial and parallel outputs. My implementation is posted below: ...
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1 answer
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Problem with reading a .csv file into a Verilog module

I was trying to read a .csv file and use its contents. The csv is formatted as: 0001,1010,1110 0101,1100,1001 My code is: ...
1 vote
1 answer
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Verilog port width larger than defined

I simulated a design and viewed waveforms in Simvision, and an input port width is shown as in1[223:0]. But, it was declared as: ...
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1 answer
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Strange thing with concatenation and adding in Verilog

I have some code for convolution in Verilog where I need to generate the result after multiplying the pixels with kernel and adding bias. After I multiply with the kernel, the value is in signed hex ...
1 vote
2 answers
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Do wire/net type constructs in Verilog map to programmable interconnects/ switching matrix of FPGA?

Reprogrammability in FPGAs comes from 2 building blocks: configurable logic blocks (LUTs) and switching matrix. It is often said that the HDL code gets translated into the corresponding LUT logic, but ...
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1 answer
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Verilog mux select condition not correctly evaluated

I have a Verilog question. For the following wire test, somehow the mux select condition B + 1'b1 == C does not evaluate to true ...
3 votes
2 answers
161 views

Reading a file in Verilog

I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are: -4 20 28 -52 and so on. Also, after reading ...
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1 answer
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Verilog help: .V to schematic

I trying to see what is going on in this .v file to learn (need visual). Could any one help with terminology: What is a Verilog schematic called? What is a Verilog schematic viewer called? Could ...
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2 answers
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What is the maximum limit of signals in sensitivity list of always block?

I am working on a project with multiple signals required in the sensitivity list. I want to know is there any maximum limit of signals that can be present in the sensitivity list of the always block ...
3 votes
2 answers
514 views

What kind of adder does the default Verilog addition operator implement?

If I want to add two 16-bit inputs, for example, using the default + operator, what kind of adder will this implement in hardware?
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CORDIC module for (0, 90)

I found this CORDIC Verilog code online. It calculates sine and cosine from (0, 360). I was thinking if there is a way to modify it to (0, 90) and then use 4 such CORDIC modules in a pipelined ...
1 vote
1 answer
88 views

SystemVerilog testbench giving don't care (X)

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care. ...
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1 answer
249 views

Syntax error verilog code token is 'module'

I am currently in training phase with verilog and I encountered an error near the 'module'. Basically what I did is that I want to assert the output q to be either '1' or '0' from my design, which is ...
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1 answer
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Why does adding "& 1" to an assign statement produce a completely different synthesis?

I am trying to implement a one-bit full adder in Verilog. Here's my original code: ...
1 vote
1 answer
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Multiplication 32x32 Mealy machine using 16x8 multiplier Verilog code

I am trying to implement a multiplication 32x32 Mealy machine using a 16x8 multiplicator in Verilog. I wrote the arithmetic part and the FSM part + a code to connect both and a test bench, but when I ...
-1 votes
1 answer
187 views

Syntax error in continuous assignment

Why is there a syntax error in the continuous assignment to the out_money signal? ...
0 votes
0 answers
76 views

Priority encoder for TDC in Verilog

I am implementing a TDC TDL on Artix 7 and I need an encoder to convert the thermometer code to binary code using an encoder. I did my research on several encoder approaches and ultimately chose to ...
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3 votes
1 answer
645 views

Result is XXXXXXXXXXXX for Verilog

I'm currently doing a project, and I can't find the reason when my result is XXXXXX which is error. The code run smoothly when I test, but when I want to see the result, it comes out something I can't ...
1 vote
2 answers
111 views

Why is order of bits not getting reversed?

In this code, while declaring in and out, the seventh bit of input is MSB, while the zeroth bit of output is MSB. So, why is the ...
1 vote
1 answer
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How to print uvm_tlm_analysis_fifo properties with `uvm_info() in UVM?

I'm stuck on the print properties of uvm_tlm_analysis_fifo handle with `uvm_info(). I made a simple sequence item as below. <...
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1 vote
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FPGA blocking assignments in always block not working properly

In the following setup I have created a custom clock through switch on Spartan 3E FPGA to toggle the LED states one by one. I have connected 8 registers with 8 LEDs. By triggering the clock through ...
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1 answer
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More clarity on Verilog Non-Blocking assignments

Consider HDL code below: ...

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