Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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Verilog Implementation error DFFs and Gates

I am a beginner in verilog and came across this question- Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins. Build ...
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Verilog: use calculated variable as length or index of another variable

I need to expand and truncate variables a lot in my Verilog project. The issue is that the constraints for these operations are dynamically generated. Example: ...
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Inferred latch occurence in verilog

Implement the following circuit: Note that this is a latch, so a Quartus warning about having inferred a latch is expected. This is my implementation ...
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Logic Synthesizer generates bad timings

I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
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3answers
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“Register is illegal in left-hand side of continuous assignment” in modelsim but not verilator

module foo (A, B, C, Y); input A, B, C; output Y; reg Y; assign Y = (A && B); endmodule ...
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System verilog bind assertion sequence with variable [closed]

I have to write system verilog assertion with binding. The assertion should be something like: assert property (@(posedge (mod_clk & clk_gen_enable)) ##delay (clk_sync = 1))`; mod_clk, ...
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Signed Overflow Detection

I am a beginner at verilog and encountered this problem: Assume that you have two 8-bit 2's complement numbers, a[7:0] and ...
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3answers
45 views

How to implement a flip-flop with synchronous and asyncronous reset?

The flip-flop of FPGA (at least those from Xilinx or the ECP5 family from Lattice) support both synchronous and asynchronous reset (extract from the ECP5 datasheet : "There is control logic to ...
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1answer
61 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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1answer
79 views

Embedding data in RAM during synthesis

I have designed a CPU that works in simulation using Verilator, and would now like to test it in hardware on an FPGA. A quick way to get to the testing phase would be to embed a program to run on the ...
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In Verilog, does an event control always execute once at the beginning?

As illustrated in the image below, there is an event control with the variable r (for reset). I have not initalized c in the top module, but it shows in simulations that it starts at a low state. The ...
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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How to extend a pulse in system verilog

I am trying to make a very simple module in System Verilog that receives a short pulse as an input, and returns as an output a pulse which is twice wider. For example, if the input is a 1ns pulse, ...
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How does this code execute with respect to the The stratified event queue?

always @(posedge clk) begin A <= 1; #5 B <= A + 1; end I was wondering how this code is working . How are delay assignments executed in the event queue ?...
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1answer
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Verilog code: how do I make the state transitions instantaneous?

I have the following Verilog code to implement ...
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1answer
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Intra-assignment delay in verilog

What is the difference between x=#5 a; where a blocking statement is used And x<=#5 a; where a non blocking statement is used
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In Verilog , if the always@ block is executed sequentially , how do non-blocking statements work since they are executed parallely?

I am getting totally confused because contradictory things are given. https://class.ece.uw.edu/371/peckol/doc/Always@.pdf In this pdf, it is said that whether the 'always block' will be executed ...
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System verilog: check if logic signal changes at posedge

I'm relatively new to SV. I'm building a testbench in which I want to monitor a signal and take some action if it value changes @ clock posedge. I’m looking for a compact way to this (I.e. not using a ...
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Unary-type input to binary output in Verilog?

I've built an FPGA-based circuit which outputs to \$n\$ ordered bits strings which take on the form of either \$k<n\$ \$1\$'s followed by \$n-k\$ \$0\$'s, or \$k\$ \$0\$'s followed by \$n-k\$ \$1\$'...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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2answers
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How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
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2answers
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ModelSim wave window showing zero time transitions

I'm new to verilog and so ModelSim. There's a problem or actually may not be a problem that I have noticed. It seems to me that ModelSim wave window imposes by default a transition at time zero on ...
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Why would this cause a latch?

I'm reading ZipCPU's tutorial and got confused. Specifically, I'm referring to this page. To transcribe the Verilog code: ...
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1answer
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The error “requires SystemVerilog extensions” while declaring an error

What's wrong with the following code? The array "FIFO" is declared correctly, but an error appears. Can you please help how to fix this? ...
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2answers
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Median Filter FSM Modelling

I'm trying to build a median filter in Verilog using a comparator to sort out the highest pixel value and erase it, then sort out the next highest etc. until I have only 5 pixels left (I'm treating ...
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1answer
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always @(*) vs. assign

I may have used these interchangeably without thinking, and did not have any problems. always @(*) output = input ? a : b or ...
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2answers
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Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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2answers
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Combinational loop in Verilog/System verilog

What's the difference between a += 1 and a = a+1 in SV/V? always_comb begin a = '0; a += 1; end always_comb begin a= '0; a = a+1; end Is 2nd case combinational loop?
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1answer
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PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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1answer
42 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
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1answer
41 views

array must be of constant range error

i have an output reg called compressed_out.base_size and delta_size are parameters. if the enable[l] = 0, I need the base_size bits in sub_out to be written to compressed_out. if enable[l]=1, only ...
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1answer
36 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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2answers
47 views

What's an idiomatic way to detect posedges inside a FSM in Verilog?

I'm getting started with Verilog, using FSM patterns. I'm finding that something I keep needing to do is to wait in a particular state until I see a leading edge of a (much slower) signal. What I ...
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1answer
48 views

Verilog - use a clock signal as a value in its own procedural block

I tried synthesizing the following code and was surprised to see that it doesn't work (at least with Vivado 2017.2). ...
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1answer
92 views

How to implement 32-bit adder logic using two 16-bit adders?

I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this. verilog code ...
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1answer
85 views

Mod-3 asynchronous up counter using T flip flop in verilog

Design: ...
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1answer
120 views

Single-cycle MIPS processor in Verilog

I'm very new to Verilog and I've tried to create single-cycle 32bit MIPS processor. Instructions I want to implement are ...
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2answers
128 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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1answer
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Verilog : Using previous generate iteration's wire in current iteration

For background, I am trying to implement something like this: My idea was to use a couple of nested generate statements to first create each of the 4 stages, then the second to create each mux in ...
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1answer
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verilog-101 detect I can not y output

ı can not get y output for '101' detect ...
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1answer
49 views

How can i make an always statement run with initial values in verilog

I am trying to use this MUX in a MIPS Datapath design that i'm trying to create, but since i use an initial for these, they don't change and the always block is never triggered in the first clock, ...
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64 views

Bidirectional Counter implementation using internal counter

There was an assignment as follows: Design a two directional three-bit counter with the following functionality. the counter is changing its value on each positive edge of the clock. the counter's ...
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1answer
95 views

Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
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1answer
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Initial value for 32 bit register made using D F/F in verilog

I am trying to make a 32-bit register using 32 negative edge trigerred D F/F. Here is the verilog code for D F/F: ...
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1answer
51 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...
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Round-Robin Arbiter Architecture from Efficient microarchitecture for network-on-chip routers

I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient ...
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1answer
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In Verilog, How is a 4:1 Mux made using case statements without creating a D-latch?

Whenever I try to make a 4:1(32:8) mux in verilog using the following statement: ...
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1answer
60 views

When to use blocking and non-blocking assignments

I am having a really hard time to understand where to use blocking and non-blocking assignments. I have read many answers regarding this on this site and have also referred to book on Verilog by "...
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1answer
62 views

Understanding the Verilog Stratified Event Queue

I'm trying to understand how the Verilog scheduling algorithm works. The below example outputs 0, xxxx and not 1010. I'm not ...
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1answer
87 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...