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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target ...

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45 views

Clock domain cross and metastablilty problem

I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical, so we put another flip flop with no ...
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3answers
46 views

Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, ...
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1answer
64 views

2D convolution on 32x32 grayscale image on FPGA using verilog for inference of CNN

Hi I am new to the world of convolutional neural networks and would like to implement a 2D convolution operation using the sliding window approach on a xilinx FPGA. The input to the image is a 32x32 ...
2
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1answer
59 views

Optimizing Verilog Code

I'm trying to convert Hex number into Decimal ASCII representation in Verilog, I've done the next code that converts successfully but this it cost a lot of timing for my design, could anyone help me ...
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1answer
32 views

Blocking and nonblocking statements for counter

Is there any difference between nonblocking and blocking assignment for the following counters? ...
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2answers
48 views

Verilog circuit not synchronous

I am new to Verilog and I was trying to make a Decade counter. I simply took the reference of an actual circuit that implements the decade counter using JK-Flip Flops. So I wrote a sub-module for JK-...
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0answers
38 views

How to convert verilog designs for Xilinx products to Quartus? [Beginner]

I am trying to run a complex design that uses both verilog and system verilog files in Quartus, but they do not work. Partly due to syntax errors (VHDL like assigning proper outputs with reg for use ...
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1answer
39 views

Unexpected indeterminate outputs from verilog conditional operator

I have the following combinatorial assignment in a verilog module: assign ififo_di = fetching_pc ? { 5'h02, 3'h7, 16'h8000 } : decoded_insn; where ...
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0answers
16 views

How to stop netlist generation indefinitely during functional simulation (Quartus Prime Standard Edition)?

I'm having trouble running my functional simulation for a Verilog code I designed. I tried this code on my friends laptop (and with proper pin assignments) and it works on his yet when I run it on ...
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0answers
32 views

Issue with Booth multiplier

I coded a 4 bit booth multiplier in Verilog. It is working fine for Multiplicand Multiplier + 0 to 7 0 to +7 & -1 to -7 But it does not ...
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2answers
29 views

Easy way to define wire output multiplexers in Verilog

For the wire type in Verilog, I know that I can define a multiplexer as follows wire a; assign a = select ? 1'b0 : 1'b1; And for reg's, I can do it as follows <...
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3answers
76 views

How are blocking statements synthesised? - Verilog

I understand that with the following Verilog code ...
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1answer
54 views

How to write constraint file for the divided clock in Verilog?

I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
51 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
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2answers
945 views

Finite State Machine FSM

I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit, but what is the function of ROM here ?
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1answer
35 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
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2answers
21 views

Verilog :Range must be bounded by constant expression

I have one doubt..... The error is came like Range must be bounded by constant expression when Compile the below line X=in[i+2 : i] +1'b1; In[i]=-1; Please tell how to resolve it?
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1answer
72 views

Weird reset problem in FPGA Design

I'm facing a weird problem. I have written an UART and a FSM. This design just print some text on the screen automatically, just after loading the bitstream. The problem is: when I load the bitstream, ...
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1answer
44 views
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1answer
52 views

Vertical ghosting on 64x32 1/16 RGB LED matrix panel

I have been working at driving some of those generic LED matrix panels found all over the web for sale (such as this one), 64x32 I've struggled a lot with the lack of real documentation, but I've ...
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2answers
262 views

Verilog - Can you `define a bit slice?

Can you define a bit slice in Verilog? For example, is this possible: ...
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0answers
33 views

Multiple driver error in Verilog

I am trying to run carry look ahead adder but when I try to synthesize it i get the errors. Signal cin in unit main_src3 is connected to following multiple drivers: ERROR:HDLCompiler:1401 - " Signal g[...
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2answers
225 views

When is proper to use <= or = assigments in Verilog

I have not clear at all this part of Verilog when using <= or when = I have some always blocks that make some adds, subtracts and multiplies an example is like this: ...
0
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1answer
47 views

Verilog Case Statement evaluating all combinations of a 10-bit ADC sample

I have a (hopefully) pretty easy question on case statements. If I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a ...
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1answer
44 views
1
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1answer
51 views

How to truncate the least significant bits in a Verilog assignment?

I have a register of around 120bits, where data is shifted in lsb first, at some point I want to assign it to smaller registers but instead of truncating the most significant bits, I'd like to ...
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2answers
32 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
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2answers
46 views

Sensitivity list for clock edge and state change

Not sure if this is correct implementation, although it works so far. I output the data on the rising edge of the FETCH signal (this is not a clock). The data should only be out in the OUTP state. ...
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0answers
50 views

Verilog localparam as string in vhdl?

I found the following statement in a verilog modul: localparam str2=" Display Demo ", str2len=16; Seems to me that str2 is a string value but I wonder how this ...
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2answers
64 views

how to pass parameter variable to module in verilog

I need some help changing dynamically parameters of one module I'm trying to extract part of network data that it comes from the top module and goes to the internal modules In specific I have one ...
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2answers
33 views

Icarus verilog syntax error in a generate block

In the top level of a module, I have the following block: ...
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1answer
59 views

Pipelined vs Low Latency implementation of cube of a number in Verilog

I was studying about FPGA design and then came across this terms Throughput and Latency. So the author provided an example of a ...
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2answers
75 views

mips single-cycle branch verilog

I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
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1answer
45 views

Including one module in another module with variable

I need to implement this code to synthesize and do so that xor21 and and21 will work separately. ...
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1answer
49 views

Should I model an ethernet message decoder with byte based instead of bit?

The steaming interface (for example the Avalon ST) input logic data[255:0] in_data; // a 256 bits input stream data The local signals of data like this: ...
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1answer
49 views

Problem with my 8-to-3 line priority encoder using verilog gate level description

I am attempting to build a working 8-to-3 line encoder using gate level description in verilog. Although, I have working models, in terms of successful compilation and simulation, the recurring issue ...
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2answers
67 views

Asynchronous Active High SET & RESET D-FlipFlop

I have two pieces of modules as below, may I ask which one is the right verilog to represent an Asynchronous active high set/reset D-flip flop (Rising clock edge)? Are both of them logically ...
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2answers
99 views

Unable to figure out VGA [Verilog]

After doing plenty of research on how to generate VGA signals and looking at a few code examples, I attempted to write my a simple VGA signal generator that just displays a single solid color on the ...
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1answer
58 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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2answers
99 views

SystemVerilog: Race condition in memory

Hello I'll be brief because my English isn't good thank you for your patience I'm working on a system that drives this memory: ...
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3answers
117 views

Demodulation of a data

As seen in this picture, I have a circuit that has created those desired pulses in the output. There is a last stage in my circuit and that is: Translating the times that more pulses have happened to "...
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0answers
51 views

fsm model in verilog

I have tried replacing the while loop with a FSM model. Though it was synthesized correctly, I am not able to get the right answer at the output. ...
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4answers
110 views

Toggle output using Verilog

Can anybody explain this code to me? ...
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1answer
69 views

how to access the same RAM module from different modules?

I have a cyclone v gx starter kit. It comes with 4884 bits onchip memory. I want to write a module for accessing the onchip memory. So, I have generated the ram ip reference design from ip catalog ...
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3answers
114 views

Is it possible to create a working JK-flip flop using gate level description in Verilog

I am attempting to create a working JK flip flop using gate level description in verilog. Although, the design is successfully compiled and simulated, the outputs to the FF are always unknown. ...
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1answer
19 views

Expressions in Verilog module instantiations

If I have the following verilog module definition: module foo ( input a, output b ); assign b = !a; endmodule And then I instantiate it within another ...
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2answers
87 views

What is the difference between a casez and a casex statement in Verilog?

I know that a case statement in Verilog can start with case, casex, or casez. However, with casex and casez, when would I use one over the other?
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1answer
62 views

Assigning specific bits of vector to outputs in verilog ucf

When I set up my module, I have code like input signed [7:0] SIGNAL but in the UCF I want to assign each bit individually. Currently my code in the UCF looks ...
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1answer
171 views

How to define n-bit signed int in systemverilog?

We can define unsigned integer like these: typedef bit[4:0] int5; // 5 bits unsigned integer typedef bit[3:0] int4; // 4 bits unsigned integer How to define type ...