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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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How to create a 400 MHz synced clock from 1200 MHz in Verilog?

I'm trying to generate a 400 MHz synced clock from 1200 MHz. ...
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Can generated events get placed before events already in the event queue in SystemVerilog?

I tried to consult the Verilog LRM but wasn't successful; some of the reason is because I don't really know the correct terminology. This question is related to this one here, but I never got an ...
EE18's user avatar
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Synthesizable system verilog code to find least number in an array

I have tried a few ways using for loops to find the least number in array, but having a hard time in updating the pointer whenever a new least value is encountered. I am following the below textbook ...
Saransh Choudhary's user avatar
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1 answer
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I am calculating the sum and signed overflow on the addition of two signed numbers, but the overflow is not true in some cases. Can anyone correct it? [closed]

...
C0MPL3x's user avatar
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1 answer
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Is This Verilog Assignment Statement Legal? (Else assigment to itself)

I'm working on a Verilog project and have encountered a possible issue with an assignment statement. I wanted to check if the following code is legal in Verilog: ...
Lane's user avatar
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Simulating a noisy sine wave

I'm trying to simulate a sine wave with white Gaussian noise on my test bench. I have generated 40 values for this signal following @vipin's blog post here and integrated this module into my test ...
nisak's user avatar
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Alignment characters in the JESD204B standard

I have a question regarding the alignment characters in the JESD204B data converter interface protocol. To anyone who is familiar with this protocol. There are certain alignment that are used during ...
fisherman's user avatar
2 votes
1 answer
79 views

Divider Generator handshake is not working

I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
nisak's user avatar
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-1 votes
1 answer
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Why does multiplication give 1 even though inputs are not 1? [closed]

When I'm doing multiplication inside an always block for my variables K_next_num and ...
user25028310's user avatar
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1 answer
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Why does Divider Generator output an unknown x?

I'm a beginner in FPGA programming and I'm trying to implement a noise filter in Verilog on Vivado. I'm doing calculations on the input signal where division is needed, so I'm using the Divider ...
user25028310's user avatar
1 vote
1 answer
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How do i write my synopsis design constraint(sdc) for a generated clock with a variable frequency?

Here is what I got so far for my SDC: create_clock -name clk -period 20 -waveform {1.7 19} This is the part of my verilog code that derives a variable frequency ...
Mister Moron's user avatar
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3 answers
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Increase operation width during the operation without extra registers in Verilog

I have two signals of type "reg" with different bit lengths: reg [15:0] A; reg [11:0] B; I want to display the value of ...
Saeed Jazaeri's user avatar
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Why is my code implemented in latches?

I am starting to design in a HDL. So, I'm designing a simple test, where variable "var" is an and of each "partial" row. However, when I synthesize this, I see that the RTL ...
Lane's user avatar
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Verilog set bit counter

I'm trying to create a Verilog program that would display the digit with greater number of bits set. The code is working. However, it counts the bits from the previous values instead of its current ...
Paula Bianca Pascual's user avatar
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1 answer
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How to Resolve LINT-1 Warning During Synthesis?

I am currently working on the synthesis stage of a hardware design project and encountering a specific warning from the LINT-1. I'm seeking assistance to resolve this issue. Tool: design compiler ...
강영완's user avatar
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1 answer
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Synthesis with Verilog Parameter AUDIO_DW = 32 Results in LINT-1 Warning

I'm working on a Verilog project and encountering a warning during synthesis. When I set the parameter AUDIO_DW = 32, I get a ...
강영완's user avatar
2 votes
2 answers
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Passing Matrices (larger arrays) between modules

I'm trying to have my design be more compartmentalized and separate each task into different modules/source files. I basically want to pass a matrix and a vector into a module I created where I'll do ...
Samuel's user avatar
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2 answers
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Modeling Flip-Flops (RS, T, JK) in Verilog

I encountered an unusual behavior while simulating flip-flops in Verilog using Vivado. Take, for instance, a four-bit up counter where I used an RS flip-flop for the most significant bit (...
user97662's user avatar
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Vivado and simulation for a 4-bit up counter

I am creating a 4-bit up counter using Verilog in Vivado. For this counter, I would like to use flip-flops to represent each bits from Q0 to Q4. For simplification, I used D flip flop to represent Q3, ...
user97662's user avatar
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2 votes
2 answers
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Please help me with my verilog code for processor (extension)

This is an extension to my previous question. I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (...
Damstridium's user avatar
1 vote
1 answer
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Can someone help me with this Verilog code for a processor?

I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (instruction + data memory). Here is the instruction ...
Damstridium's user avatar
1 vote
1 answer
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Error while building a MIPS ALU Controller Design

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Zelda's user avatar
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1 answer
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Confusion in synthesis of parallel case

I am learning full case and parallel case directives used in synthesis. I am unable to understand what will be the output if "sel" matches "a" as well as "b". My doubt is ...
Jatin Sharma's user avatar
-1 votes
1 answer
60 views

canonical way to set a reset line at startup in verilog [closed]

(Total noob at FPGA) For real hardware not simulation. I want to assert a global reset / clear signal on the first n clock cycles (maybe just 1)
pm100's user avatar
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1 vote
1 answer
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Single-Digit BCD Adder

I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
David's user avatar
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1 vote
2 answers
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Final non-blocking assignment to a register in case of parallel if-else statement in Verilog

I have the following code: ...
lousycoder's user avatar
1 vote
1 answer
59 views

SystemVerilog help, I'm stuck

Please help with this SystemVerilog code. The intended behavior is that the seven-segment displays 7 and 5 will show the current inputs, and the segment displays 0 and 1 will be the two-digit result ...
David's user avatar
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2 votes
1 answer
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Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
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1 vote
1 answer
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Dissect code related to "Convergent rounding: Round half to even" written in SystemVerilog

This question is related to article on rounding found here. The "Convergent rounding: Round half to even" code is written as follows: ...
quantum231's user avatar
0 votes
1 answer
72 views

Why am I getting error C:\Program Files (x86)\iverilog\bin\iverilog.exe: unknown option -- O when trying to run this Verilog code?

On Visual Studio, I run this Verilog simulation command, but I get the error message: ...
Ahmed Sweillam's user avatar
0 votes
1 answer
75 views

When I assign a signal with x in verilog, what happend in circuit?

I want to know what happen in circuit if I assign wire_a = 2'bx1. Actually I used a module MuxKeyWithDefault, I want to use a ...
Molly Zheng's user avatar
1 vote
1 answer
59 views

Verilog: How do I assign multidimensional arrays as outputs in my module

I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way. For Example: ...
Khadeer Bin Kashif's user avatar
1 vote
1 answer
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Why does passing the subrange of a bitvector to a module in Verilog produce an unexpected result?

To better understand what it is that I'm asking about, please compare "Code A" to "Code B" below. Code B is more compact, but unfortunately does not produce what I would consider ...
phil1008's user avatar
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2 votes
4 answers
136 views

Verilog Non-blocking and Blocking is logically confusing

I am having a very difficult time to understand the logic behind the naming of "Blocking" and "Non-blocking" statements in Verilog. By definition, Blocking assignment evaluates and ...
user97662's user avatar
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1 vote
2 answers
73 views

How are event-controlled events scheduled in Verilog?

Consider the following snippet (please let me know if you need me to include more): ...
EE18's user avatar
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1 vote
1 answer
71 views

Moore Detector -1011, non-overlapping case

I am not able to figure out why the output goes low when I have done it properly. I used the similar logic for Mealy. It worked, but here it's not proper. ...
Ojas Kudari's user avatar
1 vote
2 answers
74 views

How does Verilog deal with this snippet (procedural block order dependence)?

At the outset, I would like to say that I am not able to run this snippet at the moment but, even if I were, I hope this question would still stand as I'd like to understand why the Verilog standard ...
EE18's user avatar
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1 vote
2 answers
89 views

UART Transmitter implementation using Verilog

I am trying to implement the UART transmitter FSM using Verilog, but the FSM is stuck at IDLE state. Can someone tell what mistakes am I making? The code is as ...
Kartikey's user avatar
1 vote
2 answers
63 views

Why am I getting ZZZ output for my Verilog cordic code?

...
user avatar
1 vote
1 answer
122 views

Verilog synthesize FIR filter coefficients in correct representation

For an implemented FIR filter in Verilog, I generate filter coefficients using Python's scypi. Using its firwin-function, I receive 64-bit floating-point coefficients like: ...
Alex's user avatar
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1 vote
2 answers
49 views

Can an event name be manipulated in Verilog/SystemVerilog?

In a Verilog testbench.v, there are commands that are used in a task. ...
Carter's user avatar
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0 votes
1 answer
113 views

Is there any restriction on the maximum size of a SystemVerilog packed array?

Suppose I make a packed array as: logic [x:0] packed; As packed arrays guarantee continuous memory allocation, is there any restriction on the maximum value ...
Kartikey's user avatar
0 votes
1 answer
96 views

Post Synthesis Simulation in QuestaSim

I am attempting to perform post-synthesis simulation of a Verilog system designed in Vivado on QuestaSim. I am using QuestaSim 2021.2_1 and Vivado 2020.2. Here are the steps I have followed: I ...
Adam01's user avatar
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1 vote
1 answer
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How to connect multiple TLM ports to UVM Sequencer?

There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
TSyi's user avatar
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4 votes
2 answers
181 views

Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog

Please refer to the following Verilog module: ...
lousycoder's user avatar
1 vote
2 answers
111 views

Verilog sum problem

I have an array named mixed_signal, and I need to sum of its elements in a register but it cannot be sequential. Can you help me? ...
Emre YILDIZ's user avatar
1 vote
1 answer
68 views

Functions in Verilog for combinational logic

I encountered something weird in a Verilog code, and I have doubts about it. Someone used a function in Verilog in the following way: ...
Michael Rahav's user avatar
1 vote
1 answer
61 views

(Verilog) Why $signed() and >>> operation cannot generate ASR when inside ?: operator in such case?

Here is the module, I want to use signext to determine whether it is ASR or LSR. ...
bionukg's user avatar
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2 votes
2 answers
96 views

Fixed point multiplication circuit in HDL doesn't work as expected

I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
Becker's user avatar
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2 votes
1 answer
75 views

How to design a T flipflop with NAND gates in Verilog (structural design)?

From a typical circuit diagram of T flip flops made of 3- and 2-input NAND gates, I tried to implement it with this code but could not figure out why am I not getting any answer in output terminal (...
Dhrubajyoti Mandal's user avatar

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