Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

Filter by
Sorted by
Tagged with
0 votes
1 answer
68 views

My FIR filter inputs and outputs are either giving zero or xxx on Systemverilog

I am trying to design an FIR filter which reads very small 10 bit decimal fractions of 2 integer bits and 8 fractional bits as the input and coefficients. But anytime I run the testbench my ...
topeagb's user avatar
-1 votes
0 answers
53 views

Reducing complex Verilog clock generation

I have the following verilog module, let me explain what it does with examples from GTKWave ...
Vladouch's user avatar
-1 votes
0 answers
49 views

Simulate a verilog design with IP blocks [closed]

I would like to simulate and visualize my design with GTKWave. I am targeting the Arty-S7 dev board and have to use several IP blocks (BUFR, BUFGCE_DIV, etc..) in my design. Of course I do not have ...
Vladouch's user avatar
1 vote
2 answers
57 views

Lattice Diamond timing errors in place and route with large registers

Is there a good way to generate a timer with at least 27bits of precision so the place and route doesn't fail? I've tried breaking up the timers into 4x8 bit timers, but it only makes the slack worse (...
Gacekky1's user avatar
1 vote
1 answer
29 views

Dataflow operation on a variable is making it a don't care term (Verilog)

I want to implement a 4-bit parallel adder and subtractor using the same circuit while using a control input variable to switch between addition and subtraction. When my ...
Lev Yashvin's user avatar
1 vote
1 answer
68 views

Detect a 1 to 0 transition in an input in Verilog

I'm practicing Verilog using the HDLBits website, and I am trying to solve this problem where I have been given a 32-bit wide input signal and I have to detect whenever a ...
Socks's user avatar
  • 25
0 votes
2 answers
41 views

Verilog Non-Blocking and IF statement mixed

always @(posedge clk) begin clk_counter <= clk_counter + 1; if(clk_counter == divider) clk_counter <= 0; end Will the ...
Fc3 Fc3's user avatar
1 vote
1 answer
49 views

Instantiating an array of modules in Verilog without using a loop

Let's say I have a module called mymodule. I need to call it 10 times in my top_module file. I have seen someone on ResearchGate ...
Socks's user avatar
  • 25
1 vote
2 answers
49 views

Combinatorial circuit testing with Verilator

I have this very basic combinational logic in file tb_shift_right.v: ...
NoiseEHC's user avatar
  • 115
1 vote
1 answer
43 views

Verilog/Xilinx Vivado Multidriven Net

I am trying to implement a TPU like SoC and seem to have a bug in one of my modules. Here is the code for that module: ...
Vladouch's user avatar
0 votes
2 answers
34 views

I am designing a Carry-Save Adder, but my output waveform is all StX

My CSA has ten 5-bit binary inputs, and one 9-bit output with a carry-out. I am trying to use full adder to realize the function. I have two 3 stages CSA to get two output sets (sum and count) and I ...
JarvisLYu1's user avatar
1 vote
1 answer
58 views

I am designing a 4-bit Carry Look Ahead Adder, but it doesn't work correctly

I am new to Verilog. I am asked to write a gate-level design of a CLA adder. The equation is: ...
JarvisLYu1's user avatar
0 votes
1 answer
59 views

Accessing all ram contents at the same time

So I want to access all my ram contents in the same time. As in I want to store my 16 ram contents in 16 reg variables and then pass them onto some functions and then insert back into the ram. I want ...
Rezef's user avatar
  • 93
1 vote
1 answer
51 views

My 4x4 parallel multiplier outputs are all x, just like the inputs

I'm new to Verilog and I am using ModelSim to compile and simulate. Here is my code for code for PM: ...
JarvisLYu1's user avatar
1 vote
1 answer
46 views

Shift and continue not changing value

I am trying to implement a Cyclic Redundancy Check algorithm in Verilog. The algorithm will take the data and then find the modulus with respect to the the quotient polynomial. My problem is that in ...
Rezef's user avatar
  • 93
0 votes
3 answers
67 views

How to use variable wire data as an integer data for part select? [duplicate]

I am trying to control the width of data bus using part select. But, the following error occurs: r_count is not a constant. Is there a way in which I can use the ...
Rezef's user avatar
  • 93
-3 votes
0 answers
37 views

How to pass each coefficient value to 8 DSP slice in parallel filter design using verilog [duplicate]

For parallel architecture (8 tap) filter needs to be designed using 8 DSP slice and one SRLC32E Ip. I have written module code and test bench, but I am unable to get how to pass each of 8 coefficients ...
superb ranjeet's user avatar
-1 votes
1 answer
46 views

Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog

I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
superb ranjeet's user avatar
0 votes
1 answer
60 views

Ice40 SB_IO primitive input has glitches

I am trying to implement SWD protocol on ICE40 USB stick using Verilog. I have designed the SWDIO as inout in my program whose direction is controlled by a wire ...
Ravi's user avatar
  • 9
-1 votes
1 answer
101 views

Logical AND vs Bitwise AND for single bit and multibits [duplicate]

What is the functional and physical difference in using Logical AND ( && ) and Bitwise AND (&&) over singlebit and multibit signals. Below shared cases. case 1: A[3:0] & B[3:0] = ?...
DonMano's user avatar
  • 11
0 votes
1 answer
48 views

How can I make addition in Verilog wraparound?

I'm creating an ALU in Verilog, and I would like overflow to be dealt with by wrapping around to lower values. For example: ...
Connor's user avatar
  • 389
0 votes
1 answer
29 views

Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code

Here's the Verilog code for my UsedBeforeAssign module: ...
Tokubara's user avatar
  • 125
0 votes
1 answer
61 views

Why isn't my addition in Verilog overflowing?

I'm testing a basic ALU in Vivado using a testbench. One of my tests checks that overflow works correctly. The test has the following form: ...
Connor's user avatar
  • 389
0 votes
0 answers
43 views

How to use IF/ELSE conditions in xemacs verilog-mode /*AUTO_TEMPLATE();*/

When using autoverilog to instantiate modules the character @ defines the module number. How do I instantiate many instances of the same module and tie some of the ...
Nazar's user avatar
  • 3,142
2 votes
2 answers
107 views

Verilog UDPs : What basic mistake am I making?

I've been designing digital logic in Verilog (and more recently SystemVerilog) since 1998 but I have never had much use for user-defined primitives (UDPs) as they're generally non-synthesizable. Well, ...
jdb2's user avatar
  • 33
1 vote
2 answers
122 views

Getting an empty netlist after synthesis of I2C slave in Vivado

I'm getting an empty netlist after running the synthesis on the I2C Slave. The inputs (SCL, RESET) and the ...
Sushant Chachadi's user avatar
1 vote
1 answer
43 views

I2C slave: how to change control of SDA line from testbench to DUT to act as output?

...
Sushant Chachadi's user avatar
2 votes
1 answer
75 views

Need help debugging Verilog I2C slave code

As you can see in the waveforms and the code after the start (busy line goes high) condition occurs, I start sending the slave address bit by bit in the testbench through the ...
Sushant Chachadi's user avatar
1 vote
1 answer
61 views

Unable to open input file in Verilog

I'm having trouble running my Verilog code. Here is my code: module hello(A,B); input A; output B; assign B = A; endmodule And here is my testbench: ...
Afonso Britto's user avatar
0 votes
0 answers
66 views

How to fix undefined modules error in Verilog? (Nandland)

I am trying to run a synthesis on the Verilog code that I copied line-for-line from two different Nandland tutorials: Seven Segment Display UART Receiver Every time I run a synthesis on each project's ...
Christian Aguillon's user avatar
0 votes
1 answer
83 views

The timing issue with FPGA, after synthesizing this code, the total hold slack is a negative number [closed]

...
dodo_123's user avatar
2 votes
1 answer
46 views

Verilog: Self bitwise logical operation [duplicate]

I want the output out variable to be the output of 4 input AND gates, and the input variable is input [3:0] in; Is there any ...
Aryan Gupta's user avatar
1 vote
2 answers
65 views

Why don't signals change in For loop in Verilog?

I am trying to write memory elements using for loop. The for loop runs, and I get the value of ...
Zerox's user avatar
  • 33
3 votes
2 answers
140 views

How can I get rid of warnings in Verilog code for 32-bus 8:1 mux?

...
Johonathan's user avatar
1 vote
1 answer
53 views

What's the correct way of port declaration while instantiating modules in Verilog HDL?

From what I know, if we need to instantiate module1 in module2, then I need to declare all the ...
Killjoy's user avatar
  • 111
0 votes
1 answer
45 views

Why does this Verilog testbench not undergo a race condition?

This is the testbench in question: ...
Killjoy's user avatar
  • 111
1 vote
1 answer
45 views

Why does multi-input AND gate output give x-propagation?

...
Johonathan's user avatar
1 vote
1 answer
45 views

How do I figure out if my Verilog code output was generated out of race condition?

Apart from physical observation, is there a way to know if my code will undergo a race condition? For example, the following code has a race condition because both ...
Killjoy's user avatar
  • 111
1 vote
1 answer
68 views

Why is my testbench not driving any output?

In my testbench, I have connected the net z to the output of the seq_det module: ...
Killjoy's user avatar
  • 111
0 votes
1 answer
42 views

What's causing this error in synthesizing and inferred latches warning?

I have two issues with my code: This is the module that's showing an error in line 11 curr_state <= rst_n ? next_state : A; during synthesis: ...
Killjoy's user avatar
  • 111
0 votes
0 answers
47 views

How do I use conditional compilation in Xilinx Vivado?

I want to conditionally include one of three files if the respective macro for that file has been defined. Normally I would define the macros in a separate file, say ...
Killjoy's user avatar
  • 111
0 votes
1 answer
87 views

Assign a new (default) struct to a current struct

System verilog allows defining a structure type with variable initialization. That's is when I declare a struct type, the struct's members are already initialized. I was wondering if there is a way to ...
Nazar's user avatar
  • 3,142
0 votes
3 answers
74 views

Determine which clock of a compound sensitivity list triggered always block

I am trying to implement a non-synthesizable dual-clock FIFO in Verilog (solely for testbench purposes). Since the FIFO has to operate correctly even when both clocks toggle precisely at the same ...
firegurafiku's user avatar
1 vote
1 answer
72 views

How do I create a 2D array in Verilog?

I want to use a 2D array in a Verilog testbench. I tried it this way: ...
Killjoy's user avatar
  • 111
1 vote
2 answers
144 views

Error shifting a binary number in Verilog

I want to shift a binary number, for example 001011010 to 101101000 or 0000111001 to 1110010000. I wrote Verilog code but getting error. ...
Johonathan's user avatar
1 vote
1 answer
72 views

What's the purpose of "functions" if they can be replaced by "tasks" in Verilog HDL?

In Verilog, a task can do everything that a function can along with having other features. Then what's the purpose of having ...
Killjoy's user avatar
  • 111
0 votes
0 answers
144 views

SPI slave on FPGA

I am a newbie in FPGA domain and trying to learn as I develop my own verilog code. As Part of it I was trying to implement a SPI slave on icestick FPGA. Below is my code. IN this code for testing ...
Ravi's user avatar
  • 9
1 vote
1 answer
83 views

What am I doing wrong with this 2x2 Karatsuba Multiplier in Verilog HDL?

I am trying to implement a 2x2 karatsuba Multiplier which I will be using as a base case for a higher bit multiplier. Here's the code: ...
Killjoy's user avatar
  • 111
3 votes
1 answer
488 views

Why is my Karatsuba multiplier not giving right answers for large numbers?

I tried to implement 16-Bit Karasutba Multiplier in Verilog HDL. It gives me right answers for small numbers, but it's incorrect for large numbers. Can someone point out what's wrong? Here's the ...
Killjoy's user avatar
  • 111
1 vote
1 answer
49 views

How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?

I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
Killjoy's user avatar
  • 111

1
2 3 4 5
38