Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

Filter by
Sorted by
Tagged with
3 votes
3 answers
764 views

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what ...
user avatar
0 votes
0 answers
48 views

Verilog state machine, state does not change

Below is my code in which i want to shift the data serially out from the fpga in state "transfer". However when i simulate it, the state does not update. It is stuck in "update state.&...
user avatar
0 votes
2 answers
61 views

Synthesis of Blocking Statements in Verilog - time required for circuit to complete

This question is purely about synthesized verliog, not simulated. I have read that blocking assignments are executed in order, but also that blocking assignments assign values to the RHS immediately. ...
user avatar
1 vote
0 answers
48 views

Don't understand why tweak changes inference from distributed RAM to block RAM

In ISE 14.7 with the following code, the synthesizer infers distributed RAM, with warning xst:3218 citing an asynchronus read ...
user avatar
0 votes
0 answers
70 views

FPGA: issues with synthesis and implementation of quad SPI flash controller

I have written a state machine to act as a quad SPI controller for W25Q128JV Serial NOR flash ICs from Winbond. I tested the design in simulation and the waveform looks as expected based on the ...
user avatar
  • 182
1 vote
1 answer
74 views

Array Sum Not Synthesizing

I'm writing a FIR filter in Verilog, but the circuit does not synthesize. I've tried many different things, but ultimately it doesn't seem to want to synthesize the sum of an array. I have tried ...
user avatar
-1 votes
0 answers
29 views

SystemVerilog indexing issue: Erroneous design and duplicated register/latch removal in Lattice Diamond

I use Lattice Diamond (Linux, 64-bit, Version 3.12.1.454) with Lattice Synthesis Engine (LSE) in SystemVerilog-mode, with a Verilog-only design (not mixed). I was indexing a reg in Lattice Diamond the ...
user avatar
0 votes
1 answer
27 views

Conditional compilation of Verilog based on parameters

I have created a SPI controller in Verilog and I want to support all 4 SPI modes (clock phase and polarity options). It's easy enough to do this by changing the always block to be posedge or negedge ...
user avatar
  • 182
2 votes
1 answer
73 views

Correct way of estimating delays in FPGAs

What is the correct way of estimating delays when doing operations in Verilog? For example: reg [31:0] a, b; ... wire [31:0] res; assing res = a + b; The above <...
user avatar
  • 913
2 votes
1 answer
48 views

VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?

I am reading the code for an AXI Slave provided by Xilinx (here below). I am wondering why they declare all outputs as wire and then assign them to an internal ...
user avatar
-1 votes
0 answers
42 views

Verilog FSM Moore Design '111' pattern

Hi I was wondering if anyone could offer their advice. I am designing a FSM Moore code using Verilog HDL, that outputs 1 when three consecutive 1's are detected for all other instances the output ...
user avatar
0 votes
1 answer
53 views

Which of two Verilog lines is preferred?

If we want a modulus 10 counter (counts from 0 to 9), we can write this: reg [3:0] cnt = 0; always @(posedge clk) cnt <= (cnt==9) ? 0 : cnt+1; optimization is ...
user avatar
  • 13
0 votes
1 answer
30 views

Modelsim Altera not working [closed]

Hi i'm new to verilog designing and i'm trying to simulate but modelsim doesn't even load the design, i'm glad if someone could help, thanks. ( counter and contatore are two modules that i included in ...
user avatar
  • 1
1 vote
1 answer
43 views

How can one pass values to a bus in Verilog without first making a wrapper bus?

I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
user avatar
  • 35
-1 votes
0 answers
64 views

How to instantiate multiple modules into a top level module?

I am trying to make an NCO, using a DFF, ALU, and LUT modules that I have written. I can get the module to run, but when I run the testbench I get undefined values for my output every time! What am I ...
user avatar
-1 votes
0 answers
59 views

How do I implement half wave symmetry for sine wave generation in Verilog?

I want to generate a sine wave using a look-up table of 1024 points. If I use half-wave symmetry, I only need 512 points in the LUT. I tried implementing this using Verilog but the output is not ...
user avatar
1 vote
1 answer
54 views

SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
user avatar
  • 21
0 votes
2 answers
97 views

Lattice Diamond - trying to pipeline but tool is fighting me

I am trying to pipeline a 1-bit signal that has to travel pretty far across the chip (an ECP5 FPGA). The software is Lattice Diamond. The Verilog looks like this: ...
user avatar
-1 votes
1 answer
53 views

Verilog: Can I chain nonblocking assignments?

I'm trying to find the most human-readable way to pipeline some logic in system verilog. Most of my delays are routing delays. Is it valid to write something like this? ...
user avatar
1 vote
0 answers
73 views

Amplitude modulation on FPGA

I'm trying to implement amplitude modulation on a Xilinx Vivado using Verilog HDL, but can't seem to get the proper output. Can anyone point out what I am doing wrong? This is in reference to my last ...
user avatar
2 votes
1 answer
60 views

ISE Design Suite simulation problem

I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit ...
user avatar
  • 173
3 votes
1 answer
83 views

Is it necessary to take into account the actual state of a combinational circuit's signals to calculate its maximum delay?

I'm doing an exercise in which I need to calculate the maximum delay of a 1-bit full adder. In a full adder, the slowest path is the carry_out. Here is how I have designed it: Let's suppose all gates ...
user avatar
  • 913
1 vote
1 answer
55 views

SystemVerilog ring oscillator simulation with different delays

I am currently encountering issues with my ring oscillator simulation in SystemVerilog, which I cannot explain. Toolchain: ...
user avatar
2 votes
1 answer
96 views

What does it mean when there's a minus sign in front of a signal?

What does it mean when there's a minus sign in front of a signal? For example: reg [8:0] A; reg [4:0] B; wire C; assign C = -A[4:0] <= B; What's the meaning of ...
user avatar
2 votes
1 answer
60 views

Hardware implementation of Verilog Block & Non-blocking FSM

I'm doing a FSM question from here: https://hdlbits.01xz.net/wiki/Fsm1s I have implemented 2 different FSM using non-blocking and blocking for this question. Non-blocking: ...
user avatar
-2 votes
1 answer
78 views

Am making a 32bit adder but "X" is outputted after every addition

Am very new to Verilog and am completely lost and don't know why this doesn't work, any help is appreciated. Am making a 32bit adder by using only Half adders but I can't seem to make it work. am ...
user avatar
0 votes
1 answer
54 views

Verilog "bus switching"

Sorry I am not an expert with Verilog. I come from a software background. I have RAM sharer/multiplexer that I am creating which can take "command requests" from 3 different sources (1. VGA ...
user avatar
  • 115
2 votes
1 answer
124 views

FPGA: Verilog synthesis and Simulation - Open Source Appoach

I've been taking an CS Engineering Course where I've chosen minors in Electrical engineering. I'm a total noob here and no idea what's basically going in chip/FPGA Design process. I wished to ask if ...
user avatar
0 votes
1 answer
49 views

Fifo/shift register starting value duplicated

Can someone tell me why i got a duplicated start value in simulation for this implementation of shift register in verilog code : ...
user avatar
-5 votes
1 answer
99 views

What is toggle? [closed]

...
user avatar
0 votes
1 answer
106 views

JK flip flop gate level description in Verilog gives Z output

Im trying to implement a jk flip flop gate level in verilog using nand gates but for some weird reason i dont get a proper output. Here is my jk flip flop module: ...
user avatar
  • 9
0 votes
2 answers
66 views

Where do the procedural block etc. lie in Verilog timing region?

Where do the procedural block, fork - join, and specify-endspecify block lie in the Verilog timing region? Rough guess is Active or NBA region.
user avatar
0 votes
2 answers
132 views

FPGA counter works in simlation, not in hardware

I'm trying to implement an synchronous 4-bit counter in Verilog on the DE10-Lite (according to the Intel Lab Exercise 4). The design works fine in simulation (counts from 0-15 repeatedly), but in ...
user avatar
2 votes
1 answer
77 views

Non-constant index in a synthesizable Verilog deserializer

I would like to represent a Deserializer 4096 to 4 in a more efficient way than declaring a counter and assigning sequentially the 1024 cases. I have faced errors in trying to assign a non-constant ...
user avatar
0 votes
1 answer
53 views

How do I assign one of the outputs of a module to the output of a different module?

...
user avatar
  • 1
0 votes
1 answer
173 views

How to use ODDR output inside sub modules without connecting it to output buffer or port?

I am using Xilinx VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45) and vice versa at 1G. I instantiated two PCS/PMA core (1G/2.5G Ethernet PCS/PMA or SGMII v16.0), ...
user avatar
0 votes
1 answer
71 views

How does Virtual I/O Core work in Vivado?

I've recently started to learn programming in Verilog by using Vivado simulator and I noticed that the testing/checking part of your Block Design plays a very important role in obtaining the final ...
user avatar
0 votes
1 answer
77 views

Passing Unpacked Array of Packed Array as task arguments

task xyz(output op, output bit [width-1:0] write_data []); I have my task xyz definiton in an interface. I want to call this ...
user avatar
2 votes
1 answer
98 views

Does declaring Verilog arrays with indices in different directions makes any difference?

My question is about how you should declare Verilog arrays. As far as I read till now arrays in Verilog can be declared in two ways: Like this: array1[0:7] Or ...
user avatar
0 votes
2 answers
168 views

Verilog modulus operator % for non power of two (Synthetizable)

I would like to have a synthesizable and optimized solution for the modulus operator in Verilog (%) for the nonpower of two integers. cnt_mod <= cnt % 3; For ...
user avatar
2 votes
2 answers
94 views

Parametric bit-width assignment in Verilog

I would like to create a parametric bit-width assignment in Verilog. Something like the following code: ...
user avatar
0 votes
1 answer
61 views

Is the L298N H-bridge in FPGA (Intel DE0-Nano-SoC) compatible?

I am trying to write a code that controls various DC-motors through a multi L298N H-bridge using FPGA (Verilog or VHDL). I have a PWM signal generated right now, but can't figure out how to write to ...
user avatar
  • 1
0 votes
1 answer
46 views

Exporting Xilinx ISE simulation results into text file

(Using ISE Design Suite 14.7) I have been trying to export the simulation results into a text file or CSV file, but could not find a way to do so. I want to print output (in 20-bit signed decimal) at ...
user avatar
0 votes
1 answer
72 views

How does verilog treat multiple if block inside always_ff

If I have two if statements inside always_ff block, such as. ...
user avatar
0 votes
1 answer
111 views

FPGAcontrolling VGA: why does the monitor show a right triangle and not an isosceles one?

I'm trying to draw on a monitor by using an FPGA (SPARTAN 3A) and by considering a monitor with 640x480@60 Hz of resolution. In my code, I would like to start from a certain pixel (320,190) and to ...
user avatar
  • 13
0 votes
1 answer
146 views

What is the logic behind the behaviour of reg in Verilog?

I know SystemVerilog and now I'm trying to learn pure Verilog. I find the way reg works to be rather odd. I thought wire is used ...
user avatar
  • 25
0 votes
1 answer
98 views

RTL to Gate Level Design - Verilog

I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
user avatar
-1 votes
1 answer
74 views

What is the difference between a sinc3 and a sinc6 filter?

I have implemented a sinc3 filter in Verilog as follows. Now I am trying to implement a sinc6 filter using the same methodology. I am thinking to just increase the number of accumulators and ...
user avatar
2 votes
1 answer
100 views

What is the function of " *| " operator in Verilog?

What is the function of the "*|" operator in Verilog? ...
user avatar
1 vote
3 answers
367 views

Can I combine <= and = in a always @ clock block?

I want to implement this approximate(*) absolute difference design in a clock block and I want to calculate it within one single clock cycle: (*): Approximate because it's correct at an error of 1 (...
user avatar

1
2 3 4 5
34