Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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How do I write the top module for this Verilog code

I am writing Verilog code for A 4-bit BCD adder. I am having trouble wringting the top module and understanding how to call the other modules into the top module. Here are my codes. ...
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33 views

How to Use Addresses with Single Port RAM on FPGA

I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
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Demo of designing a modern CPU in Verilog/VHDL [closed]

Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
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Unexpected Behavior: i2s L/R clock only works under arbitrary conditions?

I'm new to Verilog (and HDL at all) and working with a Cyclone II EP2C5 Mini Dev Board in Quartus II (version 13sp1 to be compatible with my cheap FPGA). I use the below two modules (one mostly just a ...
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Simulating RV32I ALU + load/store instructions using verilog

I'm writing a Verilog code to simulate RISC-V RV32I ALU and Load/Store instructions in Verilog. It contains of 5 parts: regfile.v- which contains the 32*32 registers required for RV32I, decoder.v- ...
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1answer
14 views

SystemVerilog Assertions syntax error unexpected |->

I'm starting to use SVAs for formal verification. I run QuestaSim2019 and I can successfully import uvm_pkg (is it needed to use assertions anyways?): as I do ...
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43 views

Confusion in Sequential circuit

I was asked to write a verilog code about the SLE shown in the picture above. I have wrote the code until satisfying the condition of LAT=0, however the other half of the truth table I couldn't ...
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1answer
16 views

how can i make compile stage shorter in VCS (synopsys) after logic changed?

if I changed few lines from a specific Verilog of design and now I want to recompile, can I compile just the related files or I need to compile the whole design again? i'm using VCS tool by Synopsys.
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260 views

Verilog Code: When should I bother making a detailed code if I can make it shorter?

I made 2 verilog codes for a BCD adder. On the first code: I made a carry look ahead adder module That adder module is then instantiated inside the BCD_Adder module to add two 4 bits Then I use my ...
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Can the following conditional assignment be done on a verilog localparam

parameter enum_e TYPE = VAL_0; localparam type INTERNAL_TYPE = (TYPE==VAL0) ? struct_a : struct_b; Thanks
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How to create a nested for-loop in Verilog?

I try to create a CRC module on Verilog. The CRC calculating use an LFSR and can be fully-sequential (with two cycles), semi-sequential (with one cycle) or parallel. I have already made sequential ...
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2answers
84 views

Efficient single cycle huffman decoding technique with wider input data?

I have a wider input data (Byte width) running in my system, and I'm implementing a huffman decoding on this incoming data. Since, the Huffman encoded words don't have the fixed length, hence I need ...
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What adder does the use of the operator + synthesize to when used in creating an adder module? [closed]

I want to find out what adder(ripple adder, carry look ahead adder etc.) does the operator + in verilog synthesize to when used in design an adder module. For example: ...
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33 views

my spi_interface code in Verilog is not working

I have written a spi protocol in Verilog for communication between a master and a slave device. the problem that I am facing is I've written its testbench and in the simulation, as you all can see ...
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64 views

my spi protocol in verilog is not working

I have written an spi protocol in verilog and it is showing error. here is the link from where i took the information for spi. https://www.nxp.com/files-static/training_pdf/26821_68HC08_SPI_WBT.pdf ...
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50 views

Vivado Simulator Error

I am simulating code in Vivado but it gives an error like this. ERROR: [VRFC 10-3180] cannot find port 'newsymbol_0' on this module ERROR: [VRFC 10-3180] cannot find port 'curr_0' on this module ...
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1answer
44 views

Displaying 4 different characters on a seven segment display with Verilog?

I'm programming a blackboard using Verilog. The hardware information is provided in the link above. My goal is to light up the seven seg. display such that I can see characters on the seg. display ...
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1answer
19 views

How to use Design Vision to find area overhead for gate level Verilog code with multiple module?

I'm using Design Vision to find area overhead for my FIR circuit, but the code is already in gate level and have more than 1 module. Here's the code ...
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1answer
28 views

I Need to Generate SMPTE / BDU Time-Code using verilog , but I don't understand some parts of the time-code itself

So as mentioned in the title I have to generate a certain custom EBU time code using verilog, I have found this website that explains time-code systems and it's properties,but the problem is i can't ...
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1answer
61 views

Systemverilog - Register Chain Simulation Problem

I wrote a Systemverilog code that gets an input and connects it to a chain of registers (I.E: a "word shift register"). The output is an array whose size equals to the number of registers + ...
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1answer
47 views

Verilog/System Verilog restrictions on generate block and continous assignment

I took the carry look-ahead code from link and modified it to be wrong. The part I modified are ...
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1answer
40 views

Half Precision Floating Point in Systemverilog

I have a 16 bit vector defined as: logic [15:0] x; In my simulation I want to assign x a half precision floating point number. For example: 7.42 Is there a simple ...
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1answer
43 views

Assigning a zero to a vector in Verilog

In Verilog, I have a vector element defined as: logic [ width_x - 1 : 0 ] x ; I want to assign the value 0 to x. Can I always safely use : ...
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48 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
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2answers
69 views

Verilog bit indexing

A signal is defined as : logic [width_x-1:0] x; I want to assign x a value where the second bit from the top is '1' and all other bits are '0'. For example, if ...
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2answers
48 views

Understanding “Verilog default:’1”

I have a few questions about what this code does and how it works: x <= '{default:'1} ; What is the purpose of the "default" keyword ? What is the ...
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55 views

Verilog for loop - genvar vs int

When creating logic using a for loop, Verilog requires the loop index to be declared. I've seen examples where it's done with either "int" or "genvar" keywords. For example: ...
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Assigning to a parameterized 2d Verilog array

I have a Verilog array defined as : logic [ 0 : num_elements - 1 ] [ element_width - 1 ] some_array ; I want to assign every array element with a vector that is ...
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1answer
116 views

Apostrophe in Verilog array assignment

I've seen a Verilog example that assigns values to an array as follows : array = '{'{0,1,2,3},'{4,5,6,7},'{8,9,10,11}}; What's the purpose of the apostrophe (') ? ...
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1answer
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Strange Waveform Using FPGA with NI myDAQ

I am testing my Microsemi FPGA with a NI myDAQ and am getting some strange waveforms. All that I am doing is inputting a 3Vpp square wave at 10kHz and expecting the same output since my code is just ...
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2answers
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How can I improve my testbench for testing a 1024x4 RAM memory in Verilog

This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog". Basically, I have modified the previous solution in an ...
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1answer
48 views

How to use “AND” statement in Verilog

I am trying to create a counter that starts counting when a start signal goes from 0 to 1. Then, I want the counter to keep counting until both the start and stop signal are 1. Once both signals are 1 ...
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43 views

JK-flip flop using gate level description in Verilog give me a timming error

I still playing in the lowest Verilog level (gate level). I found this post: Is it possible to create a working JK-flip flop using gate level description in Verilog in that I could understand that ...
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1answer
45 views

Unknown error in Verilog

I am currently getting an error saying that my "counter_2" is not a constant. I am also getting a syntax error when I use "<=" with my counter_2. I've attached screenshots of my ...
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53 views

verilog program will only work if sensitivity list is (posedge clock)

I have a program in Quartus Lite 19.1 that will only work if a particular always block uses posedge of clock sensitivity. If I try to use an (star) sensitivity list then it does not, even though this ...
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1answer
116 views

Why should we not change inputs to a sequential circuit (Moore machine) at the clock edge?

The code included here takes a bit stream of binary digits, Least Significant Bit (LSB) first, and outputs the two's complement of the complete stream, also LSB first. A Moore State diagram is ...
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1answer
41 views

Trying to measure a pulse width and then send pulse of same width using Verilog

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods ...
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3answers
54 views

Using a counter to count how many clock cycles a signal is high using Verilog

I want to use a counter to count how many clock cycles an input signal is high. The issue I am running into is that once the input signal returns back to zero, my counter resets which causes my output ...
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1answer
38 views

Active Low LED and Active Low Switch behavior on FPGA counter-intuitive

I was following a tutorial to get started with Libero SoC with MicroSemi SmartFusion FPGA. I coded a small LED toggle module ...
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1answer
83 views

Verilog, problem understanding gate-level

I know that the code I am going a publush is terrible and pointless, just I am playing trying to go deep in verilog, deep to gate behaviour... Well, this is the pain code: ...
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2answers
60 views

In verilog is legal to implement a reset using assign?

I am trying to add a reset to a counter and I have this code, that syntethize perfectly: ...
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1answer
51 views

Verilog assign breaks the synthesis using Icestorm

well, i have this code that is giving a warning "Warning: No clocks found in design", and the FPGA is not doing nothing after flash: ...
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1answer
48 views

Why I can not copy a content of register to another one in “always” block in Verilog?

well, I have this code, that is working perfectly: ...
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1answer
43 views

Error handling two posedge signals in “always” block

I have a problem with an "always" block in Verilog. First let me present the code: ...
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1answer
211 views

24-bit binary to 32-bit bcd

I'm trying to write a 24bin-32bcd BCD counter. Can anyone explain how to implement it ? Here is my code: http://tpcg.io/JOHf4IFj but it needs to be checked. I have some problems with "valid" ...
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1answer
38 views

What difference do blocking and non-blocking assignments have on a single-line assign statement?

always @(posedge clk) count = count+1; and always @(posedge clk) count <= count+1; what difference do ...
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1answer
49 views

How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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41 views

pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
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33 views

ModelSim does not run until “$stop” command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ...
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36 views

Time to Digital Converter using FPGA with Coarse Counter in Verilog

I am currently using Verilog to program an FPGA and create a time-to-digital converter. What I am trying to do is measure the time interval when a square wave is high and then convert this to a binary ...

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