Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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I'm using a moore design pattern in verilog for a traffic light controller and all my output are displaying Z's

I am creating a traffic controller in verilog with a N/S light and E/W light that runs off of T that changes ever 20th rising edge of the clock. When I run the code the T changes correctly; however ...
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traffic design verilog hdl running into high impedance (z) issue

Below is my implementation for a traffic light four-way street and its test bench. Whatever I do, I keep getting "z" as my output. I do not know what to fix. ...
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Where did I code my multiplier wrong?

I've wrote a verilog code for Multiplier (8bit). I'm not getting the right result. Kindly tell me where i went wrong. ...
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Problem with PIPO Register - Verilog

I'm building a PIPO register to implement on a fpga. I have written the code below, but there is something wrong with my register module I believe. The value of Q won't save. My intention was that Q ...
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PSpice Model Editor Not Giving .dll and .lib Files for VerilogA Module

I am trying to learn how to import VerilogA Modules into PSpice using the Model Editor. For now I am starting with a simple VerilogA model of a capacitor so I can learn how to use the Model Editor and ...
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How to solve xilinx error ''Simulator:793 - Unable to elaborate instantiated module Half_Adder''?

I am making 2-bit multiplier using half adders in verilog in Xilinx ISE 14.7, but I am getting the error. The modules codes are shown below: ...
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Why is my Verilog code for Mealy-type sequential circuit not working?

I am supposed to write code for a circuit which outputs (z) 1 whenever the 2-bit input (x) is either 00 or 11 for two consecutive clock cycles. I feel like I'm close, but I can't figure out where I'm ...
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59 views

How to pack oddly sized chunks of data into 128-bit FIFO

In my FPGA project we get a 100-bit wide vector on each 100 MHz clock cycle from a 10Gbps receiver. I can then compress it to 75-bit wide vector due to some particulars of the data. I would like to ...
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Verilog conditional assignments without using procedural blocks like VHDL with/select

I am trying to find a way to conditionally assign values to a signal in verilog similar to the with/select in VHDL. So far I found two ways https://www.chipverify.com/verilog/verilog-4to1-mux. This is ...
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How to implement a continuously scanning multi-channel system in Verilog

I currently have a multi-channel system where each channel is receiving a pulse at different times. I want whichever channel receives its pulse first to act as the reference to then measure the time ...
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Signal connected to multiple drivers error in Verilog

I have only assigned the values to RegMem once. ...
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Datapath and Control Design

I am learning how to model a datapath and control design in Verilog, and I have taken an example of multiplication through repeated addition. Following is the output I am getting: 0 x x 35 0 x 45 ...
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Barrel shifter in verilog

I am new to verilog . I have instantiated a 4-bit barrel shifter in my top module design. shift_mag is the amount by which i am shifting the input. ...
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Will the Boolean equation change when we reduce the CMOS transistors in a static CMOS logic?

We are doing a project about a multiplier. Two of my teammates are assigned to make the transistor level designs of the adders, subtractors and few barrel shifters. My prof has told me to make a ...
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How to implement neural network using FPGA? [closed]

I want to design neural networks using FPGAs and make neuromorphic chip. Is there a tutorial or course to learn how to do that and to implement neural network using FPGA especially for evaluating the ...
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1answer
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Asynchronous FIFO design with PULSE synchronizer

I'm trying to understand various implementations of asynchronous FIFO from the following link https://inst.eecs.berkeley.edu/~cs150/sp10/Collections/Discussion/Honors/Honors14_1PP.pdf In the slide 7 ...
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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2answers
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Is it a good practice to define TRUE/FALSE constants in SystemVerilog?

Is it a good practice to define TRUE, FALSE, HIGH, LOW, ENABLE and DISABLE constants/defines/parameters in separate file and use them in expression ...
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57 views

Verilog testbench for inout

Can anybody please help me out with how to write test benches for inout ports in Verilog? I can't instantiate them as reg type variables in the test bench.
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Single Value range is not allowed in packed dimension

I have been reading about packed and unpacked dimensions in systemverilog from https://www.chipverify.com/systemverilog/systemverilog-arrays, in the following code I just want to use a memory array ...
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1answer
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How to parameterize a clock divider?

The best clock divider is a PLL inside a FPGA. But the number of PLLs are limited. And sometimes using of counter to divide a clock is justified: ...
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1answer
46 views

Verilog - Use integer constant to define signal width

I have a module which takes two parameters, ParameterOne and ParameterTwo. I use their ratio a lot, so I gave it a name ...
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2answers
50 views

Truncate in verilog

Given [15:0] number (there is no fractional part, only integer). How do I truncate lower two bits [1:0] and round it off to closest possible value. Consider a case where no overflow happens. Need to ...
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UCN -1 error in Design Complier synthesis

I have a block for 2's complement in Arithmetic module of a ALU. In the netlist synthesized by Synopsys Design compiler, I find that the 2's complement block output LSB is assigned to input LSB. ie, ...
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48 views

Coarse counter giving incorrect pulse length measurements at high frequencies

I am using a simple counter to measure pulse length. I have copied the code below, but the counter increments by 1 at each positive edge of the clock. Once the counter is done incrementing for that ...
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2answers
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Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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Module not giving correct output when the input is changed - verilog

I am trying to implement a 32-bit floating point divider. When I give only the mantissa as input, the divider gives correct output whereas when I change the input to 32-bit floating point number(...
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2answers
333 views

Verilog odd behavior with multiple edge detect

So I'm a newbie to Verilog. I decided to purchase a nice board (a Terasic DE0-CV) and teach myself some Verilog. And I'm seeing some strange behavior that I can't explain. I lifted some code out of ...
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182 views

Multiple driver error for SystemVerilog initial value

In my code I have an always_comb block coded as follows: ...
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Intel De1-SoC VGA controller in verilog

I am trying to write a vga controller for D1-SOC boards with 640*480 resolution at 60hz. I did a modelsim simulation with it and it seems to be working correctly, but when I program it on fpga it is ...
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1answer
26 views

How to rewrite ULCO error compare between genvar and int?

Trying to propagate a valid signal to one of several destinations I write the following code. The problem is there is a ULCO error (Unequal length in comparison operator) between the genvar ...
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Pipelined designs with outputs in differentes delay clocks

I have a pipelined design that ends in 13 clock cycles when the input value is not close to zero, but when the input is close to zero, the design only needs about 4 clock cycles, because of all the ...
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1answer
54 views

Model running slower than RTL in SystemVerilog

I'm testing an RTL implementation of a certain block from a 3rd party company in SystemVerilog using Questa. The block is fairly large and my block which acts as a wrapper around it is also large. The ...
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1answer
94 views

Johnson counter using structural modelling in verilog

I'm trying to build a 4 bit johnson counter using JK flip flops and structural modelling. For the FF's themselves I'm using behavioral code and then instantiating them inside the counter module which ...
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1answer
72 views

Verilog Counter is not working

I am a beginner in Verilog and my counter is not working. I'm not sure what I'm doing wrong. Below, I will type my code. ...
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2answers
140 views

How to derive an exact 10Hz clock from the generated clock?

How do I go about getting an exact (or as close as possible) 10Hz clock from the generated clock? The master is 100MHz. I have used this 32-bit register to make a clock as close as possible to 10kHz ...
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How should TDQS pin be driven?

I am confused with how TDQS and TDQS# pins be driven in verilog syntax ? I suppose these two pins are of ...
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1answer
42 views

New (for me) wire range syntax [(1)-1:0] in Verilog

I think this is quick question and assume the range of the wire is 1, but I wonder why they used the following syntax, maybe I am missing something else and would like to know your thoughts. ...
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1answer
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What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?

I couldn't find anything in the Verilog-2001 standard about this. For example, the following code works (Xilinx ISE): ...
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help me solve concurrent assignment error in verilog for the code given below?

Error is concurrent assignment to a non-net "c" is not permitted. ...
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1answer
44 views

Doubt in verilog [duplicate]

I have a doubt what is 4'd0 meaning in this program? ...
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1answer
49 views

Setting Pulldown on the PMOD Pins (Nexys A7)

Ive created a keypad scanning project with Verilog. The waveform works great! But it did not work in practice. Through troubleshooting I found that it will work if I add external pulldown resistors to ...
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1answer
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Doubt in non-blocking regarding order of execution

If I have theses statements: output reg [7:0] cnt; initial cnt=8'b00000001; always @(posedge clk) begin cnt<=cnt<<1; cnt[0]<=cnt[7]; end Now in this ...
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31 views

Doubt in non-blocking statement verilog

Suppose i have 2 non-blocking statements as follows: reg x,y; initial begin x=10; y=20; end and if I execute this: a) ...
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1answer
48 views

Copying Queues to Dynamic Arrays

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Concatenation with shift operator on concatenated array

I am relatively new to SystemVerilog and have found myself having to dig through quite a bit of it for work. I have come across a statement as follows: ...
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44 views

How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?

I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: ...
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89 views

What happens if we use non-blocking assignment <= inside of always @* block?

In verilog, we are supposed to use blocking assignment = in conjunction with always@( * ) to build combinational logic, but what happens if we use non-blocking assignment <= inside of always @* ...

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