Stack Exchange Network

Stack Exchange network consists of 174 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

0
votes
1answer
27 views

Verilog Include Statement Error

I'm trying to teach myself Verilog. I have some previous experience using VHDL. I am using Lattice Diamond as my environment. I successfully created and simulated a full adder. I now want to use this ...
0
votes
0answers
25 views

Generating a specific sequence of signals in Verilog with timing requirements

I am a beginner in Verilog, and as a part of a project, I have to send a sequence of signals to a chip in order to program one of its parameters. This Verilog code will be synthesized on an FPGA, and ...
0
votes
1answer
23 views

Initial register value in synthesized design is always 0

I'm using Altera Cyclone IV EP4CE6 as my FPGA. Compiling the design in Quartus Prime 18.0.0 Lite Edition. The State register in the below module appears to be 0 ...
0
votes
0answers
47 views

Help to translate verilog code lines to vhdl

I tell you that I am new to this forum, I have limited knowledge of vhdl, but I am a novice in verilog. A couple of days ago I'm trying to translate a module from a verilog project to vhdl, but this ...
0
votes
0answers
35 views

AES Sub Byte subsitution in four clock cycles

I am trying to implement AES in verilog using 32-bit data path, but I am not able to subsitute the 128-bit in just four clock cycles, my code requires five clock cylces, Here is the small portion of ...
-1
votes
0answers
92 views

algorithm to implement 48bits unsigned integer division in hardware

R = A / (A + B) < r% (A * 100) / (A + B) < r A and B are 48 bits unsigned integer. A and B are retrieved from hardware onchip memory. r is a 5 bits unsigned integer range from 0 to 31 r is ...
4
votes
4answers
1k views

sequence detection, why use SM?

The accepted way for implementing a sequence detector is with a state machine. why implement a SM when (it seems) any sequence detector can be implemented with logic demonstrated below (ASIC and FPGA) ...
-1
votes
1answer
38 views

Signed and unsigned numbers in verilog

I understand the concept of fixed point and multiplying signed with unsigned by sign extension the unsigned number with 1 bit of '0' so it will be signed always positive number, But my question If I ...
0
votes
1answer
33 views

Unable to diagnose StX fault in Modelsim

I'm unable to figure out why Modelsim is giving me a StX fault for this testbench. I'm just creating a counter and simulating a device that returns the MSB of the counter. Any help in figuring out ...
0
votes
2answers
61 views

What does these Verilog line of code mean?

I'm looking at this code: https://github.com/hgeisse/eco32/blob/dfd24eb13387f16b7da99a2285df023f446a676a/fpga/experiments/de2-115/memctrl-32/sim/memctrl-1/ramctrl/ramctrl.v and I've found two lines ...
1
vote
1answer
50 views

Multiplying signed to unsigned binary numbers in verilog

How can I multiply a signed number to unsigned number in verilog for example: a = 6'b111111 ; //which is means -1 as it is signed b = 6'b111111 ; //which is means 63 as it is unsigned I want the ...
1
vote
2answers
89 views

Why 4 regs to control a FSM? Verilog

I'm studying an SDRAM controller (in Verilog), which uses 4 reg to control a FSM. I couldn't understand why they use 4 regs instead of 2 (state and next_state). Here's the piece of code: ...
0
votes
0answers
37 views

ALU not working in Verilog MIPS Single cycle implementation

I have written the following code in Verilog which for the time being caters to only a subset of R-type, load word and store word instructions in the single cycle implementation based on the diagram ...
0
votes
1answer
26 views

warnings “Xst: 1710 or 1895” in ISE14.7

i have a module, written in verilog, that gives me couple of warnings e.g. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed ...
0
votes
0answers
41 views

How to connect outputs of functions to a multiplexer?

New to Verilog. I have a multiplexer / ALU that I want to perform the "adding" operation using a ripple carry adder. (essentially, I want to add SW[7:4] with SW[3:0] and store it in ...
-1
votes
2answers
75 views

Can I use 8 bits out of 16 bits as signed bits in verilog?

Generally Verilog takes the first bit of any bit pattern as signed bit. I know that -4 can be represented in signed representation as ...
0
votes
0answers
26 views

Ferroelectric Capacitor model using verilog-a

I am trying to develop a behavioral model of a ferroelectric capacitor using verilog-a. The ferroelectric material is HfO2 in between the capacitor plates. I know the polarization hysteresis formula ...
0
votes
2answers
44 views

how to handle a data set with negative values in verilog?

Suppose I have the following data set FFDD FFF5 0006 0007 0007 FFFE FFFD So far what I have studied is that verilog stored data in ...
0
votes
1answer
18 views

Instantiate sub module according to input value

I want to instantiate a sub module according to input value but this seems impossible. I tried these methods: method 1: always @ -> cannot instantiate sub modules there. method 2: generate -> gives ...
1
vote
3answers
70 views

Types of finites state machine in FPGA design

There are 2 types of FSM: 1- block of combinational logic + clocked block that hold only the current state 2- clocked block For example, if we take a look to how an SDRAM controller is made, most ...
-2
votes
2answers
71 views

Ii need to get the remainder while dividing from 5 but I don't want to use modulus airthematic operator or a divider in verilog [closed]

I want to work with residue number system and make an ALU based on residue number system. So frequently I need to calculate the remainder and using modulo operator is not helping as it is not ...
-3
votes
0answers
39 views

Error 3566 in vhdl

I get the following error message: ERROR:HDLParsers:3566 - xst/work/hdpdeps.ref line 20 Invalid date/time (".vhd") found. When I press on ERROR I get to the Xilinx site and it can't find ...
0
votes
1answer
63 views

I write this module to arithmetic shift to left and right in verilog

this is my code: module zero(out,A,B); output signed[5:0] out; input signed[5:0] A,B; assign out = A[5:0]<<<2 + B[5:0]>>>1; endmodule ...
0
votes
2answers
51 views

Generate one-input pulse in Verilog

I'm attempting to port discrete schematics into a FPGA. In the schematics some AND gates function as short pulse generators, when input goes low output is enabled, until input propagates down an ...
0
votes
1answer
38 views

verilog behavior changes with part name in iverilog

So I'm trying to build a master-slave d flipflop in verilog, ...
0
votes
1answer
109 views

How many flip-flips would this code require?

H, I'm trying to understand the below code what how many FFs would be required when synthesis. TEST1. ...
0
votes
2answers
37 views

Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
0
votes
1answer
29 views

Verilog - Using 'define' to declare a constant created by a 'parameter'

Pardon the wordiness of the question's title. How would you accomplish the following. I have this parameter: parameter BUS_SIZE = 16; And I want to use it later ...
0
votes
0answers
23 views

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer

Using ALTLVDS_TX megafunction with a DS90CR485 Serializer Hello there, First of all I'm a beginner in FPGA programming and i don't know if my whole approach to this is wrong. I'm currently trying to ...
1
vote
1answer
94 views

Fpga communicate to pc through usb

I'm currently working on my thesis project on making a secure pendrive. For that I have to design an USB protocol implementation on an FPGA. But I don't know how to physically connect that USB core ...
0
votes
1answer
67 views

Problem in blocking and non-blocking - verilog

I have this code and I am having a problem in the product output, any ideas? I've tried a lot and it doesn't work.
2
votes
0answers
94 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
0
votes
1answer
38 views

FSM transition table from verilog code

I'm looking at this verilog code and it asks me to do a state transition table This is the answer, but it's using x=a and z=b and q=y. the thing i don't understand is why in the code does it say ...
0
votes
1answer
64 views

Modelsim: resume simulation future

I have long running simulation in Modelsim for VHDL/Verilog designs. I want to know are there any way to save current simulation progress and resume it somehow in later time?
0
votes
2answers
74 views

Connecting the following structure of multipliers and adders in an elegant way in verilog

I am attempting to write a synthesizable verilog (or Systemverilog) module. I also want to make the modul parameterizable, which has presented a problem when trying to connect the following structure ...
0
votes
1answer
55 views

Verilog nested for loop not behaving as expected

I am having trouble with a simulation of an 8-bit full adder i wrote in verilog. Basically I have two integers that I feed into the full adder, I add them together and I check if the result is as ...
1
vote
1answer
67 views

Creating a Counter in Verilog for Flashing LED on Lattice Starter Kit

I have a lattic X03LF starter board with 6900C FGPA. There are eight LED available on this board and a push button. The goal of my code is to design a 8 bit counter that increments whenever a button ...
0
votes
1answer
50 views

Can't Resolve Multiple Constant Driver[Verilog] [duplicate]

Can't Resolve Multiple Constant Driver Error (10028): Can't resolve multiple constant drivers for net "NumOfPixCF[31]" at Pixel_Tracking.v(30) Error (10028): Can't resolve multiple constant ...
2
votes
2answers
109 views

Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its ...
0
votes
1answer
45 views

LT-SPICE subcircuit programming

I want to create a SPICE subcircuit file for an electronic component. I have found the Verilog A code for the component, I want to know how to convert the Verilog A code to LTSPICE compatible ...
0
votes
0answers
53 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
0
votes
3answers
92 views

HDL code convention for register resets

When it comes to (synchronously) resetting registers in HDL (I'll use Verilog), is it considered bad practice to code the reset combinatorially? As far as I can tell, the following two snippets are ...
0
votes
1answer
73 views

Shift register using dff verilog

I want to create a shift register using d-flip-flop as basic structural element, code: dff: ...
1
vote
1answer
39 views

Verilog: MIDI receiver port fails when more than two keys are pressed at the same time [closed]

I'm designing a MIDI receiver port (using Altera CLPD MAX 7000S). The device samples the second byte it receives and outputs the binary value on an LEDs. The device works fine whenever I input MIDI ...
-2
votes
2answers
106 views

7 to 128 decoder in Verilog

I'm new to digital electronics and programming in Verilog particularly. I have programmed some basic programs like 2 to 4 decoder, and 4 to 16 decoder. But I am trying to make an image sensor and say ...
0
votes
2answers
88 views

Verilog problem on Spartan 6 board

I'm planning to do a waveform generator using an FPGA board (spartan 6 board from diychips), however I am new to verilog so I am encountering a bit of a problem. I created a sine-wave sequence using ...
0
votes
1answer
60 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
0
votes
2answers
65 views

(System)Verilog: extracting a smaller bus/vector from a larger bus?

What is the best practice for creating a bus, which is just extraction of certain bits of a larger bus. I do not want to store the index numbers to make the lookup in the generate-for if it could be ...
0
votes
1answer
62 views

Understanding Testbench Waveform for UART module

I have taken the following code for testing a UART module from https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html Can anyone explain what is happening in the ...
-1
votes
1answer
53 views

Debugging Gate-level Verilog Multiplexer

I've built a 4-1 multiplexer using three 2-1 multiplexers, but am having a lot of trouble debugging my code. I've tried using $display statements as rudimentary ...