Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Read and write simultaneously from different indices of an associative array in system verilog
Is it possible to read and write simultaneously (In parallel) from different indices of an associative array in System Verilog ?
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What's wrong with my taillight verilog design?
I'm working on a T-bird car taillight design code, here is my design:
B means brake, all lights on at break,
when turn left lights on sequence: 000000 -> 001000 ->011000->111000
turn right ...
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2
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If I need to access memory cell by cell, should I shift or index?
I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024;
reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially....
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1
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Implementing a Mealy Machine in Verilog
I have a piece of code that I don't understand:
always_ff @(posedge CLK)
state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate;
...
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SystemVerilog: selecting bits without storing calculation in variable
Is there really no way to select bits straight from a calculation without giving them a name and then selecting the bits from the name in SystemVerilog?
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Work library is empty after compiling Verilog source file in Modelsim [closed]
How I can solve this problem: my Work library is always empty after compiling a selected file in Modelsim?
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1
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Sampling data at 5 MHz with 50 MHz clock in Verilog
I'm trying to make a controller for the MAX31855 thermocouple IC. My FPGA works at 50 MHz and this IC works at 5 MHz, so I'm using a frequency divider to get the 5 MHz clock signal.
Now the IC is ...
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Extract a motion filter using camera movement in number of pixel and angle, in VHDL or Verilog
I have read some papers about the topic and searched some MATLAB algorithm. There is one called 'fspecial' in MATLAB. And it could return a Motion filter, when motion is given in number of pixel and ...
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How to Implement Clocking Wizard IP into Vivado Project
I am using Vivado (2017.4) and have been trying to experiment with the Clocking Wizard IP. I understand how to create a new IP but am not sure what to do with the HDL file it generates. I've looked at ...
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How to send a packet every n clock cycles in verilog?
I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
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Testbench for simple register file
I want to test my register file before connecting it to ALU.
So I wrote a testbench for my register file.
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System Verilog Coverpoint Bin for everything else that is counted towards coverage calculations
Setting a bin to default grabs everything else in the coverpoint, but the default bin is ignored in coverage calcuations. Is there anything similar to default that I can use for syntax that will ...
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CORDIC algorithm using Verilog
Here is my code to compute the sine and cosine of the input angle using the CORDIC algorithm:
Design code :
...
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1
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Need help understanding the status output generation of an ALU
I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model.
The thing I can't understand is the ALU is generating a "status" ...
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What is the difference between scalar array and vector array?
First question
Whether we declare the array as scalar or vector, we can access each element bit by bit. For example, we can declare two arrays below.
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Declaring vector variable in the Verilog not starting with the MSB(e.g,. reg var[0][20])
I am familiar to the syntax described in here
net_type [msb:lsb] list_of_net_identifiers;
reg [msb:lsb] list_of_register_identifiers;
For example, to declare the 32bits memory address, I could use ...
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Why the one-hot state encoding has an advantage in decoding compared to binary state encoding?
Before I asked the question, I've googled advantages of the one-hot state encoding compared to others such as binary and gray state encoding.
I could understand one-hot's advantages and disadvantages ...
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How to use the parameter in comparing the variable and constant value?
I've learned that using a parameter in defining a module is a good habit like having a default value for the parameter in C++ or other languages.
So, I've used a parameter value a lot but faced a ...
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1
answer
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Sending SPI signals to the Flash Memory through verilog FPGA controller, but not receiving anything from it, why does it happens?
As a school project I want to write a very simple controller for a flash memory in a IC board. The FPGA chip is Altera 5CEFA4F23C8 and the flash is MX25L3206E.
I did an effort to produce the SCLK, SI ...
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3
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High impedance in RTL Verilog
I am designing a shift register. It has a control signal called RD which is asynchronous (so I can't use it inside the procedural block). The whole point is my n-1 ...
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1
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Self checking test bench verilog
I am designing a ring counter with 8 bit input. I was successful in design and verifying it through a testbench module. Now I am asked to do the auto correction and self checking of the test bench. ...
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How to scale output of butterfly unit radix 2 for further stages?
I am designing 8 point FFT by radix 2 using verilog. I am using radix 2 butterfly unit with 8 bits input and so output. I expect to be 8 bit so that I can use this structure again and again for ...
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Usage of "initial" in Verilog module description
I'm writting a code and I have 2 dumb questions:
1- Is it a bad practice to use "initial" in the module description?
I'm asking this because I have a frequency divider with 2 signals (clk_in and ...
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Using generate statement in Verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
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system verilog 3d array ,cant insert data , what am I doing wrong?
Im trying to implement 2d convolution (8 bits each cell int he convolution so in systemV it's 3d) in system verilog,and I have trouble inserting data into the "result" array, and i dont understand ...
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Verilog - instantiation input port not connected in top level design but design is working?
I want to convert a verilog design into vhdl but i found a verilog module which I see no way to convert it, because the design itself makes no sense to me. The module entity is the following code ...
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1
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Concatenating from Block RAM in Verilog
I have instantiated a block RAM module using Block Memory Generator segment of the Xilinx IP Core. Alternatively, I have coded my own simple single-port RAM module, much like on page 33 of these ...
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2
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Synchronising signals of Verilog test bench with RTL clock
I have been given an interesting assignment. My task was to design a 4 bit up_down counter which has two controlling signals, up_down and load. The up_down decides weather the counter should be up-...
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2
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Very big matrix multiplication in FPGA
I'm working with convolutional neural networks and I have written a code to make the convolution of two 3x3 matrices. This is my code: https://www.edaplayground.com/x/6G7h
Now I want to make the ...
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Output internal reg to a .txt in Verilog
I would like to write an internal reg to a txt file.
I have tried something like:
...
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CPLD is (sometimes) not incrementing counter
I have this simple program running on the Altera EPM240 that’s sometimes not doing the counter increment.
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How does verilog evaluate conflicting assignments?
Is code like the following legal or would this give undefined behavior in case reset is set? Would the compiler turn the initial assignment into a conditional or first increment the counter, then ...
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Using $floor in Verilog
Verilog has a bunch of math system functions.
I'm trying to use $floor in my Verilog code but I'm getting this message:
System function call floor is not allowed here
Does anyone know why I'm ...
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<Verilog, FPGA> Priority encoder and normal encoder
I would like to ask some questions about inferring the priority and normal encoder using Verilog on the FPGA.
I've used the example codes from the book "advanced chip design practical examples in ...
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Question about Synthesizable For loop and Generate
I am using the Verilog language and Zedboard as a target board.
As far as I know, the for loop can be synthesized, and the synthesis tool translates the for loop as a sequence of duplicated ...
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1
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Verilog to Logic Diagram
I am trying to draw the logic diagram of this Verilog Code of a counter using mux, d flip flop, nand, and.
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bruteforce with Xillinx FPGA [closed]
How can I brute force a password list with xillinx FPGAs?
For example, I have a zip file that encrypted with password, I want to check password list with high speed to open this zip file. i want to ...
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1
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Verilog - how to overcome the fact that I cannot mixed edge and level triggers,writing to memory
I have a 32x32 ram module which i built, the simple code:
Verilog Code
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1
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807
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compare rising edge occured before or after an other edge with verilog
I would like to write a verilog code to generate RTL level for signal B as in the figure. It has been a long time since I wrote verilog at school so I am quite rusty at this.
Let's say I have two ...
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When and how to separate Control and Datapaths for hardware designs?
Must we always separate control and datapath during hardware programming? Are there any advantages? If yes then what is the basic methodology followed for this strategy? I am trying to interface an ...
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2
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FPGA Internal Timing constraint failing
I'm currently trying to implement an IP-Core on a Cyclone V 5CSEBA6U23I7 FPGA-HPS System using Altera Quartus II and TimeQuest Analyzer.
The Verilog code pasted below produces a timing problem, namely ...
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Verilog - Array of Inputs
Im new to Verilog, so please just dont blast me.
If in a module i declare as inputs' vector
[0:3]D
or
[3:0]D
What does it ...
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Verilog - Name is optional when instantiating primitive gates
Why is the name optional when instantiating primitive
gates, but not optional when defined modules are instantiated?
Example:
...
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What is the purpose of this Verilog code for implementing 3-port Block RAM?
LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented.
One particular troublesome point I have trouble with is how the register file is ...
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<Verilog> Mixed blocking & non-blocking assignment
I would like to ask three questions about blocking & non-blocking assignment.
The first question is that How the blocking and non-blocking statement works when they are combined.
following the ...
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Verilog simulation: How can I start my circuit after the reset signal is turned off?
I tried to implement the simple FIFO and its test bench.
FIFO testbench code:
...
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2
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Why Verilog doesn't introduce a FF for reg type variable in always@* block and why reg is allowed in combinational circuits
as far as I know, register (e.g., reg reg1) and register file (e.g., reg [3:0] reg2)
can be used in the always block whether it is a sequential (i.e., always @(posedge clk)) or combinational (i.e., ...
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always @* block in sequential circuit
as far as I know, always @* block is used in combinational circuit, and
the logic inside the always @* are sequentially executed regardless of the clock (asynchronous).
However, it seems that the ...
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Why Non-parallel but full case statement uses ROM not the MUX?
as far as I know, when the items in case are not parallel
it would compose a priority routing network not the multiplexing network.
In other words, it should uses multiple 2-to-1 MUXs to represent ...
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Question on UART parity check verilog source code
Why is parity_value equal to value of 1 ?
check_parity verilog source code
...
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