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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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1answer
37 views

Verilog - use a clock signal as a value in its own procedural block

I tried synthesizing the following code and was surprised to see that it doesn't work (at least with Vivado 2017.2). ...
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1answer
68 views

How to implement 32-bit adder logic using two 16-bit adders?

I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this. verilog code ...
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1answer
126 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
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6answers
18k views

Random bit sequence using Verilog

I want to generate a random bit sequence using Verilog. i.e. the random bit sequence would be composed of 1 and 0. Can someone guide me as to how to do it? Does anything equivalent of rand() in C/C++ ...
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0answers
36 views

Design mod 10 synchronous up/down counter using D Flip Flops [on hold]

I tried to design a Mod 10 synchronous up/down counter by using D Flip Flops in Verilog HDL language but was unable to do so succesfully. So can anyone guide me through the design and code?
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1answer
140 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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1answer
129 views

Verilog: cannot be driven by primitives or continuous assignment

Could someone help me figure out why I am getting such an error. The code below implements a 4 bit shift register adder which takes one bit at a time from each register computes the sum of the 2 bits ...
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1answer
76 views

Single-cycle MIPS processor in Verilog

I'm very new to Verilog and I've tried to create single-cycle 32bit MIPS processor. Instructions I want to implement are ...
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3answers
7k views

How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
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2answers
130 views

Interval measurement in Verilog

I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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0answers
33 views

Port name missing in module header in System Verilog

In System verilog, is it okay if a port name is not included in the module header but defined outside the header? Say, for example I have an input port i1 and it is to be included under a module h. ...
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2answers
50 views

Verilog latch occurring with instantiating modules with in a generate statement

I am trying to create a register file in Verilog. To do this, I am instantiating multiple instances of a register module I designed in a generate statement. Each module uses a different input and ...
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1answer
177 views

synchronous serial interface in verilog

i have a ADC (ADS1672 datasheet) (20MHz) with serial interface and xilinx spartan 3 XC3S400-208 (50MHz) in it's datasheet to data retrieval comes this: for that i implemented this code: inputs and ...
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1answer
43 views

Verilog : Using previous generate iteration's wire in current iteration

For background, I am trying to implement something like this: My idea was to use a couple of nested generate statements to first create each of the 4 stages, then the second to create each mux in ...
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1answer
109 views

Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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1answer
42 views

verilog-101 detect I can not y output

ı can not get y output for '101' detect ...
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1answer
48 views

How can i make an always statement run with initial values in verilog

I am trying to use this MUX in a MIPS Datapath design that i'm trying to create, but since i use an initial for these, they don't change and the always block is never triggered in the first clock, ...
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0answers
62 views

Bidirectional Counter implementation using internal counter

There was an assignment as follows: Design a two directional three-bit counter with the following functionality. the counter is changing its value on each positive edge of the clock. the counter's ...
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1answer
72 views

Register File for MIPS Processor

I am writing code for Register file (32 registers, each of 32 bit) for MIPS Single Cycle processor. I want writing to happen at the negative edge of the clock. As usual, reading can happen any time (...
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2answers
279 views

Verilog inout port

I have a doubt question. I know that I can use "inout ports" to connect to a pin, but can I use "inout ports" to connect internally 2 modules? I'm asking this because I have written an SRAM ...
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2answers
92 views

Is it better to combine logic for two flip flops in a single always block?

I have always used separate always block for infering different flip flops when they dont have much in common. ...
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1answer
28 views

Initial value for 32 bit register made using D F/F in verilog

I am trying to make a 32-bit register using 32 negative edge trigerred D F/F. Here is the verilog code for D F/F: ...
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1answer
213 views

Syntax error selecting a range from a range

I'm trying to run an old Bitcoin miner project in Vivado. The old code is written in Verilog and the rest of my project is in System Verilog. I have a syntax error I don't know how to solve. It ...
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1answer
141 views

Synopsys Synthesis with underlying modules as gate libraries

I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module. With setting -hierarchy option in write_file, I get all the modules ...
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1answer
35 views

How to read data from an .mif file in Vivado?

My knowledge on the subject is bare-bones. I created a .coe file and used Block Memory Generator to get an .mif file. I need to store the contents in the block memory and then use it. Following is my ...
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0answers
33 views

Round-Robin Arbiter Architecture from Efficient microarchitecture for network-on-chip routers

I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient ...
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1answer
51 views

In Verilog, How is a 4:1 Mux made using case statements without creating a D-latch?

Whenever I try to make a 4:1(32:8) mux in verilog using the following statement: ...
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1answer
54 views

When to use blocking and non-blocking assignments

I am having a really hard time to understand where to use blocking and non-blocking assignments. I have read many answers regarding this on this site and have also referred to book on Verilog by "...
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1answer
53 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
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2answers
138 views

How do I represent in Verilog a circuit with a resistor?

I write a piece of Verilog code: ...
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1answer
29 views

Understanding the Verilog Stratified Event Queue

I'm trying to understand how the Verilog scheduling algorithm works. The below example outputs 0, xxxx and not 1010. I'm not ...
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1answer
465 views

system verilog 3d array ,cant insert data , what am I doing wrong?

Im trying to implement 2d convolution (8 bits each cell int he convolution so in systemV it's 3d) in system verilog,and I have trouble inserting data into the "result" array, and i dont understand ...
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1answer
165 views

Interlacing Verilog and schematic in a FSM

I'm a noobee to HDL based design. I've built a Simple Dual Port memory using the fpga's IP tools and instantiated it in a schematic. I'm implementing a custom external cpu interface (with hand shake)...
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1answer
37 views

sdf generation using prime time

I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these ...
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2answers
472 views

backtick in verilog numeric constant

So I was writing some verilog in quartus and wondering why the heck it was misbehaving. I eventually discovered the problem was some constants where I had inadvertantly used a backtick instead of a ...
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1answer
912 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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1answer
41 views
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1answer
56 views

Arbiter Physical unclonable function

I do not understand why my verilog code doesnot produce output of arbiter puf when I am trying to implement on fpga. ...
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1answer
761 views

Reading a parameter value of module instance in verilog

I have an ALU module with a set of parameters used as opcodes. parameter ADD=0, SUB = 1, MUL = 2, DIV = 3; Currently building ...
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1answer
42 views

Verilog: Register File assignment not updating on clock pulse

I wrote some fairly simple code in Verilog to implement a 32-bit deep, 8-bit wide register file. However, when I actually run a behavioral simulation of the thing the two data-read lines (rd0_data and ...
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1answer
57 views

Lattice MachXO2 reset

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip. In the How to ...
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2answers
34 views

Unrelated change causes circuit simulation delta

I'm seeing some where differences in circuit simulation when changing what should be an unrelated module. I'm trying to understand what optimizations are going on here to cause this: ...
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2answers
67 views

Are there any free simulators for SystemVerilog?

Are there any free simulators available for a hardware design coded in SystemVerilog? In particular, I need SystemVerilog's dynamic arrays.
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3answers
217 views

Demodulation of a data

As seen in this picture, I have a circuit that has created those desired pulses in the output. There is a last stage in my circuit and that is: Translating the times that more pulses have happened to "...
3
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2answers
4k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
2
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1answer
65 views

What is need of transmission modes in Serial Peripheral Interface

I am going through SPI transmission for implementing in FPGA, While researching, In few articles such as https://en.wikipedia.org/wiki/Serial_Peripheral_Interface and this https://web.archive.org/...
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1answer
37 views

Can size of a module's port be input as a parameter in Verilog?

I have a hardware algorithm that compares two operands, each (keyBits) bits long, and returns a logical one if the first operand is less than the second, and returns a logical zero otherwise. This ...