Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Verilog counter delay in task not working
I'm trying to generate different delays in multiple places using task WAIT in a synthesizable module, and the code is as follows:...
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I2C slave PWM Verilog problems
I have been trying to get this I2C slave controller to work and send PWM signals, but I still can not drive the PWM. I think that it is an issue with the testbench on maybe how the slave controller is ...
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Synopsys Synthesis with underlying modules as gate libraries
I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module.
With setting -hierarchy option in write_file, I get all the modules ...
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How to select a handshake and code examples in verilog [closed]
I'm new to Verilog, and I was taking a look into the ready-valid handshake. I saw that this is the most used handshake, as it is simple to understand. However, I couldn't find the disadvantages of ...
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Verilog: only run an edge triggered always loop once per edge change
I'm currently working on a simple up counter triggered by the negative edge of a push button. If the button is held while pressed down, the counter gets stuck in the always block and increments by ...
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Verilog code for adder shows unknown results (X) for some reason
I wrote this code, and it doesn't give a known value for the sum (S[15:0] in the waveforms). Why is that?
Design:
...
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Verilog error: cannot be driven by primitives or continuous assignment
Please someone explain why I am getting below error from this code:
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Using generate statement in Verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
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What is the meaning of "e" in this timing diagram?
https://hdlbits.01xz.net/wiki/Edgecapture
What is the meaning of "e" in this timing diagram?
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Error: illegal Verilog output port specification
I am having problems with my Verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times, but I cannot ...
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Verilog variables updated only when assigned as an output
I am facing a strange issue, and I am not sure what is going on here:
assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]};
Where last 5-bits of output data ...
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Why I am getting one clock cycle delay in Verilog case statement?
I have a Verilog code here:
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Under which situation must a signal be defined as a reg?
For example, in this code. The answer is none of the signals must be declared as reg. So, if this is truly the case, then what is the use of this code? I think the ...
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Defining vector in Verilog
Given the following code:
module add16 (input [15:0] a,b, output[15:0] sum, output court);
Are both input a and ...
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sdf generation using prime time
I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these ...
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Interval measurement in Verilog
I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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Lattice Diamond Port 'direction' is unconnected
I am following the tutorial to turn on the LED on the embedded vision development kit found in:
C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v
...
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Why does it take so much time for compiling verilog HDL code in Quartus?
I am writing a verilog code in Quartus to encrypt AES-128bit.Every sub-module works well but when I compile the main module, it take more than 2 hours to complete with no error. Especially, when i ...
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Verilog output register not changing
I have to use combinational logic to write Verilog for a circuit schematic. However, my output registers, CLK1 and CLK2, do not change and are stuck at the initial values. What is causing this bug? ...
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Exporting Xilinx ISE simulation results into text file
(Using ISE Design Suite 14.7)
I have been trying to export the simulation results into a text file or CSV file, but I could not find a way to do so. I want to print output (in 20-bit signed decimal) ...
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SPI read of MAX31856 in Verilog
I am trying to read the K-type thermocouple temperature with MAX31856 in Verilog.
Configured the configuration registers CR0 & CR1.
The conversion result is stored in the registers 0xC, 0XD, 0XE. ...
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Can size of a module's port be input as a parameter in Verilog?
I have a hardware algorithm that compares two operands, each (keyBits) bits long, and returns a logical one if the first operand is less than the second, and returns a logical zero otherwise. This ...
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Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
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Signed representation of negative numbers in Verilog HDL by Samir Palnitkar
I'm reading about signed number representation and the book says
-6'd3 // 8-bit negative number stored as 2's complement of 3
Is there a reason as to why a ...
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Misunderstanding in sequential and combinational implementation, based on blocking or non-blocking behaviour
I have a very simple module that waits for the valid signal to become 1 and then sets the ...
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SystemVerilog output issue with "m" in a 5-to-1 Mux
I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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8 bit counter from T Flip Flops
I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
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Designing a sorting network with an FSM as opposed to combinational logic
During this semester I have been spending a bit of time learning how to use Verilog. I took on a project to develop a sorting network for 1024 32-bit numbers and tried to develop the circuit by ...
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Is there a way to make the Verilog port declaration based on a macro value?
Basically, what I am trying to achieve is that,
There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized.
But I also want to create dedicated output ...
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Why is this power-on reset generator Verilog module getting optimized out?
I am trying to write a Verilog module that generates a power-on reset signal for a few clock cycles. I am synthesizing using Lattice iCEcube2 + Synplify Pro targeting an iCE40 HX1K on the Nandland Go ...
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Why does the waveform simulation go wrong using structural D flip flop in Verilog?
I am designing a state machine in Verilog HDL to identify a specific number sequence. I must make it in structural.
When I design the DFF with a behavioral style, everything is great, but with the ...
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Verilog - arithmetic comparison with part of register
I am new to Verilog/HDL and I have a problem. Whenever I try to perform an if/else conditional between two registers of different size the synthesis completes but I am never able to get it to fit.
...
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Problem with getting data properly from memory using RoCC interface
I am using RoCC interface to communicate with Memory in chipyard.
The memory has the width of 64 bits, and I need to read the first 64 bits and put it in lower register and then read the next 64 bits ...
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Can anyone please take a look of this Verilog HDL code? Does it look strange by any means?
I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
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Radix-4 multiplication problem with unknown simulation output
I'm writing code in Verilog that takes A and B as 8-bit inputs and multiplies them using the radix-4 method.
When I execute the ...
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Designing a Moore sequence detector using three always blocks
Trying to implementing a Moore state machine using three always blocks. The Moore state machine has two inputs (ain[1:0]) and one output (...
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Verilog- Why is my state machine output arriving one clock cycle earlier?
I'm writing a Verilog code for a state machine with 4 states. state 0 is buffer time of 1 microsecond. state 1 is trig pulse for 10 microseconds. in state 2, the input is read. If the input is high ...
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Trying to measure a pulse width and then send pulse of same width using Verilog
I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods ...
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Using if/else syntax for assign statements
I have a wire to which I assign a complex right-hand-side expression with lots of bitwise operations. This right-hand-side expression is quickly becoming long and ...
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Sampling data at 5 MHz with 50 MHz clock in Verilog
I'm trying to make a controller for the MAX31855 thermocouple IC. My FPGA works at 50 MHz and this IC works at 5 MHz, so I'm using a frequency divider to get the 5 MHz clock signal.
Now the IC is ...
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Implementing a Mealy Machine in Verilog
I have a piece of code that I don't understand:
always_ff @(posedge CLK)
state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate;
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how can i make compile stage shorter in VCS (synopsys) after logic changed?
if I changed few lines from a specific Verilog of design and now I want to recompile, can I compile just the related files or I need to compile the whole design again?
i'm using VCS tool by Synopsys.
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How does Verilog treat multiple if blocks inside always_ff
If I have two if statements inside an always_ff block, such as:
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How to make a waveform simulation in Quartus II from testbench module
I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
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Johnson counter using structural modelling in Verilog
I'm trying to build a 4-bit Johnson counter using JK flip flops and structural modelling. For the FF's themselves I'm using behavioral code and then instantiating them inside the counter module which ...
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