Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Difference between blocking and nonblocking assignment Verilog
I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:
We normally have to reset flip-flops, thus every time the clock makes the ...
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How can I generate a schematic block diagram image file from verilog?
I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
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VHDL vs. Verilog [closed]
VHDL and Verilog are some of the HDLs used today.
What are the advantages and disadvantages of using Verilog or VHDL over the other?
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Why are inferred latches bad?
My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided....
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Stress testing an FPGA's power supply
I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
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synthesizability of the code
I got this piece of weird code in a text book. Simulation seems fine, the synthesis run returns an error on line #7... someone please comment on this piece of weird code... Iverilog has no issue ...
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Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
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How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
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Free IDE for VHDL and Verilog [closed]
I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
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How do I learn HDL
I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
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What is the "+:" operator called in Verilog?
I am going through a Verilog test case, and I found this statement:
assign XYZ = PQR_AR[44*8 +: 64];
What is the "+:" operator known as? I tried to find ...
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Difference between >> and >>> in verilog?
What is the difference between >> and >>> in verilog/system verilog? I know that ...
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Generate a 100 Hz Clock from a 50 MHz Clock in Verilog
I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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Implement serial port on fpga (verilog)
I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections?
I have a Spartan-3AN evaluation board and I'm ...
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Asynchronous reset in verilog
I am new to verilog and having a bit of trouble getting along with it.
I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
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Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?
I have the little doubt related to initializing condition in Verilog.
Like in given statement:
...
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Blocking vs Non Blocking Assignments
I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
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'1011' Overlapping (Mealy) Sequence Detector in Verilog
I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog.
The FSM that I'm trying to implement is as shown below :-
Verilog Module :-
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How to read hexadecimal data from text file and write in into memory in verilog?
I have a text file named "Hex_data.txt". I want to load content of Hex_data.txt into a variable name RAM in verilog. When I try this, I get an error that the text file can't be found. Where is this ...
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Random bit sequence using Verilog
I want to generate a random bit sequence using Verilog. i.e. the random bit sequence would be composed of 1 and 0. Can someone guide me as to how to do it? Does anything equivalent of rand() in C/C++ ...
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What is supposed to happen in Verilog if a signal of one width is assigned to another signal of a different width?
As in these two cases:
wire [3:0] A, B;
wire [4:0] C, D;
assign A = C; // larger width to smaller width
assign D = B; // smaller width to larger width
What ...
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Verilog: Check for two negedges in always block
i try to do something like this:
always @ (negedge speed_dec or negedge speed_inc)
begin
do something
end
This doesn't work as checking for 2 negative edges ...
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How do I calculate constant values across several modules at compile time in Verilog?
I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
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always @(*) vs. assign
I may have used these interchangeably without thinking, and did not have any problems.
always @(*)
output = input ? a : b
or
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Is it possible to create a working JK-flip flop using gate level description in Verilog
I am attempting to create a working JK flip flop using gate level description in verilog. Although, the design is successfully compiled and simulated, the outputs to the FF are always unknown.
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Why is my output showing as X?
I have written a Verilog file for memory error correcting that takes an n-bit input and using certain logic, it would output an n-bit output that would possess the corrected code. Here are my modules ...
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Are Verilog if blocks executed sequentially or concurrently?
I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent.
For example, are the ...
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Counter in verilog
i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx.
Can someone tell me if there is something wrong in this code?
...
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Why do my tests pass using a "wrong" JK flip-flop model?
I have a testbench written for a JK flip-flop. Below I have the correct circuit that passes the testbench and another circuit which passes the testbench as well. Is there something wrong with my ...
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27 points median filter
Edit:
I successfully made it work, but the algorithm not efficient
I taking the date coming in to my block, pipeline the data for how much points I need to median filter (for example 31), take all ...
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Verilog code synthesis error
I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is:
...
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De2 Board reading sensor reading
I wish to operate a LVMAX Sonar EZ1 sonar rangefinder.
They say
With 2.5V - 5.5V power the LV-MaxSonar EZ1 provides very short to long-range detection and ranging, in an incredibly small package. ...
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Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog
I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
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Indexed Vector Part select operator +: usage in verilog
I am using Indexed Vector Part Select in a Verilog test case and i am very confused with this.
when we have described
input [415:0] PQR_A;
output [63:0] ABC;
...
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What is the purpose of this statement in Verilog?
I see syntax quit similar to this very frequently:
4'd0
Sometimes it is associated with an assign statement:
assign S0 = 2'b00;
I tried searching online however I could not find any sources.
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Can an FPGA design be mostly (or completely) asynchronous?
We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.
I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
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Verilog: XOR all signals of vector together
Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out:
...
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SystemC vs other HDLs [closed]
I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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FPGA starts working after irrelevant changes, why?
I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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Is there a way of conditionally triggering a compile-time error in verilog?
I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating ...
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How to assign value to bidirectional port in verilog?
I'm trying to use a bidirectional port in Verilog so I can send and receive data through it. My problem is that when I try to assign a value to the port inside a task, I keep getting an error.
What is ...
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Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
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How are Verilog "always" statements implemented in hardware?
The Verilog always statement, namely
always @(/* condition */)
/* block of code */
executes the ...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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Why can't regs be assigned to multiple always blocks in synthesizable Verilog?
The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It'...
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What is the difference between an array and a bus in Verilog?
I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following?
What is the difference between an array and a bus?
...
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Open Source verilog synthesizer
I'm looking for an open source verilog synthesizer. I am using Icarus Verilog as a verilog simulator. Originally I was going to use it for both simulation and synthesis, but found out the tool no ...
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Setting FPGA pins as virtual
I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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