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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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14
votes
3answers
88k views

Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following: We normally have to reset flip-flops, thus every time the clock makes the ...
8
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3answers
7k views

How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
4
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5answers
1k views

Stress testing an FPGA's power supply

I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
95
votes
11answers
93k views

VHDL or Verilog? [closed]

VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
29
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10answers
53k views

Free IDE for VHDL and Verilog [closed]

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
42
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2answers
12k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
24
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7answers
5k views

How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
22
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5answers
41k views

Why are inferred latches bad?

My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided....
6
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2answers
12k views

Implement serial port on fpga (verilog)

I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections? I have a Spartan-3AN evaluation board and I'm ...
7
votes
1answer
35k views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
9
votes
3answers
5k views

Is there a way of conditionally triggering a compile-time error in verilog?

I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating ...
8
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2answers
28k views

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that ...
4
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2answers
11k views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
4
votes
6answers
18k views

Random bit sequence using Verilog

I want to generate a random bit sequence using Verilog. i.e. the random bit sequence would be composed of 1 and 0. Can someone guide me as to how to do it? Does anything equivalent of rand() in C/C++ ...
0
votes
2answers
1k views

De2 Board reading sensor reading

I wish to operate a LVMAX Sonar EZ1 sonar rangefinder. They say With 2.5V - 5.5V power the LV-MaxSonar EZ1 provides very short to long-range detection and ranging, in an incredibly small package. ...
5
votes
2answers
19k views

How to read hexadecimal data from text file and write in into memory in verilog?

I have a text file named "Hex_data.txt". I want to load content of Hex_data.txt into a variable name RAM in verilog. When I try this, I get an error that the text file can't be found. Where is this ...
2
votes
1answer
129 views

How do I calculate constant values across several modules at compile time in Verilog?

I have a Verilog module that uses three instances of the same low-level module, called 'pole'. The instances are identical, except for a constant offset value, which is provided by the top level. ...
2
votes
1answer
7k views

What is supposed to happen in Verilog if a signal of one width is assigned to another signal of a different width?

As in these two cases: wire [3:0] A, B; wire [4:0] C, D; assign A = C; // larger width to smaller width assign D = B; // smaller width to larger width What ...
1
vote
2answers
1k views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
0
votes
2answers
589 views

Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is: ...
39
votes
9answers
8k views

Can an FPGA design be mostly (or completely) asynchronous?

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere. I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
10
votes
3answers
28k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
8
votes
3answers
37k views

How are Verilog “always” statements implemented in hardware?

The Verilog always statement, namely always @(/* condition */) /* block of code */ executes the ...
13
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2answers
49k views

What is this operator called as “+:” in verilog

I am going through verilog test case and found a statement assign XYZ = PQR_AR[44*8 +: 64]; What does "+:" operator be known as. I tried to find this on google ...
8
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4answers
5k views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
1
vote
3answers
18k views

Verilog output reg vs output wire

I am currently designing an asynchronous FIFO for learning purposes. I have the module done but I am having some second thoughts about it. Firstly I've been thru some articles describing how to ...
5
votes
2answers
1k views

Beginner with fpga and timing issues

I got myself a spartan-3an evaluation board in order to learn fpga programming and some verilog. It's taken a little while to stop seeing it in terms of a sequential programming language and to start ...
4
votes
2answers
8k views

Why can't regs be assigned to multiple always blocks in synthesizable Verilog?

The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It'...
4
votes
6answers
3k views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
2
votes
1answer
14k views

Accessing rows of an array using variable in Verilog

I have a module I'm writing in Verilog that effectively contains a 16 by 10 2D array. At a given point and "row", what I want is to have that data pushed to a net that can be read outside of the ...
9
votes
4answers
16k views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
8
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3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
6
votes
3answers
4k views

Clock problem with Spartan 6

I have a clock divider implemented as follows: ...
3
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3answers
23k views

Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
3
votes
1answer
712 views

What FPGA chips support verilog-ams or verilog-a

I am having trouble finding explicit evidence on any FPGA vendors website that their chip supports the verilog-ams and/or verilog-a. Do all these chips support it, or is it only "mixed-signal" chips, ...
3
votes
1answer
1k views

What exactly do we write in a test vector?

My professor has asked me to write Test vectors for the controller shown in the circuit below: We have not implemented the controller as of now. I want to understand what exactly we write in a test ...
2
votes
1answer
16k views

sequence detector in verilog

I have the task of building a sequence detector Here's the code : ...
1
vote
4answers
545 views

Usage of “initial” in Verilog module description

I'm writting a code and I have 2 dumb questions: 1- Is it a bad practice to use "initial" in the module description? I'm asking this because I have a frequency divider with 2 signals (clk_in and ...
1
vote
3answers
351 views

Calculating rolling sum of array

I am trying to implement a rolling average of an array of 12 bit samples in SystemVerilog. New samples are generated and shift into an array via a clocked flip flop. The goal is to have a register ...
0
votes
1answer
275 views

fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it ...
0
votes
2answers
886 views

Verilog modules: estimating power consumption before physical design

What can a designer do to get an idea of how much power a various module with consume? It seems like there should exist some decent heuristics to go about doing this, else we would have to wait until ...
5
votes
3answers
3k views

non-blocking assignment does not work as expected in Verilog

I have a very simple Verilog code and it does not seem to work as expected: Here is my code: ...
5
votes
1answer
7k views

How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector. If it is on, show Y = SW[15:8], if it is off, ...
5
votes
4answers
4k views

What is the purpose of pre-synthesis simulation?

I have used Verilog to develop RTL representations of synthesizable digital circuits, and have recently been using Verilator to run simulations of these. My understanding of Verilog semantics, ...
4
votes
3answers
23k views

Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?

I have the little doubt related to initializing condition in Verilog. Like in given statement: ...
3
votes
2answers
4k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...
3
votes
2answers
881 views

Unexpected patterns in Verilog $random

I have a Verilog test bench that monitors a 64-bit bus and should randomly schedule a flipped bit (packet corruption) to happen every 1-in-X packets. I was surprised to find it not injecting any ...
3
votes
2answers
1k views

Generate flip-flops using only combinational logic

Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation. My initial attempt, which ...
3
votes
1answer
4k views

How to find the critical path delay of a big combinational block

I have a 54*54 multiplier, i want to find the critical path delay.how do i go about, should i clock the module in order to find the delay?
3
votes
2answers
10k views

$random in Verilog doesn't seem to be working

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random ...