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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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Initial Block is Sythesizable!

I came across a lot of posts saying that initial block is not synthesizable in Verilog HDL.Even I followed the standard reference (https://link.springer.com/content/pdf/bbm%3A978-81-322-2791-5%2F1.pdf)...
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181 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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1answer
52 views

Issue with Booth multiplier

I coded a 4 bit booth multiplier in Verilog. It is working fine for Multiplicand Multiplier + 0 to 7 0 to +7 & -1 to -7 But it does not ...
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1answer
141 views

Synopsys Synthesis with underlying modules as gate libraries

I am trying to synthesize my Verilog modules into 1 top module which contains all the modules extracted into 1 top module. With setting -hierarchy option in write_file, I get all the modules ...
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0answers
259 views

Analysis of Branch misprediction in MIPS 32 bit architecture

I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below. I am considering the case where there is already a branch delay slot ...
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218 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
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737 views

How to create .vcd file for power analysis through xpower(xilinx 10.1) software?

I had a verilog code. I did xpower analysis without .vcd file, with .vcd file(using simulate post route & route model) and .vcd file (using ...
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32 views

Round-Robin Arbiter Architecture from Efficient microarchitecture for network-on-chip routers

I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient ...
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1answer
122 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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2answers
124 views

Interval measurement in Verilog

I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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100 views

Unexpected behaviour of implication operator in SVA

There is an issue I face while using an implication operator in one of my code examples. This code can be found at https://www.edaplayground.com/x/4fVz Code Summary In my code, I have defined ...
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3answers
146 views

what's the correct way to add counter inside flip-flop?

I want to count number of "clock enable" signal inside flip flop. I learn from tutorials that the output value should be assigned for all combinations of input. However I don't know how to add ...
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1answer
424 views

CRC hardware implementation

What is the difference between these two implementations as the feedback is in first implementation the last reg only but the second implementation last reg xored with the input bit, so, what is the ...
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2answers
309 views

Using Memory values in Verilog / VHDL

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself. The target function of the block can ...
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61 views

Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should ...
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1answer
747 views

Sending SPI signals to the Flash Memory through verilog FPGA controller, but not receiving anything from it, why does it happens?

As a school project I want to write a very simple controller for a flash memory in a IC board. The FPGA chip is Altera 5CEFA4F23C8 and the flash is MX25L3206E. I did an effort to produce the SCLK, SI ...
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1answer
527 views

Question on UART parity check verilog source code

Why is parity_value equal to value of 1 ? check_parity verilog source code ...
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1answer
482 views

Verilog modulus operator for wrapping around a range

My background is in software and I'm new to (System)Verilog so when tasked with implementing a caesar shifter (shift each letter in a string by N letters, wrapping around if necessary e.g. ABCXYZ ...
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88 views

Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
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0answers
1k views

Verilog SRAM controller

I am trying to implement a SRAM controller module. It's structured as follows External connections: extA[18:0] -- address extIO[7:0] -- bidirectional input/output OE,WE,CE -- control signals ...
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0answers
264 views

Matlab and HDL code generation

I have a project involving audio on a Xilinx Spartan6 FPGA. The goal of the project is to make an audio processor using HDL (mostly educative and for fun). It's basically a pipeline of audio effects ...
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2answers
494 views

Controlling MAX31855 via SPI with Verilog from FPGA

I am trying to create an SPI between the MAX31855 - thermocouple to digital converter, and my FPGA - DE0. I'm understanding the gist of SPI, and the timing requirements of the MAX31855. My problem ...
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0answers
916 views

Unable to assign value in an always-block

NO IDEA that the value of register just never changes whatever the clock and the cases are. but no problem while compiling. WHAT is happenning? It is really confusing... ...
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0answers
121 views

Reduce routing avoiding multiplexer

I'm implementing a systolic array for a project, every Processing Element (PE) contains many multiplexers in cascade due to absolute value subtraction and conditional operator, the code looks like ...
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0answers
127 views

col not declared issue{Verilog}

I am having a problem here can't make this code compile. It is a 4x4 keypad scanner with a 20ms debouncer. It gives error "Error: 'col' has not been declared" Any suggestion? ...
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0answers
240 views

What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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0answers
467 views

problem with CPLD and 24C16 EEPROM interface

Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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0answers
6k views

How to assign a pull-up/down resistor in Verilog for inputs?

As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how. I have written my code that works just fine but when I connect my XC3S400 to ...
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0answers
922 views

verilog file with own library import into cadence

I need to import a verilog netlist into cadence. I'm writing the verilog file with my own developed application. I defined several library elements inside the netlist file which are not part of the ...
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1answer
58 views

Mod-3 asynchronous up counter using T flip flop in verilog

Design: ...
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1answer
48 views

How can i make an always statement run with initial values in verilog

I am trying to use this MUX in a MIPS Datapath design that i'm trying to create, but since i use an initial for these, they don't change and the always block is never triggered in the first clock, ...
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62 views

Bidirectional Counter implementation using internal counter

There was an assignment as follows: Design a two directional three-bit counter with the following functionality. the counter is changing its value on each positive edge of the clock. the counter's ...
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1answer
51 views

In Verilog, How is a 4:1 Mux made using case statements without creating a D-latch?

Whenever I try to make a 4:1(32:8) mux in verilog using the following statement: ...
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1answer
50 views

My work directory in ModelSim is always empty. How can I resolve this problem?

I'm new to Verilog. I made a new ModelSim project and kept the default directory to work. Then I added .v (Verilog) files to the project. And after that I compiled the files. Compilation was ...
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1answer
37 views

sdf generation using prime time

I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these ...
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1answer
112 views

Verilog: cannot be driven by primitives or continuous assignment

Could someone help me figure out why I am getting such an error. The code below implements a 4 bit shift register adder which takes one bit at a time from each register computes the sum of the 2 bits ...
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1answer
37 views

Can size of a module's port be input as a parameter in Verilog?

I have a hardware algorithm that compares two operands, each (keyBits) bits long, and returns a logical one if the first operand is less than the second, and returns a logical zero otherwise. This ...
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1answer
34 views

Can a Verilog function return an array indexed from one to the value passed in as an input parameter?

If an input parameter to a Verilog function is integer "lg" then can the function return an array of integers indexed from one to (lg)?
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26 views

How to write the negation of 'a until b' property without using until (in SystemVerilog)?

I would like to write the negation of the property a until b (a and b being different ...
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2answers
45 views

Getting around two dimensional array prohibition

The textbook I just bought, Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar, says it's impossible to have a two-dimensional array directly, but someone who's used Verilog says ...
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0answers
60 views

Flexible way to define filepath in Verilog

Imagine I have a Verilog design with the following structure: ...
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0answers
27 views

Using Verilator for Co-Simulation

I want to simulate a home-brew CPU written in Verilog along with some "peripherals", like a "VGA monitor" and a keyboard, written in, let's say, Javascript. From my understanding, here's some possible ...
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1answer
44 views

Verilog Testbench - wait for specific number of clock cycle edges

In my testbench, I want to wait for two events in sequence: one after 60000 clock cycles and next after additional 5000 clock cycles I know I can wait for clock edges using statement @(posedge clk), ...
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1answer
137 views

how to do a shift/add multiplier in verilog?

I tried this ...
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1answer
45 views

How to use QSUB to submit jobs in parallel?

I would like to run thousands of simulations using qsub command, but I am not sure how to use it adding variables. Right now I have made this bash script to run my simulations, but it is too slow, ...
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1answer
50 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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1answer
99 views
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1answer
36 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
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1answer
64 views

Understanding signed numbers in Verilog

For my Verilog code, I am trying to define a 64 bit array, like this input signed [63:0] var_name This array is broken up such that it is 8 bytes, each with a ...
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0answers
31 views

Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...