Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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Constraining FPGA design on the lower level module

I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the ...
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Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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Verilog inout port

I have a doubt question. I know that I can use "inout ports" to connect to a pin, but can I use "inout ports" to connect internally 2 modules? I'm asking this because I have written an SRAM ...
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What is Warning: Replacing memory \MEM with list of registers?

I have this little code that displays a binary count on LEDs: ...
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Fast ADC interface with FPGA

I have to interface a fast ADC with an FPGA and then do the data processing. The FPGA used will be Zynq Ultrascale+ RFSoC ZU29DR. I have been given the information that ADC_clk = 4x FPGA_clk. ADC ...
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Johnson counter using structural modelling in Verilog

I'm trying to build a 4-bit Johnson counter using JK flip flops and structural modelling. For the FF's themselves I'm using behavioral code and then instantiating them inside the counter module which ...
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Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my ...
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FPGA and CPU design: Moving from ideal memory to real RAM blocks

I implemented the single-cycle MIPS design from "Computer Organisation and Design" in Verilog, shown below: I used my own "ideal" data memory implementation, which asynchronously presents the read ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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sdf generation using prime time

I have a stdcell library which has “.v” file which contains all Verilog RTL models for stdcells. This stdcell library also has a “.lib” and ".db" timing files with all the delay information for these ...
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Synchronous serial interface in verilog

I have an ADC (ADS1672 datasheet) (20MHz) with serial interface and xilinx spartan 3 XC3S400-208 (50MHz) In its datasheet to data retrieval comes this: for that I implemented this code: inputs and ...
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Analysis of Branch misprediction in MIPS 32 bit architecture

I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below. I am considering the case where there is already a branch delay slot ...
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Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...
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How to create .vcd file for power analysis through xpower(xilinx 10.1) software?

I had a verilog code. I did xpower analysis without .vcd file, with .vcd file(using simulate post route & route model) and .vcd file (using ...
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How to assign a pull-up/down resistor in Verilog for inputs?

As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how. I have written my code that works just fine but when I connect my XC3S400 to ...
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Verilog output register not changing

I have to use combinational logic to write Verilog for a circuit schematic. However, my output registers, CLK1 and CLK2, do not change and are stuck at the initial values. What is causing this bug? ...
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Designing a sorting network with an FSM as opposed to combinational logic

During this semester I have been spending a bit of time learning how to use Verilog. I took on a project to develop a sorting network for 1024 32-bit numbers and tried to develop the circuit by ...
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Verilog variables updated only when assigned as an output

I am facing a strange issue, and I am not sure what is going on here: assign output_data = {3'b000, cmd_state[1:0], w_data[2:0]}; Where last 5-bits of output data ...
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What's the correct way of port declaration while instantiating modules in Verilog HDL?

From what I know, if we need to instantiate module1 in module2, then I need to declare all the ...
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Why is my testbench not driving any output?

In my testbench, I have connected the net z to the output of the seq_det module: ...
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How can I fix the combinatorial loop alert in Vivado?

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How to give an input stimulus to the DUT in a testbench when we have a 10-bit input?

How do you get around this problem? I am spending a lot of time in giving a 10-bit input all the way from 1111111111 to 0000000000. How do I effectively write loops in my testbench when I am giving an ...
EngineeringStudent's user avatar
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Using behavioural modelling, how do I design a positive edge triggered T flip-flop with asynchronous preset and clear?

I am having trouble doing the above. I have written a little bit of code along with a testbench, and it requires some changes. I also need to add the conditions for preset. How do I do that? ...
Gun_Gani's user avatar
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Verilog code if else with localparam

What does the Verilog localparam X code below mean? From my understanding it is as follows: ...
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Getting error "A reg is not legal lvalue in this context"

I am trying to create a blockwave in SimVision, but I am struggling with the top-level module. I keep getting the same error and can't figure out the solution. The error is: A reg is not legal lvalue ...
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While do I get a compile error when I connect output reg of one module to input of another?

...
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Need some help with my Quartus code since it is not showing my waveform correctly because of an error

I need some help regarding some of my Quartus II work. This is the problem I have to solve. This my code for the 7 segment display and the multiplexer. I believe it is correct: ...
Minseok Park's user avatar
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1 answer
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Verilog contention with I2C port stretching - how to detect clock being driven low by slave when master is driving clock high

I'm trying to implement I2C on an FPGA, but I couldn't seem to figure out a way to detect clock stretching without external circuits. Is there any way that I can detect the wire (I'm using ...
Anthony Kung's user avatar
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CORDIC module for (0, 90)

I found this CORDIC Verilog code online. It calculates sine and cosine from (0, 360). I was thinking if there is a way to modify it to (0, 90) and then use 4 such CORDIC modules in a pipelined ...
blackblade's user avatar
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FPGA blocking assignments in always block not working properly

In the following setup I have created a custom clock through switch on Spartan 3E FPGA to toggle the LED states one by one. I have connected 8 registers with 8 LEDs. By triggering the clock through ...
Dipnarayan Das's user avatar
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SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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Amplitude modulation on FPGA

I'm trying to implement amplitude modulation on a Xilinx Vivado using Verilog HDL, but can't seem to get the proper output. Can anyone point out what I am doing wrong? This is in reference to my last ...
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Why is my FPGA clock so slow

To preface this I am a complete beginner with verilog and FPGAs in general. But I recently purchased a MAX1000 board to start learning things on and one of the first programs that I made was this: <...
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Verilog project - Binary to BCD - 0-49 2 digit display

I have an end of the year project where I must create an 4 operation ALU that outputs its result onto 7 segment displays in Verilog. 2 of those operations are multiplication and addition. Considering ...
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Verilog design to display character using "16x2 Character Display" IP from Quartus IP Library

I was trying to display a single character on 16x2 display. I created simple Verilog design for "Altera Cyclone V Development Kit". In the project I used "16x2 Character Display" ...
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Confusion in Sequential circuit

I was asked to write a verilog code about the SLE shown in the picture above. I have wrote the code until satisfying the condition of LAT=0, however the other half of the truth table I couldn't ...
Dynamic's user avatar
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how can i make compile stage shorter in VCS (synopsys) after logic changed?

if I changed few lines from a specific Verilog of design and now I want to recompile, can I compile just the related files or I need to compile the whole design again? i'm using VCS tool by Synopsys.
asif evgy's user avatar
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How to use Design Vision to find area overhead for gate level Verilog code with multiple module?

I'm using Design Vision to find area overhead for my FIR circuit, but the code is already in gate level and have more than 1 module. Here's the code ...
Irham Fahmi's user avatar
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390 views

SystemVerilog: copy a slice from a vector to another vector of different size

as per title, I want to copy a slice of fixed size from one vector to another, starting from a variable location. Example: ...
arandomuser's user avatar
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verilog program will only work if sensitivity list is (posedge clock)

I have a program in Quartus Lite 19.1 that will only work if a particular always block uses posedge of clock sensitivity. If I try to use an (star) sensitivity list then it does not, even though this ...
bryant p's user avatar
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Trying to measure a pulse width and then send pulse of same width using Verilog

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods ...
yer's user avatar
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27 points median filter

Edit: I successfully made it work, but the algorithm not efficient I taking the date coming in to my block, pipeline the data for how much points I need to median filter (for example 31), take all ...
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Inferring a pipelined divider in Verilog

I want to synthesize an integer divider in Verilog to divide 16-bit integers by 8-bit integers. I assume that the compiler will be way more clever than me when it comes to implementing the details of ...
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Why does the output of a register bank( designed by me in verilog) change after two clock cycles, even if input changes every clock cycle?

I have designed a register bank (pipeline register) to be used in a pipeline-architecture. The code of the register is: ...
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Round-Robin Arbiter Architecture from Efficient microarchitecture for network-on-chip routers

I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient ...
kevin's user avatar
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Interval measurement in Verilog

I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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Why 4 regs to control a FSM? Verilog

I'm studying an SDRAM controller (in Verilog), which uses 4 reg to control a FSM. I couldn't understand why they use 4 regs instead of 2 (state and next_state). Here's the piece of code: ...
Jose de arimatea's user avatar
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Unexpected behaviour of implication operator in SVA

There is an issue I face while using an implication operator in one of my code examples. This code can be found at https://www.edaplayground.com/x/4fVz Code Summary In my code, I have defined ...
Green's user avatar
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Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should ...
Hachani Ahmed's user avatar
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Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
Renegade243's user avatar