Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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94
votes
11answers
94k views

VHDL or Verilog? [closed]

VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
42
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2answers
12k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
39
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9answers
8k views

Can an FPGA design be mostly (or completely) asynchronous?

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere. I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
37
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7answers
3k views

Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, ...
29
votes
10answers
54k views

Free IDE for VHDL and Verilog [closed]

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
24
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7answers
5k views

How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
22
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5answers
41k views

Why are inferred latches bad?

My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided....
16
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2answers
1k views

Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
15
votes
7answers
13k views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
15
votes
3answers
93k views

Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following: We normally have to reset flip-flops, thus every time the clock makes the ...
14
votes
2answers
51k views

What is this operator called as “+:” in verilog

I am going through verilog test case and found a statement assign XYZ = PQR_AR[44*8 +: 64]; What does "+:" operator be known as. I tried to find this on google ...
13
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5answers
5k views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
13
votes
1answer
19k views

Verilog: XOR all signals of vector together

Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out: ...
12
votes
6answers
27k views

What's the motivation in using Verilog or VHDL over C?

I come from a programming background and not messed around too much with hardware or firmware (at most a bit electronics and Arduino). What is the motivation in using hardware description languages (...
12
votes
1answer
927 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
11
votes
3answers
18k views

How to truncate an expression bit width in Verilog?

Consider an expression like: assign x = func(A) ^ func(B); where the output of the func is 32 bits wide, and x is a wire of 16 bits. I want to assign only the ...
11
votes
9answers
19k views

Newbie projects on an FPGA?

I'm two weeks away from completing my first college digital logic design course, and apparently there isn't going to be a final project--just a tedious final exam. So as any curious student would do,...
11
votes
3answers
2k views

Is there a “Design Patterns” for synthesizable RTL?

For software, the book Design Patterns is a set of patterns for doing common things in software and it gives software practitioners common terminology to describe some of the components they need to ...
10
votes
3answers
10k views

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
10
votes
3answers
28k views

What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To ...
10
votes
1answer
2k views

what is the meaning of the pipe symbol “|” in front of a variable

I am analysing some verilog code and found something like wire z = |a & b; while simultation the code behaves just like ...
10
votes
4answers
24k views

Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
10
votes
2answers
28k views

How to compare two numbers (nets, variables, constants) in Verilog

I am new to Verilog, and would like to learn how to compare two numbers. For example, let's compare a parameter or reg (say a) with the number 2 (2'b10). How this will be written in Verilog?
10
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3answers
8k views

Free VerilogA simulators [closed]

There are plenty of free SPICE and Verilog simulators out there such as LTSPICE or TINA or even WinSPICE. There are also several Verilog simulators as well. However, I am looking for free VerilogA ...
9
votes
3answers
5k views

Is there a way of conditionally triggering a compile-time error in verilog?

I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating ...
9
votes
4answers
17k views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
8
votes
3answers
4k views

Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. ...
8
votes
2answers
30k views

Difference between >> and >>> in verilog?

What is the difference between >> and >>> in verilog/system verilog? I know that ...
8
votes
3answers
38k views

How are Verilog “always” statements implemented in hardware?

The Verilog always statement, namely always @(/* condition */) /* block of code */ executes the ...
8
votes
2answers
2k views

Why does this Verilog hog down 30 macrocells and hundreds of product terms?

I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this: ...
8
votes
2answers
1k views

“Logic Design” vs. “Digital Circuit Design”

I'm aware that different companies have different definitions for job titles, but in general, is "logic design" the same thing as "digital circuit design"?
8
votes
3answers
7k views

How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
8
votes
4answers
350 views

Detect registers which are not reset

When writing Verilog, I use a variety of "linters" that will give errors and warnings. These are my simulator (ModelSim), my compiler (Quartus II), along with a linter (Verilator). Together, I have ...
8
votes
4answers
5k views

SystemC vs HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
7
votes
1answer
36k views

Generate a 100 Hz Clock from a 50 MHz Clock in Verilog

I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
7
votes
3answers
42k views

How to assign value to bidirectional port in verilog?

I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error. ...
7
votes
4answers
3k views

Different Adder Implementations

I'm putting together an ALU, that I want to synthesize on an FPGA. The carry-look-ahead adder is the one many choose to use as opposed to the ripple-carry adder. However, a thought crossed my mind. ...
7
votes
5answers
3k views

Exercise based book to learn Verilog/vhdl?

I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I ...
7
votes
4answers
5k views

Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare ...
7
votes
2answers
6k views

What is the difference between reg and wire after synthesizing?

Assuming i have these two codes: module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule and the second one ...
7
votes
1answer
31k views

Generate an n bit random number in Verilog

I can easily generate a random number of width 32 bits in Verilog using $random. Is there a way to generate a random number of exactly ...
7
votes
1answer
23k views

Concatenate signal n times in Verilog

Given a signal wire [7:0] dummy, how can I concatenate it n times? That is, is there a notation for the following: ...
7
votes
2answers
8k views

Verilog UART Transmitter Sends Bytes Out of Order

I have the following Verilog code which sends 8 bytes to the serial port successively after a button is pressed. The problem is, the bytes are sent out of order as to what I would expect. For ...
6
votes
2answers
12k views

Implement serial port on fpga (verilog)

I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections? I have a Spartan-3AN evaluation board and I'm ...
6
votes
3answers
19k views

What is the I2C ACK, and how do I detect it?

I am writing an FPGA driver in Verilog for a temperature sensor (datasheet available here). The communication protocol is SMBus, a close cousin of I2C. Now reading the datasheet, I understand that the ...
6
votes
3answers
4k views

Clock problem with Spartan 6

I have a clock divider implemented as follows: ...
6
votes
5answers
1k views

How to think while working with VHDL or Verilog

All of my experience belong to general purpose programming languages e.g; c/c++ etc where each instructions are executed one after the other but it seems in VHDL/Verilog, all the instructions are ...
6
votes
3answers
17k views

Procedural blocks in verilog

We have two types of procedural blocks in verilog: initial and always block. The statements inside these blocks are executed ...
6
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2answers
4k views

My serial receiver verilog implementation does not act as expected

I have coded my own implementation of a serial receiver. It will work for incoming data at a baud rate of 115200. Here's my code: ...
6
votes
1answer
3k views

What is the difference between an array and a bus in Verilog?

I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following? What is the difference between an array and a bus? ...