Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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VHDL vs. Verilog [closed]
VHDL and Verilog are some of the HDLs used today.
What are the advantages and disadvantages of using Verilog or VHDL over the other?
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Can an FPGA design be mostly (or completely) asynchronous?
We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.
I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
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How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
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Readable and educational implementations of a CPU in a HDL
Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented.
P.S. I know I can look at opencores, ...
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Free IDE for VHDL and Verilog [closed]
I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
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Why are inferred latches bad?
My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided....
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Difference between blocking and nonblocking assignment Verilog
I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:
We normally have to reset flip-flops, thus every time the clock makes the ...
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How do I learn HDL
I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
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What is the "+:" operator called in Verilog?
I am going through a Verilog test case, and I found this statement:
assign XYZ = PQR_AR[44*8 +: 64];
What is the "+:" operator known as? I tried to find ...
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What's the motivation in using Verilog or VHDL over C?
I come from a programming background and have not messed around too much with hardware or firmware (at most a bit of electronics and Arduino).
What is the motivation in using hardware description ...
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What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
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Why is this Verilog RAM modification better in terms of resource usage?
I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm ...
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Verilog: XOR all signals of vector together
Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out:
...
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Difference between >> and >>> in verilog?
What is the difference between >> and >>> in verilog/system verilog? I know that ...
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1
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Concatenate signal n times in Verilog
Given a signal wire [7:0] dummy, how can I concatenate it n times?
That is, is there a notation for the following:
...
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Is there a "Design Patterns" for synthesizable RTL?
For software, the book Design Patterns is a set of patterns for doing common things in software and it gives software practitioners common terminology to describe some of the components they need to ...
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SystemC vs other HDLs [closed]
I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
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In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
I have a piece of code in Verilog which needs to assign the value of shift register to an output register when the shifting has finished, and I want to reset the value of the shift register in the ...
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What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?
I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
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what is the meaning of the pipe symbol "|" in front of a variable
I am analysing some verilog code and found something like
wire z = |a & b;
while simultation the code behaves just like
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3
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Generic free Verilog synthesis tools?
Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
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FPGA starts working after irrelevant changes, why?
I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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Using both edges of a clock
I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
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How can I generate a schematic block diagram image file from verilog?
I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
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How to truncate an expression bit width in Verilog?
Consider an expression like:
assign x = func(A) ^ func(B);
where the output of the func is 32 bits wide, and x is a wire of 16 bits. I want to assign only the ...
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Newbie projects on an FPGA?
I'm two weeks away from completing my first college digital logic design course, and apparently there isn't going to be a final project--just a tedious final exam.
So as any curious student would do,...
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5
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Why FPGA's have latches when they are almost never used?
This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both".
If use of latches in FPGA's is limited to rarest or rare ...
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Is there a way of conditionally triggering a compile-time error in verilog?
I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating ...
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Free VerilogA simulators [closed]
There are plenty of free SPICE and Verilog simulators out there such as LTSPICE or TINA or even WinSPICE. There are also several Verilog simulators as well. However, I am looking for free VerilogA ...
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Lint tool is throwing an error about bit width when adding two 10-bit unsigned numbers and assigning to a 11-bit net
My code:
module adder(a,b,result);
input wire [9:0] a,b;
output wire [10:0] result;
assign result = a + b;
endmodule
My company recently changed policy to ...
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What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
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How to assign value to bidirectional port in verilog?
I'm trying to use a bidirectional port in Verilog so I can send and receive data through it. My problem is that when I try to assign a value to the port inside a task, I keep getting an error.
What is ...
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How to compare two numbers (nets, variables, constants) in Verilog
I am new to Verilog, and would like to learn how to compare two numbers. For example, let's compare a parameter or reg (say a) with the number 2 (2'b10). How this will be written in Verilog?
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Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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How are Verilog "always" statements implemented in hardware?
The Verilog always statement, namely
always @(/* condition */)
/* block of code */
executes the ...
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"Logic Design" vs. "Digital Circuit Design"
I'm aware that different companies have different definitions for job titles, but in general, is "logic design" the same thing as "digital circuit design"?
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Procedural blocks in verilog
We have two types of procedural blocks in verilog: initial and always block.
The statements inside these blocks are executed ...
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Birectional I/O pin in verilog
I'm wanting eventually to interface some memory to my fpga.
This will require pins on the fpga that can both read data and write output to the ram.
I'm far away from doing any of that yet, but as a ...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
...
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How to think while working with VHDL or Verilog
All of my experience belong to general purpose programming languages e.g; c/c++ etc where each instructions are executed one after the other but it seems in VHDL/Verilog, all the instructions are ...
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What is the I2C ACK, and how do I detect it?
I am writing an FPGA driver in Verilog for a temperature sensor (datasheet available here). The communication protocol is SMBus, a close cousin of I2C. Now reading the datasheet, I understand that the ...
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Generate a 100 Hz Clock from a 50 MHz Clock in Verilog
I have a DE0 board with a 50 Mhz clock that am I trying to to bring down to 100 Hz in Verilog. Could anyone help me with the code to do this?
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Why does this Verilog hog down 30 macrocells and hundreds of product terms?
I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this:
...
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Are there any free simulators for SystemVerilog? [closed]
Are there any free simulators available for a hardware design coded in SystemVerilog? In particular, I need SystemVerilog's dynamic arrays.
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Relation between delta cycle and event scheduling in verilog simulation?
I understand that in Verilog/SystemVerilog standards there are different regions for event scheduling, thus mimicking the behavior of concurrent hardware. But how does this relate to the delta cycles ...
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What is the difference between reg and wire after synthesizing?
Assuming i have these two codes:
module wire_example( a, b, y);
input a, b;
output y;
wire a, b, y;
assign y = a & b;
endmodule
and the second one ...
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Detect registers which are not reset
When writing Verilog, I use a variety of "linters" that will give errors and warnings. These are my simulator (ModelSim), my compiler (Quartus II), along with a linter (Verilator). Together, I have ...
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Is the initial block in Verilog sythesizable?
I have come across a lot of posts which say that the initial block is not synthesizable in Verilog HDL. According to this appendix on synthesizable and non-...
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Implement serial port on fpga (verilog)
I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections?
I have a Spartan-3AN evaluation board and I'm ...
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Asynchronous reset in verilog
I am new to verilog and having a bit of trouble getting along with it.
I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am ...
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