Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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what's the correct way to add counter inside flip-flop?

I want to count number of "clock enable" signal inside flip flop. I learn from tutorials that the output value should be assigned for all combinations of input. However I don't know how to add ...
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1answer
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Why does the output of a register bank( designed by me in verilog) change after two clock cycles, even if input changes every clock cycle?

I have designed a register bank (pipeline register) to be used in a pipeline-architecture. The code of the register is: ...
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How to use array in Verilog actually?

I found that inVerilog, the array can only be declared in reg. And I found that it seems ...
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1answer
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RISC-V Arithmetic Shift vs Operator “<<<”

I'm new at learning Verilog so some of my practices are based on already existing codes. I was reading the RISC-V implementation of arithmetic shift and didn't quite understand why it's that way when ...
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1answer
110 views

Understanding Skid Buffer Mechanism

I have some questions about http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html 1) Why is skid buffer designed to be 2-entries FIFO instead of just 1-entry FIFO ? However, pipelining handshaking is ...
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1answer
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Assigning a value to a tri data type variable in Verilog

Suppose there is a 'tri' data type variable A declared in a module m in verilog. A is connected to the output of another module n which is instantiated twice inside m, in both the instances. In one ...
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2answers
241 views

FSM sequence detector in Verilog

I'm designing a finite state machine (FSM) to detect the sequence "10001" in Verilog. I'm having a similar problem to that described in this question in that my FSM does not tick when the sequence ...
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43 views

Direct NOR assignement doesn't work but all others do

I'm assigning a value 1 or 0 to my LED Gates of a Basys3. I a and b, not a and b, not b and a and neither a or b. Using direct assignement ...
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0answers
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Present two images side by side on the VGA screen from FPGA

Im trying to get a clue how to present two images on the screen using VGA. I using Altera Cyclone 2 DE2 and VGA, I have already working vga sync driver for 640*480 res: ...
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Declaring Pins in Top Module gives unspecified I/O default error, declaring it gives me the design is empty error

I have two modules top (input a, input b, output c) second(input a, input b, output c) I instantiate second in ...
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226 views

Verilog Generate statements: Syntax error near “<=”: unexpected <=

I am very new to Verilog, and I found the need to use "generate loops" to instantiate multiple hardware blocks. In this case, I am instantiating multiple "pe" blocks, a block which performs some ...
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1answer
112 views

Unknown problem with I2C on Spartan 3-E {VERILOG}

I have a Spartan 3-E board.I was using the inbuilt Xilinx SRL 16 (16 bit concatenated shift registers) for I2C communication.I verified successful implementation by displaying the number of "Acks" ...
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Elevator time calculating problem

I'm a Verilog beginner and I'm working on a project which calculates the time of an elevator going through different floors and down to the first floor eventually. There are four input signals: clk(...
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1answer
50 views

UART Receiver in Xilinx Spartan 6 FPGA

I am new to FPGAs and I'm trying to make a UART receiver in a Spartan 6 xc6slx9 FPGA. I searched online about UART receivers but almost all of them use FSMs. I don't yet know about FSMs. I have ...
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2answers
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When developing an algorithm for FPGA, should I be aware of amount of logic blocks (and other FPGA-specific properties)?

I want to see how certain algorithm would fit FPGA architecture and plan to implement it with HLS tool like CλaSH which produces VHDL/Verilog. All I know about FPGAs so far is it's an array of ...
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AXI burst read transaction returns unknown RDATA bits

My AXI burst write transactions had zero AXI protocol violations. However, during my data loopback test, Xilinx AXI BRAM IP slave returns me unknown RDATA highlighted in red colour in the simulation ...
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1answer
159 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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1answer
36 views

3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators

Simulation of a 3-stage shift register using blocking assignment statement in Verilog gives different simulation results across simulators: The RTL code is as follows: ...
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1answer
32 views

Verilog: Counter is not working

I have just started learning Verilog, so I tried writing a simple 4-bit binary counter. However, when I run the behavioural simulation, the output stays undetermined. I will really appreciate if ...
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21 views

Decimation filter for A/D data after FFT

Im working on designing an FFT on FPGA for data coming from A/D. My sampling rate is 300MHz (ext clock to the A/D) and the FPGA working on 150MHz (clk from the A/D component). I already did the A/D ...
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2answers
50 views

Unspecified I/O Standard value 'DEFAULT instead of User defined value. But I can also not assign a value

So I'm totally new to this and sorry if this is a really basic question which answer is in the error message. I get the error: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 25 logical ports use I/O ...
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1answer
148 views

Vivado LOC constraint via Verilog code

I'm trying to set LOC constraint while specified in verilog code (via verilog attribute). Previous research on the internet gave reasons to think that this sort of construction should work: ...
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1answer
69 views

AXI WSTRB and AWADDR issue with overlapping writes

I am having issue with AXI Protocol Checker pc_status[22] AXI_ERRM_WSTRB . Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and ...
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1answer
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Interpretation of pc_status bit location from Xilinx AXI Protocol Checker IP

In the pc_status error bit location , is it bit #32 because in the following simulation waveform, BVALID is never asserted high during the time when pc_status error bit #32 is asserted ?
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Verilog/SystemVerilog SPI Module Behavioral and Post-Synthesis Simulation Guidelines

I have an SPI module written in Verilog, and I need to verify that it is working properly. For that, I first have to do a behavioral simulation, verifying the functionality, and then synthesize the ...
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1answer
582 views

Verilog: cannot be driven by primitives or continuous assignment

Could someone help me figure out why I am getting such an error. The code below implements a 4 bit shift register adder which takes one bit at a time from each register computes the sum of the 2 bits ...
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3answers
90 views

How to get signal dependencies from RTL verilog?

How can I find out if a signal B has any combinational dependency on a signal A without manually examining the verilog source code? (Question edited to try and make the reason/background more clear) ...
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2answers
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Verilog: Sampling short, external, asynchronous input signals on a FPGA

I want to sample an external, possibly very short interrupt signal in my FPGA softcore. I did some research in some digital logic design books, and found this solution, where A is the input signal. ...
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1answer
35 views

Verilog : HiZ value in simulation

Everytime i run modelsim altera i get the output with 'z' in it and i dont know what is causing this. Modules: ...
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1answer
81 views

Verilog finite state machine won't reset (asynchronous) current state to initial state (shows xx)

I have mostly worked on VHDL and I have recently started learning Verilog. I wrote a Moore Finite State Machine (FSM). The FSM is not resetting properly as current state upon reset doesn't go into ...
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1answer
114 views

Traffic Light Verilog Code

I am working on a traffic light code and the code seems to be working fine in simulation, but when implemented on the FPGA the colors do not seem to toggle from yellow to red for the main street (sc) ...
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2answers
203 views

Interval measurement in Verilog

I am writing my Very First Verilog Program Ever: I'm trying to capture intervals between incoming pulses. I have a sample clock, an asynchronous pulse source, and the output is a registered 8-bit byte ...
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how to count like this: 0,1,2,1,2.. with 2bits register

Im trying to think about correct hardware design using verilog syntax to make a switch that counts like this: if reset -> switch=0. else if (not reset) & (flag) -> switch=1, switch=2, switch=1, ...
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0answers
51 views

FPGA and CPU design: Moving from ideal memory to real RAM blocks

I implemented the single-cycle MIPS design from "Computer Organisation and Design" in Verilog, shown below: I used my own "ideal" data memory implementation, which asynchronously presents the read ...
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2answers
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What is this operator called as “+:” in verilog

I am going through verilog test case and found a statement assign XYZ = PQR_AR[44*8 +: 64]; What does "+:" operator be known as. I tried to find this on google ...
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1answer
229 views

synchronous serial interface in verilog

i have a ADC (ADS1672 datasheet) (20MHz) with serial interface and xilinx spartan 3 XC3S400-208 (50MHz) in it's datasheet to data retrieval comes this: for that i implemented this code: inputs and ...
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2answers
105 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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2answers
49 views

Verilog design question: How to generate internal interrupts without delay?

I made a single-cycle RISC CPU in Verilog, and it works well on a real FPGA I have. It has multiple components that communicate over an internal bus. One of these components is a programmable timer, ...
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1answer
160 views

Error with reference to scalar wire 'reset' is not a legal reg or variable lvalue

I'm getting an error in Verilog with an input parameter it's not recognized as a legal reg or a variable lvalue. I had the same problem with the output in the module however it was fixed by labeling ...
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2answers
53 views

Net has multiple drivers (Verilog)

I've looked at some other forums and know that this type of error occurs when multiple outputs drive the same input however I am struggling to see how to fix this error and what specifically is ...
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38 views

Implementing WOLA block for ADC data on FPGA

I have ADC (ads5463) connected to an FPGA (lattice ecp3) using Verilog, and I have built an ADC interface on the fpga which capturing the data sucessfully and stores the data on FIFO. My next step is ...
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3answers
3k views

Synchronuous Combination Lock

I'm trying to implement a synchronous combination lock that will unlock once it receives "101011" using verilog. It has one input: x, and three outputs: unlock, ready, and error. Following these rules:...
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1answer
151 views

How to constrain delay in the circuit without a clock?

Background: The image below is, in essence, a simplified schematic of the, so called asynchronous state machine (AM_fsm.v). The design does not have any clock input signal. It contains many SR latches ...
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8answers
13k views

What is the difference between testing and verification?

Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction. To ...
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4answers
119 views

FPGA counter value unstabillity

I have been building a synchronized I2C slave receiver with Verilog. The I2C slave receiver did not encounter any issues when I simulated it with Modelsim. However, it does not function properly ...
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2answers
68 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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2answers
79 views

ice40-hx8k: Weird input pin behaviour regarding digital HI voltage level

I am playing around with a FPGA dev board featuring the Lattice ICE40-HX8K using the yosys/icestorm OpenSource toolchain, and I have noticed very odd behaviour my input pins are showing: When I use a ...
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1answer
88 views

Bad results from using Lattice FPGA Interface to capture ADC data

Im trying to capture DDR data from ADS5463 (TI ADC). As the datasheet suggested I need to delay the clock and sample the data with DRY clock. Im using Lattice FPGA LFE3-35EA.. and using Lattice High ...

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