Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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599 views

Logic and communicating protocols for the RS485

I have an RS485 transceiver (reference manual here) attached to an FPGA that I need to program in Verilog. I am wondering what the logic is, for example, to send bytes. Looking at the reference manual ...
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2answers
12k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
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2answers
2k views

Unexpected Verilog warning re FPGA clock assignment

I've got a question about something I don't understand that is going on in my FPGA project. I need to control two devices (AGC and ADC) through an SPI bus. As as the FPGA will be the master device, ...
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4answers
9k views

Is making a D flip flop with asynchronous level triggered reset possible?

I am starting to learn verilog coding in college and didn't have that much of a problem till now. I think I have the basics down perfectly. But I just hit a brick wall with this one. I was ...
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2answers
616 views

Why does design_vision compile my carry-lookahead adder into a ripple-carry adder?

At my school we have Synopsis "design_vision" in the computer labs. I don't know how to use any of the features so to me it's just a schematic-drawing tool. Out of curiosity, I hand-coded in Verilog ...
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2answers
979 views

Quartus - Export Verilog as Gate Level (FPGA)

I've got a project in Altera's Quartus II software which is written in Verilog. I'm curious if anyone here has figured out how to export the Verilog as a gate level netlist. I'd like to simulate the ...
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3answers
10k views

Generic free Verilog synthesis tools?

Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not ...
4
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2answers
12k views

Verilog: Check for two negedges in always block

i try to do something like this: always @ (negedge speed_dec or negedge speed_inc) begin do something end This doesn't work as checking for 2 negative edges ...
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5answers
5k views

Learning Verilog online

Now that I'm going to be using the PSoC 5 as my microcontroller of choice, I would like to learn Verilog so I can create my own peripherals for it. I have spent some time searching the web for ...
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2answers
851 views

Not able to get ac97 audio output from Atlys board

I am trying to get audio output from Atlys board (uses LM4550 audio codec). I got the ac97_controller.v core file which generates the serial o/p for the codec. It takes slots as inputs and puts them ...
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1answer
2k views

Verilog : Are there any good sites contains open source projects? [closed]

i was wondering if there are any good sites who encourage open source in the fpga world using code in verilog or vhdl? since the open source community is very powerful and all the big firms ...
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2answers
334 views

Implementation of a large parallel algorithm for communication with a server

I want to run a parallel algorithm I will implement in Verilog/VHDL and use a FPGA to run it. I have some questions: How can I make an http request to servers using an FPGA - should I use a computer ...
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1answer
41k views

How do I define a module with a modified parameter in Verilog?

I want to define an add module which has a modified parameter in my declaration of the new instance but it doesn't go well. It is in Verilog. I want to define an ...
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1answer
720 views

What FPGA chips support verilog-ams or verilog-a

I am having trouble finding explicit evidence on any FPGA vendors website that their chip supports the verilog-ams and/or verilog-a. Do all these chips support it, or is it only "mixed-signal" chips, ...
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1answer
2k views

Verilog structural CORDIC implementation for sin/cos calculation

Does anybody have a reference to an in depth explanation of hardware implementation of CORDIC algorithm for sine/cosine calculation? I'm looking for a way to model it in Verilog on structural level. I ...
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10answers
55k views

Free IDE for VHDL and Verilog [closed]

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
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2answers
2k views

XST Verilog - Casting real to integer constants

When I try to synthesize the following Verilog code using Xilinx XST, I get the error, "Unsupported real constant". If I try wrapping that expression in an $rtoi function, XST gives a different error:...
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2answers
806 views

How will this Verilog line be synthesized?

How will this Verilog line be synthesized? data = (s == 0) ? bus0 : 16’hz The problem is that if I use mux/buffer it won't put Z if ...
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1answer
500 views

Rs232 MAXSONAR to de2

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2answers
1k views

Connecting Altera de2 to a sensor via UART

Is Nios II required when implementing UART core using the SOPC? (or a default Nios is included) I tried writing my own module for the uart connection but it didn't work out. I need a method to ...
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2answers
4k views

UART core Altera De2

I have to implement a rs232 receiver for my project. Does any one have any idea on how do I start learning / implementing this. Do i have to use the nios ii software or just implement it using verilog ...
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3answers
42k views

How to assign value to bidirectional port in verilog?

I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error. ...
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2answers
1k views

De2 Board reading sensor reading

I wish to operate a LVMAX Sonar EZ1 sonar rangefinder. They say With 2.5V - 5.5V power the LV-MaxSonar EZ1 provides very short to long-range detection and ranging, in an incredibly small package. ...
2
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1answer
1k views

Mapping address ranges in Verilog

In Verilog, what techniques can be use for mapping an address bus onto different memory modules. Typical case: a microprocessor core whose address space is mapped to various memory modules: RAM, ROM, ...
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1answer
179 views

What was the motivation for making behavioral descriptions such a big part of Verilog?

I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description. When I write Verilog I ...
2
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1answer
2k views

Trying to program an FPGA. (Altera Cyclone II)

I have got FPGA development board (Cyclone II EP2C20F484C7) and am trying to implement a simple counter program as shown below (and maybe link it to the LEDs). ...
2
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3answers
502 views

What is wrong with this attempt at an SDR RAM in Verilog?

I have a Spartan-6 FPGA wired to the AEMIF memory interface on a TI DaVinci DM365 SoC that I control. The AEMIF is set up in Select Strobe mode. I'm trying to implement memory read/write on the FPGA ...
2
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1answer
3k views

Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to find the Absolute value of an integer which is designated to Verilog core using Xilinx C running on Microblaze, what i have seen is that Verilog treats the negative number as a ...
11
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9answers
19k views

Newbie projects on an FPGA?

I'm two weeks away from completing my first college digital logic design course, and apparently there isn't going to be a final project--just a tedious final exam. So as any curious student would do,...
2
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1answer
1k views

FSL Bus Problem in Xilinx FPGA Data Return

I wrote a custom IP peripheral in Verilog and interfaced it to MicroBlaze, using a hardware co-processor option. I can see the peripheral connected on the System Design Diagram. Everything compiles ...
6
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1answer
121 views

What transaction modeling and packet linking frameworks exist?

We're looking into modeling and checking a simple mesh fabric coherency protocol for checking RTL simulation. In the past, we've completely rolled our own solution for listening to packets in the RTL ...
94
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11answers
95k views

VHDL or Verilog? [closed]

VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
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2answers
7k views

verilog to schematic block

Is there any tool in linux that converts vhdl/verilog code to an equivalent schematic block. I know the available tools * Synplicity * Synopsys Design Compiler * Altera Quartus II * ...
11
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3answers
2k views

Is there a “Design Patterns” for synthesizable RTL?

For software, the book Design Patterns is a set of patterns for doing common things in software and it gives software practitioners common terminology to describe some of the components they need to ...
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4answers
3k views

Different Adder Implementations

I'm putting together an ALU, that I want to synthesize on an FPGA. The carry-look-ahead adder is the one many choose to use as opposed to the ripple-carry adder. However, a thought crossed my mind. ...
8
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3answers
7k views

How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
2
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1answer
322 views

Reset signal for fpga evaluation board

One of the answers to this question advised I used a reset signal for my fpga design. I agree, it's good advice and I'm adding it. Is there any way for me to ensure that this signal gets asserted on ...
6
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2answers
12k views

Implement serial port on fpga (verilog)

I don't know if this belongs here or stackoverflow. I assume here as although verilog looks like software it's actually describing hardware connections? I have a Spartan-3AN evaluation board and I'm ...
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1answer
607 views

recommandation webpage/book to learn asmd chart over using verilog

I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
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3answers
989 views

FIFO : doubt in process(clk)

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1answer
520 views

FIFO(vhdl) : Delete Operation

Suppose I have a FIFO code written in vhdl for FIFO. I want to delete an element from the FIFO. Here would the FIFO be acting the same as a linked list where I check each and every element of the FIFO ...
4
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2answers
13k views

how to write output of the monitor to a file

I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor. Is it possible ? If yes, can you give me ...
5
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2answers
1k views

Beginner with fpga and timing issues

I got myself a spartan-3an evaluation board in order to learn fpga programming and some verilog. It's taken a little while to stop seeing it in terms of a sequential programming language and to start ...
3
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3answers
3k views

Verilog simulator or development environment on Mac OS

Is there a way to develop some Verilog designs on mac?
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2answers
5k views

LCD driver program in Verilog for Altera DE2 board

I need to display the characters and numbers on a 2x16 LCD on the Altera DE2 board using a Verilog program. Any advice?
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1answer
3k views

Using the AC97 Codec on an Atlys Spartan 6 Board

I'm a beginner to FPGA programming. I just started programming an Atlys Spartan 6 board and so far have written one program to blink LEDs in a counter pattern. Now I'm trying to send the clock signal ...
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1answer
272 views

What language is Cadence's Emanger *.ecom files written in?

I know this is a long shot but I thought I would ask while I am waiting for the FAE to get back to me. This is related to Cadence Verilog simulations and regressions. I am trying to debug an *.ecom ...
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3answers
3k views

recommendation to learn verilog

To learn verilog, can anyone recommend any web-page or book? I have never seen such type of a language before, so what you recommend should be for beginner.
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9answers
8k views

Can an FPGA design be mostly (or completely) asynchronous?

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere. I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
7
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5answers
3k views

Exercise based book to learn Verilog/vhdl?

I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I ...