Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

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1answer
286 views

how to do a shift/add multiplier in verilog?

I tried this ...
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2answers
95 views

Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
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2answers
88 views

Why are delays required in verilog with combinational logic?

I have been getting into FPGA programming and Verilog and have been playing around in EDA playground for a bit creating some simple stuff. Often I need a clock so what I do is generate one on the ...
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1answer
64 views

How to use QSUB to submit jobs in parallel?

I would like to run thousands of simulations using qsub command, but I am not sure how to use it adding variables. Right now I have made this bash script to run my simulations, but it is too slow, ...
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1answer
92 views

View RTL/netlist/schematic with Icarus Verilog

I am learning Verilog and using Icarus Verilog for compilation and simulation. Is it possible to visualizate result somehow as a schematic, RTL etc?
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1answer
118 views

What kind of hardware multiplier do modern processors use?

I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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1answer
61 views

Multi-bit tri state buffer in verilog not working

I'm trying to write a tri-state buffer that buffers more than one bit, this is what I currently use: ...
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1answer
128 views

SystemVerilog FIFO problem with 6 bits in and 4 bits out

I was trying to induce the following functionality into SystemVerilog but i cant think of any efficient ways: So above is a picture of two 6-bit input packets that come one after the other (triggered ...
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4answers
131 views

How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
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1answer
52 views

Does Xilinx/Vivado have something like Altera LPM?

A few years ago I used the Library of Parameterized Modules from Altera (now Intel). I am now using Xilinx/Vivado, and I can't seem to find any equivalent. For example, I used to instantiate counters ...
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1answer
55 views

Register value is not updated inside always @ loop

I am relatively new to verilog, please help with this issue I am having. Attached is a snippet of the code I am working on. The issue I am facing is, the regs - del1 and del2 are not correctly ...
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1answer
127 views

Dumping values of multi-dimensional arrays into gtkwave for verilator

I am able to do a VCD dump of multidimensional arrays using $dumpfile(),$dumpvars() commands in iverilog simulator but the same commands is not working for verilator. Kindly do let me know if there is ...
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1answer
119 views

How to automate Instantiation of modules in Verilog? (permutation)

Consider this file tb_sr_latch.v: ...
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1answer
68 views

Using arithmetic operations in systemverilog

I was trying to create a module for using the sensors that I recently bought. My module works well in simulation , synthesis and implementation. but when I used my module inside the top leveled module,...
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1answer
36 views

create sr_latch from gates in verilog

consider this file : tb_sr_latch.v ...
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2answers
163 views

How can I transform the code for a read-write register to a read only register in Verilog?

I have the code for read write register here ...
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1answer
156 views

Understanding signed numbers in Verilog

For my Verilog code, I am trying to define a 64 bit array, like this input signed [63:0] var_name This array is broken up such that it is 8 bytes, each with a ...
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0answers
34 views

Arty7 Verilog Control PWM input Clk using PLL

I currently running into a problem of creating an instant of the PLL Clk_Wizard from Xilinx IP. My goal for this project is to provide a much faster clock for the PWM module (for exotic FET). I'm very ...
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1answer
74 views

H-bridge logic driver in Verilog

I am trying to come up with a driver logic for an H-bridge (seen in the image attached) which would provide a single-ended or a differential pulse based on a user choice. Input signals: clk (clock, ...
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1answer
89 views

Number guessing game:Compare numbers and position in Verilog

I'm designing the number guessing game,aka mastermind,1A2B,And I'm stuck. I'm having problem with how to compare the 2 set of 4-digit numbers and output ...
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2answers
30 views

Synthesize ATPG Test vectors with 'X' Values

I am working on synthesizing generated ATPG test vectors and implementing them on an FPGA. However, there's plenty of "don't care" values 'X' in the stimuli and response vectors. I am not sure how ...
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1answer
72 views

Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010: ...
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3answers
140 views

Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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1answer
99 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
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1answer
266 views

Removing modelsim error

I am trying to simulate a simple inverter in verilog using modelsim 10.7 version. While compiling the code I am getting the -novopt error (error code 12110). As per user manual page 80; the -novopt ...
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1answer
76 views

How to specify a value for each bit of the reg in Verilog?

I want to declare a reg of 8 bits and set the value for each one of the bits separately (based on another "counter" reg) inside ...
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1answer
38 views

Verilog Reg File: Cant mix blocking and non-blocking assigment

I want to implement a blocking read to read the data as soon as it is written. I am trying to implement a MIPS 1 pipeline and i need the data to be available in the same clock it is written. The flips ...
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0answers
27 views

mismatch in register delays between lib files and generated sdf file (Synopsis Design Compiler)

The recovery time in sdf file of register is unrealistic delay as it is 50ns and this not the only problem, but the same register in anther place in the design has recovery time 0.3ns ! and recovery ...
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2answers
343 views

Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
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4answers
206 views

Clock Dividers with Clock Domain Crossing

I am doing a design in FPGA that looks like this: 100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with ...
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1answer
110 views

Verilog - Wiring multiple hardware instances together

I am very new to Verilog and digital hardware implementation. I want to instantiate multiple instances of a hardware block, place them side-by-side, then wire them together (ie. one block's output ...
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2answers
168 views

Verilog Generate statements: Syntax error near “<=”: unexpected <=

I am very new to Verilog, and I found the need to use "generate loops" to instantiate multiple hardware blocks. In this case, I am instantiating multiple "pe" blocks, a block which performs some ...
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1answer
135 views

Keypad saved shifting display using Verilog

I'm designing a number exchange module, and so far I've been able to make it display on Seven Segment Display (S-S-D), like if I press 0 it shows 0... etc. I'm using 2 sets of 4-bits S-S-D (Common ...
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1answer
206 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
41 views

What is the difference between a hard module and a softmodule in RTL verilog code?

I understand a Verilog code is made up of modules there are RTL codes where a lot of submodules can be instantiated in the main module. If I assume the main module(the top one) to be the parent and ...
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2answers
124 views

How to implement a Linear Feedback Shift Register in Verilog using for loops?

I tried implementing LFSR using Verilog , but I am unable to get the output properly, please check the verilog code for both module and test bench below:- ...
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1answer
209 views

MKR Vidor 4000 Verilog tutorial

I can't find any tutorial on how to write verilog on MKR Vidor 4000. If you have done it what software do you use to synthesize, simulate and create a bit stream to the board ? Thanks,
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1answer
141 views

For-Loop and repeat synthesis

We all know that the For-loop and Repeat are synthesizable, they get converted to blocks, for example: ...
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1answer
150 views

Lattice Diamond Port 'direction' is unconnected

I am following the tutorial to turn on the LED on the embedded vision development kit found in: C:\lscc\diamond\3.10_x64\docs\tutorial\Diamond_tutorial\Ledtest.v ...
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3answers
62 views

How can I improve my 3 decade counter design so that it counts sequentially in Verilog [closed]

I am attempting to build and simulate a 3 decade BCD counter by cascading 3 decades counters that produce an output to indicate when the count of 9 is reached. My design works, in that it counts ...
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2answers
147 views

Why we need non-blocking assignments in Verilog?

I understand the basics of blocking and non-blocking assignments in verilog. I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently ...
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3answers
126 views

Instantiating module in condiotional block verilog

Considering a module cannot be instantiated inside if block, how are we supposed to instantiate the module outside the if-else ...
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1answer
232 views

Ring Oscillator on FPGA for TRNG

I am implementing a TRNG on an FPGA. This TRNG is based on jitter created by ring oscillator and I would like to know how to implement the given ring oscillator on FPGA so that jitter is generated. <...
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1answer
102 views

Verilog if else if construct

I have verilog code that looks like this begin if (condition) if(condition2) else if(condition3) else if(condition4) else ..logic.. end ...
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0answers
76 views

Edge of signal triggers future jump in counter

I'm trying to make a design in which a counter is constantly incremented and loops back to zero at a certain point. That's pretty straightforward, but I'm attempting to make it so that when a switch ...
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2answers
231 views

PWM Control using Verilog problem

My PWM control is having issue,I don't know why... So I'll briefly describe my PWM specs; a 4-bit Input named value, Input clock 50MHz, a single bit output <...
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0answers
62 views

Verilog code for SET and RESET

I'm trying to write verilog to synthesize a circuit which operates as follows: At the rising edge of SET if RESET is low then OUT is set high and it will be reset when RESET is high (the first cycle ...
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1answer
156 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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3answers
375 views

XOR all signals of a vector of two dimensions together

I have a vector that contains 15 elements of 8 bits each. I want to XOR each element: $$ out = f_0 \oplus f_1 \oplus \dots \oplus f_{15} $$ where each \$f_i\$ has 8 bits (it's declared as logic [7:0] ...
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1answer
117 views

Design simulates perfectly but won't work on FPGA

First, thanks for the help yesterday. This time I will document my code correctly. So, we were tasked with creating a parking meter that would take 4 inputs, one adding 50 seconds, one adding 150 ...

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