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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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How to implement a signal with an early falling edge dependent on another signal? [closed]

I have two signals, an enabled signal and a delayed enable signal. The enabled signal is an input, and the delayed enable signal goes high a few microseconds after the enable signal input goes high. I ...
jukebox41188's user avatar
0 votes
2 answers
93 views

Why does the white space get included while reading a string from a file in VHDL?

I am trying to read data from a text file in VHDL which includes two vectors and single character. While reading, white spaces are not detected for the numbers but are detected for the character. Why ...
Sarthak Nandanwar's user avatar
-3 votes
1 answer
101 views

Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
A. V.'s user avatar
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1 answer
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How to correctly write and read to/from SRAM on FPGA with VHDL?

I want to write 512KByte data on SRAM(IS61/64WV512).I'm using spartan6 lx9 FPGA. In the program routine, the initial step involves writing all the data. Subsequently, upon completion of the writing ...
MH.AI.eAgLe's user avatar
-1 votes
0 answers
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Why does "i_spi_clock_divider - 1" not update if i_spi_clock_divider has a given value?

I'm currently facing a puzzling issue with my SystemVerilog SPI controller design and would greatly appreciate some guidance and insights from the community. Problem Description: I have implemented a ...
Adelynul's user avatar
1 vote
3 answers
64 views

Output Variable stays unintialised in my VHDL testbench

I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop. Following is the VHDL code that I have written: ...
Rohan's user avatar
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0 votes
1 answer
65 views

VHDL: Keep multiple files open until end of simulation [closed]

In my testbench I write to several outputs files as the test proceeds. These files are later processed by a Python script to generate meaningful data. The testbench writes 100,000s of lines of data in ...
quantum231's user avatar
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1 answer
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I'm trying to build a FSM in VHDL but the Mealy state machine won't change states

I'm trying to build a Mealy Finite State Machine in VHDL. each time a button 'btn' is pressed, the FSM should go to the next state. There are 4 states, s0, s1, s2 & s3. s0 is the state at which ...
Zzz's user avatar
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0 votes
1 answer
39 views

VHDL: textio variants of the write function for real data type

Here are the two variants of the write function that can be used to write the "real" data type into file or stdout. ...
quantum231's user avatar
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0 votes
1 answer
57 views

Difficulty understanding the need for multiple-register pipelines for signals [closed]

When I studied the GPIO demo code for Basys3 to create my own VGA controller, I noticed that multiple registers are used for a single signal, like h_cntr, H_sync, V_sync, VGA_R, VGA_G, VGA_B, etc. I ...
FPGAVHDL's user avatar
2 votes
1 answer
68 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
Serkan Kaya's user avatar
1 vote
1 answer
59 views

A NAND gate with propagation delay in VHDL

I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL. \$t_{PLH}\$ = Propagation delay low to high \$t_{PHL}\$ = Propagation delay high to low This is first code. ...
Serkan Kaya's user avatar
0 votes
1 answer
39 views

How do I implement a simple axistream by my self bus in VHDL?

I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
fabrice's user avatar
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1 vote
0 answers
105 views

Generating an 80 MHz clock from a 100 MHz clock with VHDL in Spartan-7

I am new to VHDL and am targeting a Spartan-7 FPGA, using VHDL. For technical reasons I have to develop outside the Vivado or other environments. It seems like there are several posts that have ...
villaa's user avatar
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1 vote
1 answer
39 views

Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&'

It may be a simple fix, but I do not understand the error: Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&' ...
Anne van der Doelen's user avatar
0 votes
1 answer
45 views

Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL

I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
David H Parry's user avatar
0 votes
2 answers
114 views

Assert 'must be power of 2' in VHDL?

I'd like: ...
David H Parry's user avatar
0 votes
1 answer
161 views

Encryption of Verilog/VHDL module

I don't have encryption licenses for Vivado or Quartus to encrypt my Verilog/VHDL modules and so I cannot give my RTL to any user. I don't want to give out synthesized netlists but only encrypted RTL. ...
Im Groot's user avatar
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1 answer
42 views

Packaging synthesized design as netlist for use in future designs

I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
John B's user avatar
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1 answer
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Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado

I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL ...
Isaac's user avatar
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1 answer
105 views

Use VHDL to create a simulated EEPROM component for testbench

I have created a component for a simulated, serial EEPROM to use in a testbench. The logic for performing the SPI communications is straightforward. In addition, I have created a byte array, with ...
Gregory Helton's user avatar
1 vote
2 answers
148 views

PSL usage in Formal Verification, assertion problem

I am investigating the usability of formal verification in FPGA designs using VHDL, PSL, SymbiYosys, and GHDL. I've watched several webinars, read a PSL book, and gone through tutorials. Currently, I ...
e2p's user avatar
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2 votes
2 answers
370 views

(vcom-1136) Unknown identifier "std_logic" & "std_logic_vector"

I am relatively new to VHDL, and I am getting the errors below although I used the same procedure before: ...
Andre_van_stone's user avatar
0 votes
1 answer
101 views

Formal HDL verification with PSL

I am trying to learn Formal Verification for VHDL design (using Property Specification Language). My module has an active-low reset input. I would like to drive tool to set the reset input to '0' for ...
e2p's user avatar
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0 votes
0 answers
89 views

ICM-42688-P read from address not given in Datasheet

I am currently working on software for a project that involves an ICM-42688-P sensor IC. The FPGA uses a 16-bit SPI interface and needs to read this data block of 16 bytes: Datasheet Page 60, 13.1 So ...
ElectronicsStudent's user avatar
3 votes
2 answers
430 views

Does SystemVerilog have (others=>'0') expression like VHDL?

In VHDL, we can set all bits of something a value by using (others=>'0'). It is also possible to use slice index e.g., ...
quantum231's user avatar
  • 11.9k
1 vote
3 answers
157 views

How to use VHDL to shift 2D array?

I first defined a binary array ...
48143447qqcom's user avatar
1 vote
1 answer
128 views

VHDL modular multiplication always resulting 0 in simulation

I'm trying to implement a modular multiplication algorithm in VHDL, but the result "r" is set to 0 on every simulation. I would like to know how to fix it. ...
Anis_bsh's user avatar
0 votes
2 answers
159 views

Drawing a Visual Hardware Representation for VHDL Code

The following code is given. My task involves drawing a visual hardware representation that outlines the modules, their associated ports, and the interconnecting signals. Check out my solution below. ...
Marco Moldenhauer's user avatar
-1 votes
1 answer
175 views

Select bit in std_logic_vector based on unsigned with multiplication

Is the following allowed in VHDL(2008)? ...
po.pe's user avatar
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0 votes
1 answer
61 views

When I try to simulate VHDL code, the signals do not work, losses, show a orange color

I'm using a Nexys 3 Spartan 6 Lower Power XC6SLX16L. The idea of the program is with a timer counter with specific conditions with the bottoms. Here is my code: ...
Omar Nossa's user avatar
1 vote
1 answer
114 views

Why do I still have latches even though I include everything in sensitivity list?

The following is the code snippet which generates the inferred latch warning. ...
kile's user avatar
  • 831
2 votes
4 answers
2k views

Is there any way to know how real discrete components are being connected to each other using logical gates?

Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each ...
dsa's user avatar
  • 31
1 vote
1 answer
69 views

VHDL schematic without connections [closed]

I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports. The program is a frequency ...
A. V.'s user avatar
  • 19
0 votes
1 answer
79 views

How to model a 4-way inout crosspoint switch in VHDL?

I want to model a crosspoint switch with 4 inout ports that can route a signal coming from any of the inout ports to any other ...
mnemocron's user avatar
0 votes
1 answer
125 views

Choose the right strategy to divide two values [closed]

Info: After getting some comments and already one answer, I decided to rewrite this question to better fit into this site. I had a problem where I needed to downsize a 12 bit value to an 8 bit value. ...
TimSch's user avatar
  • 209
1 vote
1 answer
264 views

VDHL - Using multiple I2C devices with single IP

I need help with a design that I am currently working on. I am using a Spartan 3 that is on a custom board that checks 6 devices using I2C and these devices all have the same address so I am trying to ...
newtoallthis's user avatar
0 votes
2 answers
91 views

Using Atomminer AM01's fpga for purposes other than mining [closed]

I was thinking about Using Atomminer AM01's fpga for purposes other than mining, maybe using vhdl or verilog, I wanted to ascend if it is possible?
BONIIXS's user avatar
0 votes
1 answer
401 views

Questasim Unable to find VHDL package not compiled into work

I'm currently trying to simulate a VHDL module with a SV testbench. The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the ...
EpicFoodCartDestroyer's user avatar
0 votes
1 answer
66 views

is this signal command_signal in sensitivity list ignored in synthesis?

the following process is part of my vhdl code. But I am not sure whether this works after synthesis. Are counter_sdin and command_signal ignored during synthesis? ...
kile's user avatar
  • 831
0 votes
1 answer
71 views

Initial value for index[3:0] is ignored for synthesis

My code works perfectly under Windows quartus. But when I am using hdl designer (Siemens) under Centos, I have the following problem. There is no info about this "compile_initial_values" ...
kile's user avatar
  • 831
0 votes
2 answers
123 views

How to write tests for a clock signal

I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests ...
chick3n0x07CC's user avatar
2 votes
2 answers
187 views

Parsing variable-sized data in 32-bit datastream

I have a 32-bit datastream coming from a sensor. The data is encoded as a Type-Length-Value encoding. This means the first byte indicates what kind of data there is and the second byte contains the ...
John Smith's user avatar
1 vote
0 answers
77 views

Intel DCFIFO IP crashing when using a clock with decimal place

I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock. The data are read from an SDRAM and are fed into the VGA output. To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
TimSch's user avatar
  • 209
0 votes
1 answer
120 views

VHDL compile message: array index 10 out of range

...
Noam Bank's user avatar
0 votes
0 answers
64 views

Error: (vsim-3544) TEXTIO procedure READ(BIT_VECTOR) : Cannot get value from "9"

The code is from How to Read Image in VHDL The author said it's synthesizable, but it's not like what he or she said. When I am simulating the code, ModelSim gives me the following message: "...
kile's user avatar
  • 831
0 votes
0 answers
208 views

How to Place Connections Between Microblaze and Custom RTL Modules in Vivado

I am very confused with this particular issue and would appreciate any help. So I am using the Vivado block design to place a Microblaze with 128kB local memory modules, an AXI GPIO and UartLite ...
David777's user avatar
  • 1,490
1 vote
1 answer
99 views

VHDL my FFT design doesn't work at larger N-point

I built an FFT module for an 128-point FFT in VHDL. When I use the same principle for 8-point fft or 16-point fft (ofcourse then the file must be altered for less stages and different twiddle factors),...
Mart's user avatar
  • 376
1 vote
1 answer
129 views

GENERATE statements in VHDL

I am investigating using GENERATE statements in VHDL to make duplicating the same logic tidier and more efficient. Take a basic example I found online below: ...
David777's user avatar
  • 1,490
1 vote
3 answers
239 views

Why isn't my counter reseting in VHDL?

For a project, I need to write a binary counter in VHDL that starts at zero, counts to nine, and then resets to start at 0 again. I wrote the file below, which seems like it should function correctly. ...
elvishpotato's user avatar

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