Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

Filter by
Sorted by
Tagged with
1
vote
0answers
32 views

What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a ...
0
votes
1answer
47 views

What is the SystemVerilog equivalent of the VHDL "library"?

I have been writing VHDL for a while. There, we have the concept of libraries, which comes in handy. I cannot find something of this nature in SystemVerilog. Is it true that SystemVerilog has no ...
-1
votes
1answer
28 views

Modelsim: Debugging "NUMERIC_STD.TO_UNSIGNED: Vector truncated"

I might be able to post some code if needed, it's hard though cause the code is on a different machine. But I'm looking more a general approach to debugging this warning "NUMERIC_STD.TO_UNSIGNED: ...
0
votes
1answer
62 views

Signals acting weirdly in VHDL

I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example if rising_edge(clk) then but in this testbench, after the first wait ...
0
votes
0answers
33 views

How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
-1
votes
0answers
39 views

What is the problem with "Undefined symbol 'prac7_proc2'"

I have the following code(I'm pretty new in VHDL): ...
0
votes
2answers
78 views

VHDL : "wait on" vs sensitivity list

I read that a process with a sensitivity list is equivalent to a process with wait-on statement at the end. Why does "wait on" statement have to be at the end of the process to behave the ...
-2
votes
5answers
171 views

Why Hardware Description Language?

Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL? From wiki, A hardware description language enables a precise, formal description of an ...
0
votes
0answers
45 views

VHDL error: Expression expected

I am making a testbench for a VHDL program, and in line 28 it's giving me an Expression expected problem. This is the code: ...
1
vote
1answer
89 views

Alternatives to FSM in VHDL?

I want to design a UART using logic gates but I don't know if is there any alternatives to Finite State Machine. Coding a UART in VHDL using FSM is really easy and abstract, the programmer doesn't ...
0
votes
1answer
57 views

Type of X is incompatible with type of XXXX

I have the following code(I'm pretty new in VHDL): ...
0
votes
0answers
50 views

ADC interface with FPGA CMOS Interface

I want to implement an ADC Interface for an ADC - ADS4128 (TI) in VHDL. Is there any link where I can get a reference of a 12-bit ADC in VHDL similar to ADS4128 for quick understanding of the approach ...
1
vote
1answer
48 views

Vivado cannot determine equality operator for enum type in assert statement

I have the following assertion in my code: assert (debug_decoded_opcode = types.AUIPC_OP) report "00000317 not AUIPC"; Vivado gives the error: ...
2
votes
2answers
186 views

Is it bad practice to use the positive/rising edge of a "non-clock" signal?

Situation: Before a data ready signal can go high it must wait for a data valid signal to go high. Once ...
0
votes
0answers
38 views

Pulse width validation in VHDL - OSVVM

I'm working on an FPGA project where I need to generate pulses with a certain width and a certain periodicity, for example 25 clock cyles with a period of 1024 cycles. I need to design a testbench to ...
0
votes
2answers
119 views

How important is it to register signals at both input and also output in digital design?

In digital design, the output signals may have source in register or perhaps some combinatorial logic which is directly connected to an output port. This raises these questions: How important is it ...
3
votes
3answers
230 views

Will a shift register cause metastability?

The graph above shows the output of a shift register. The output of Qa is sampled at the first rising edge on data input. the voltage is building up during that time. Will it cause metastability ...
1
vote
1answer
79 views

When behavioral simulation of RTL works but synthesis/implimentation do not

I wrote a UART receiver similar to Nandland's example. To verify that I am receiving and processing data (coming from my PC through Putty), I wrote a design that would correspond certain LEDs to ...
0
votes
0answers
76 views

Exporting Vivado simulation results

I'm trying to export the values from a behaviour simulation, but can't find a solution. I have to compare the speed of two different VHDL simulations. As they use the same state flags, comparing them ...
0
votes
1answer
87 views

What is a correct approach to implemement an AXI stream interface? [closed]

I am designing several sumodules for FPGA and would like to interface them through an AXI stream. Some of the modules I use are able to process the stream at data throughput speed same as clock one. ...
1
vote
1answer
108 views

vhdl reset synchronizer [duplicate]

I have a question regarding reset synchronizing. If I have a reset_synchronizer.vhd file like this: ...
0
votes
0answers
51 views

Serial input parallel output issue in VHDL [duplicate]

I somehow don't know how to manage compiling this design in VHDL. I implemented a SIPO and I'm facing this error below : ...
-1
votes
2answers
277 views

VHDL - Adding two std_logic_vectors, issue

I'm having an issue when trying to add two std_logic_vectors. The two vectors are reg_A and ...
1
vote
0answers
60 views

VHDL: input signal timing variations

VHDL newbie here; I am trying to solve a problem with an existing CPLD project (based on a Xilinx XC95144XL). The project in question is an plug-in cartridge for a vintage home computer, adding ...
0
votes
1answer
58 views

VHDL: Taking signals from one architecture to another

Im trying to do a series of simple operations (multiplication, CA2, and, substraction) and then, based on the values of "sel", choose one of those possibilities, so essentially, a MUX, so ...
0
votes
0answers
37 views

Initializing feedback signal in ModelSim simulation

I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit: DELAY is a delay element which I have correctly implemented using ...
1
vote
1answer
73 views

Trying to use 5 registers in Xilinx's AXI Lite interface

I have an IP for Digilent's Zybo Z7-20 which segments the image. The segmentation is done based on histogram. The segmentation module takes 4 32-bit wide inputs which contain the threshold values. In ...
0
votes
1answer
43 views

Access VHDL FSM state type in SystemVerilog testbench?

I have a VHDL block that implements a state machine, with states defined as a type and the current state as a signal of that ...
0
votes
1answer
100 views

VHDL IF statement inside process statement

I am learning VHDL. I have doubt regarding execution of If Else inside process statement. My code is : ...
2
votes
1answer
111 views

SystemVerilog vs VHDL - Is there a way in SV to do late definitions of array sizes?

In VHDL I can make my modules arbitrary. Bus sizes flow from higher levels. That way I don't need to edit all my code every time I reuse a module. Consider the following (incomplete) examples (This ...
0
votes
2answers
169 views

How can I generate a 1 Hz clock from 100 MHz clock using VHDL?

How can I generate a 1 Hz clock from 100 MHz clock using VHDL? ...
0
votes
1answer
64 views

Error 10822 when trying to create simple falling edge with signal out

I am having the below error code when attempting to compile. Error (10822): HDL error at CLEARBLK.vhd(17): couldn't implement registers for assignments on this clock edge ...
4
votes
1answer
159 views

Is it possible to know the instantiation number inside the instantiated code when using a for loop to generate multiple VHDL component instances?

So I know how to instantiate multiple instances of the same component in VHDL, see the example code: ...
0
votes
3answers
225 views

VHDL: Integrator/Accumulator Won't Subtract

This feels pretty silly but I've been trying a bunch of things for a while now and I can't figure out why this accumulator/integrator can never decrease. It can hold its value or increase, but it ...
0
votes
2answers
66 views

Should we write else statements in VHDL if/else blocks to handle things other than '0' and '1' for std_logic and std_logic_vectors?

Which of these is correct way to write synthesis code? This one: ...
0
votes
1answer
121 views

VHDL near text "begin"; expecting "end" Error

I'm trying to learn VHDL and and trying to create an 8 bit 4 to 1 MUX. Below is my code: ...
0
votes
2answers
209 views

How to easily resize strings in VHDL?

I have declared a string in the testbench code. However, I find that it is not simple to assign value to it. Here is the test code: ...
0
votes
2answers
439 views

Minimalistic TCP/IP implementation on FPGA

I know, implementing the TCP/IP stack in hardware on a FPGA is a very difficult task and should be done in software. My goal is, only to implement the necessary parts of the stack on hardware so I can ...
0
votes
1answer
139 views

Does VHDL not allow use of the concatenation operator on the LHS of an expression?

This code reproduces the error: ...
0
votes
1answer
49 views

Represent assigning part of a vector in a schematic | VHDL

In my VHDL I have signal m1, m2 : unsigned(7 downto 0); signal result : unsigned(31 downto 0); I am using an 8-bit multiplier for ...
0
votes
1answer
78 views

SPI master design: theory

I am working on SPI master and slave blocks. In the design, SPI slave has only input signals ( CLK, cs(chip select) and MOSI), SPI master has only output signals ( CLK, cs(chip select) and MOSI). I ...
-1
votes
2answers
125 views

How to avoid empty FIFO when the read clk is higher than the write clk

I have an ADC, and, in order to avoid sync problems, I have used a FIFO with two different clocks: one for the write operation, that works at the ADC clock frequency and the other, FPGA clock that is ...
0
votes
2answers
106 views

VHDL procedure evaluation and call sequence

I want to ask what is the order of procedure call in VHDL. Below I have VHDL code showing a procedure called 'IncrementWrap' and a process which calls the procedure multiple times. I got the code form ...
0
votes
2answers
73 views

VHDL testing feedback circuits

how do you test circuits with output signals which feedback into the input circuit? Below is an example of a test bench i wrote, the current_iteration and ...
4
votes
2answers
84 views

Procedure is unable to find function since it is defined after the procedure, how to fix this?

In my VHDL entity, I have declared some procedures in the header of the architecture i.e before the keyword begin. Some procedures are calling functions. The ...
0
votes
1answer
101 views

How to create a VHDL function/procedure that can return true or false based on value of signals outside it?

Here is the function I am trying to write: ...
0
votes
1answer
74 views

Why is VHDL pure function able to access a constant that exists outside it?

Here is the source code of what I created for experimental purpose: ...
0
votes
0answers
31 views

Error (10822): couldn't implement registers for assignments on this clock edge

I have to make a state of four traffic lights to make them blink every second and every half second, so I created to clocks for that but when I use them I get this errors: Error (10822): HDL error at ...
1
vote
1answer
57 views

When is it important to use keyword "null" in synthesizable VHDL code?

I have usually seen VHDL keyword null being used in the others part VHDL case blocks. However, it also sometimes appears in else part of if statements. Unlike ...
1
vote
3answers
82 views

Modeling bidirectional propagation delays

I'd like to build a VHDL model of the propagation delays on my board. For unidirectional signals, that is easy: ...

1
2 3 4 5
34