Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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How do I do an "if" or "case" statement in VHDL without a process? [closed]

So far in my learning of VHDL, I have learned to use an if and case statement in a process, such as: ...
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Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

It may be simple but I don`t know what's the error. ...
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(others => '-') in VHDL

I am trying to set res to "----" which is done in an example in my book. When I run the following code I get the message "failure1": ...
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Synthesize of "REAL VARIABLES" in Vivado 2020.1

I am using the following libraries: library ieee; use ieee.std_logic_1164.all; library ieee_proposed; use ieee_proposed.fixed_pkg.all; use ieee_proposed.fixed_float_types.all; I cannot synthesize real ...
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How to achieve signal gating with trigger input

I am currently working on a project that generates enable pulses of extremely diverse lengths from microseconds to days and under normal operation will start execution under a trigger input. However, ...
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Is there a way to use ModelSim in VHDL to change a signal value that is not explicitaly an input

I will try to keep it simple. I have a process as follows: ...
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How to implement do-while loop in VHDL?

VHDL has a while loop but not a do-while loop. In the do while loop the code inside the loop is always executed atleast once since the condition is evaluated at the end of the loop rather than the ...
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How to design interfaces for memory hungry circuits

I'm new to hardware design and one thing I'm struggling with is how to structure the communication between circuits (components). In VHDL you use the port map ...
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Is it possible to connect an AXI-Lite master to AXI Slave?

I have a VUnit AXI-Lite master BFM. On the other end I have an AXI-slave on a component written by someone else. I have found that the AXI-slave has the following signals that are not present on the ...
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Does VHDL allow a std_logic_vector port with no bounds?

Here is a code from VUnit Avalon Master BFM: ...
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How to apply two NOT gates sequentially in VHDL?

I have one signal: signal 1 : std_logic := '0'; I want this signal to go through two sequential NOT gates: ...
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1 answer
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4 input multiplexer in VHDL

I am trying to model a 4 input multiplexer using VHDL; I am using edaplayground.com. I am trying to do this using a 2 input multiplexer. The code for only the 2 input multiplexer works, but when I try ...
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ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
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VHDL: How to use records as PORTS with IN and OUT parameters?

Is there a syntax where one can use a record type in a PORT declaration, but specify that certain members of the record are IN ...
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1 answer
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VHDL: My counter increments by 2. Why?

update: I will rewrite my whole VHDL-Statemachine because I had just trouble with the basics of FSM. I will try to find a easier FSM for this. I have a state machine and as I really forced to use a ...
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2 answers
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How can I import a file's contents as an array of hexadecimal constants in VHDL?

I've written an assembler for my CPU architecture, and I'd like to be able to import its output as program memory in VHDL. Currently, the program memory is stored like this: ...
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VHDL - using PORT MAP with FOR LOOP?

Just touching base on one thing. My group and I are making a stopwatch with a lap function for our final project. For the lap function we are using a ROM along with three 32-bit subtractors, which use ...
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Design using 5x1 Mux, would this have any complications?

I am building a stopwatch with 5 counters. All are BCD counters with the exception of 1 modulo-6 counter (10ths, 1s, 10s, 1mins, 10mis.) I intend to pass these to the 7 segment displays on my board. ...
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How to set VHDL entities internal latches for testing purposes

How do I set internal/private latches deep inside entities for testing purposes ? simple example I have an entity deep inside my architecture which I cannot easily manipulate with an internal signal <...
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VHDL, how to assign signal of different types to port map with constraint inference?

I want to assign signals of a testbench to a component to which the port have infered constraints. I would like to introduce the problem with a working workbench before moving to a minimally ...
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Why is BSDL syntax so wordy?

Looking at BSDL now, one can be surprised that BSDL doesn't look like XML, for example. I understand that the first IEEE-1149.1 was released in 1990 and XML 1.0 was released in 1998. Even knowing this,...
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XILINX A7: can I connect MMCM to MGTREFCLK1N_216?

I have a problem with my MGTREFCLK1N/P_216 pins on my A7 xc200t board. I "should" connect it to a MMCM. I worry that it is not possible due to the physical placement of the bels and so on. ...
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Vivado: Design failed to meet timing requirements. Is it because of ifs?

I use Vivado 2019 and want to create a bitfile. I want to use an incoming clock for both my ip-core and my process, but I have some timing errors. 1. What I tried: 1.1 clocking How to use derivation ...
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Same behavior, different synthesis outputs, state machine coding style in VHDL

In an old course book on VHDL I've been revising, the author discussed the effect of coding style on the actual synthesis output of state machines. The example discussed in the book is a classic Mealy ...
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vivado HLS or SDsoc for use openCV

I want to do an image processing by openCV on FPGA . But I do not know if I should use the SDsoc method or the vivadoHLS method. The size of the images I am going to process is large and I want to ...
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Carry bypass adder delay higher than expected with timing analysis

Good evening all! I am facing an unexpected behaviour of the timing analysis of my bypass (or skip) carry adder. In particular, the implementation of the adder looks correct to me, the Modelsim ...
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VHDL Knight Rider LEDs

I have this code for Knight Lights in VHDL and I have few questions. Why in shift_reg <= shift_reg(6 downto 0) & '0'; if( shift_reg(6) = '1') then the 6th ...
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VHDL statement meaning

Can someone explain to me what is the meaning of this statement in VHDL: ...
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1 answer
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By design, why does SystemVerilog logic type has 4-states possible but VHDL std_logic type has 9-states possible?

The SystemVerilog logic type can take one of these possible values per bit: '0', '1', 'X' and 'Z'. The VHDL std_logic type can take one of these values per bit: '0', '1', 'X', 'Z', along with 'U', 'W',...
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Pitfall with mixing of blocking and non-blocking assignments for the same logic/reg in SystemVerilog

VHDL has a clear distinction between signals and variables. Variables are always updated as soon as we assign a value to them. However, a signal is only updated at the end of the process block. In ...
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1 vote
1 answer
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VHDL FIFO w/ RAM

I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
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Is it possible to access signals in a DUT from a testbench written in a different HDL?

I believe such a question has been asked in the past but this is more comprehensive. VHDL provides "external name" where we use an alias in a testbench to access signals that exist down the ...
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-5 votes
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Cannot find the way to update to latest GHDL version

My problem is that I'm just trying to get some lateral knowledge aside university, so I stumbled upon VHDL and I am still fascinated by this language, but as I started researching, I've noticed that ...
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1 answer
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Syntax error Begin statement HDL 9-806

I have an error in the form of HDL 9-806 on the begin statement. The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
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Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"

Problem I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
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-1 votes
1 answer
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Experiencing issues with VHDL Code ModelSim: Wave Generation

I'm working on this project where I'm basically supposed to generate square wave (and other types of wave) using VHDL. The time period can be adjusted to either increase or decrease its frequency, and ...
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1 answer
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Issues with State Machine on FPGA

I've been tasked with making a state machine following the design requirements shown in the screenshot. I have everything mostly working and the simulation worked as expected. However, when I program ...
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3 answers
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VHDL timing confusion and possible metastability risk?

Timing, especially in sequential logic, confuses me a lot. I devised an example and drew a timing diagram and I would like to ask some question regarding it; all of them are about the same issue. Here ...
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1 vote
1 answer
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Resources for learning Open Source VHDL Verification Methodology (OSVVM) [closed]

I am looking forward to learn Open Source VHDL Verification Methodology (OSVVM). In this regard, I wanted to know the following: Can I use Xilinx ISE v10.1 and its in-built simulator for OSVVM based ...
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3 votes
1 answer
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Duplication of working PWM signal leads to unexpected behaviour

I am trying to control 13 different servos with my Spartan3 FPGA. For that, I need 13 independent PWM signals generated by my FPGA. The PWM module that I am using works perfectly fine when only one ...
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VHDL conversion between signed and float

I've a small IP core module which performs some operations on a float input. The module has been developed using vivado hls. As shown below, the float input of the module is taken as a ...
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What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a ...
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What is the SystemVerilog equivalent of the VHDL "library"?

I have been writing VHDL for a while. There, we have the concept of libraries, which comes in handy. I cannot find something of this nature in SystemVerilog. Is it true that SystemVerilog has no ...
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Modelsim: Debugging "NUMERIC_STD.TO_UNSIGNED: Vector truncated"

I might be able to post some code if needed, it's hard though cause the code is on a different machine. But I'm looking more a general approach to debugging this warning "NUMERIC_STD.TO_UNSIGNED: ...
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Signals acting weirdly in VHDL

I've always been told that a signal updates its values after a wait statement, or after a rising edge if we have for example if rising_edge(clk) then but in this testbench, after the first wait ...
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How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
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2 answers
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VHDL : "wait on" vs sensitivity list

I read that a process with a sensitivity list is equivalent to a process with wait-on statement at the end. Why does "wait on" statement have to be at the end of the process to behave the ...
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5 answers
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Why Hardware Description Language?

Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL? From wiki, A hardware description language enables a precise, formal description of an ...
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Alternatives to FSM in VHDL?

I want to design a UART using logic gates but I don't know if is there any alternatives to Finite State Machine. Coding a UART in VHDL using FSM is really easy and abstract, the programmer doesn't ...
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Type of X is incompatible with type of XXXX

I have the following code(I'm pretty new in VHDL): ...
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