Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Reading time from text file in vhdl code

I want to read time value from a text file in vhdl code. wait for 60 ns; In the above command, I want to read 60 from a text file. ...
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35 views

Xilinx IP in custom code

I work with Xilinx Vivado 2020.1 and a set of selfwritten AXI Stream components. My VHDL code allows to set the length of TDATA, TUSER, TID... freely over generic. This works perfectly until try to ...
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55 views

Long enumeration in VHDL to recognize a state machine

In order that Quartus II recognizes a state machine in a case / when statement the case must be applied on an enumerated type. In my code I am using a case on integer number going from 0 to 230. And ...
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22 views

Using VHDL integer_vector for a block ram type, how to restrict the integer range?

Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
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33 views

VHDL 2008 Implicit Condition Operator Error? or Not?

I found the edaplayground website where it seems you can use a variety of tools (if you know the command line options) to test your code. Moderate success so far, but when trying Cadence Xcelium 19....
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Elegant way to check a STD_LOGIC_VECTOR to be all zero

I'm working with Xilinx and VHDL2008. Is there an builtin elegant way to detect if a STD_LOGIC_VECTOR is all zero? I use if my_vector = (my_vector'range => '0') then at the moment and hope that ...
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45 views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
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41 views

How to implement a delay in my reset state or idle state in VHDL to wait for 100ns upon power up?

So how would you actually implement the "waiting for 100 clock cycles" in hardware/VHDL ? Just use a counter in the idle state that waits 100 clock cycles ?  What would this look like ?
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What Is the Simplest FPGA VHDL Platform to Get Started With? [closed]

I would like to teach myself the basics of VHDL. Can anyone recommend a SIMPLE board platform to get up and running? I want to stress that I am not looking for a board with a ton of features, but one ...
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VHDL Aggregate on Left Side of Assignment : Error in Simulator

I'm designing a counter with a combinational carry out (not registered). To do this I have a concurrent assignment to create the unregistered sum with carry by extending the unsigned input before ...
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Demo of designing a modern CPU in Verilog/VHDL [closed]

Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
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VHDL Clock Question

What is the difference between these statements in VHDL: if (clk'event and clk='1') then if rising_edge(clk) then Are they equivalent ? Do you produce the same behavior (outputs) ? Why would one ...
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28 views

Building a better staged 1's complement adder tree?

I'm trying to calculate the checksum of IPv4 and UDP messages coming out of my Ethernet controller module. The checksum calculation for both IPv4 and UDP is defined as 1's complement addition, which ...
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1answer
60 views

UART in VHDL testbench

I have two questions in general: I have this uart vhdl example code from https://www.digikey.com/eewiki/pages/viewpage.action?pageId=59507062 I tried to do a testbench but in the simulation the ...
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1answer
77 views

Problem with summer in VHDL

I'm trying to do a summer in VHDL, but when I try simulate, appear an error. The code: ...
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29 views

could anybody help me resolve this error?

library IEEE; use IEEE.STD_logic_1164.all; entity select_assignment is port(x1,x2,x3,x4:in std_logic; f1,f2:out std_logic); end select_assignment; --CREATE ENTITY architecture Behavior of ...
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1answer
64 views

Working of resize function in VHDL

I am using resize function as below to convert 32bit vector(temp2_32) to 16 bit vector(temp2). temp2<=std_logic_vector(resize(to_sfixed(temp2_32,3,-28),1,-14)); ...
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1answer
45 views

hardware software co-simulation in HDL simulator

When we simulate (VHDL) RTL designs in a simulation tool like ModelSim or ActiveHDL e.t.c, we can have a complete visibility of all signals and variables in the design. This goes a great deal in ...
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32 views

VHDL Integer Range Output Bus Width

I'm currently working on writing a simple counter in VHDL, trying to genericize it as much as possible. Ideally I end up with a counter that can pause, count up/down, and take just two integer (min, ...
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1answer
20 views

Vivado VHDL BRAM write-read Simulation not reading properly

So im trying to simulate a simple write and read memory program in Vivado design suite. Before implementing a clock in the sensitivity list on the process to write and read, the reading part used to ...
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1answer
52 views

VHDL Type memory question

My question is very simple i think, but i would be really gratefull if anyone can help me with this. When i want to write in the fpga memory using the classic following line code: ...
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20 views

How to create an array 1D X 1D X 1D with size 2X4X8 of type sfixed, STD_logic_vector, STD_LOGIC

Is it possibe to create an array of type sfixed or std_logic?
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4 X 4 multiplier signed using VHDL

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41 views

Importing foreign VHDL generic procedure with VHPI

I'm trying to learn the basics of VHPI (VHDL Procedural Interface) for linking my VHDL simulations to c++ code and have run into a bit of a snag. When I create a procedure with no generics (vhpi_Proc1)...
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101 views

4 by 4 multiplier unsigned

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64 views

my spi protocol in verilog is not working

I have written an spi protocol in verilog and it is showing error. here is the link from where i took the information for spi. https://www.nxp.com/files-static/training_pdf/26821_68HC08_SPI_WBT.pdf ...
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51 views

Vivado Simulator Error

I am simulating code in Vivado but it gives an error like this. ERROR: [VRFC 10-3180] cannot find port 'newsymbol_0' on this module ERROR: [VRFC 10-3180] cannot find port 'curr_0' on this module ...
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31 views

How to set pointer to a specific signal in VHDL testbench by using access type?

Access type is basically a pointer in VHDL although perhaps it is not exactly the same thing as a pointer in C. I have found many examples online whereby we are using the VHDL access type to ...
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1answer
42 views

VHDL: How to create a memory block with some elements being constant?

I have created a 2D RAM block, it is an array of 32 bit std_logic_vectors: ...
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1answer
50 views

Logic OR reset and clear?

I am trying to figure out the best practice for implementing a reset (async applied, sync cleared) and a clear input. I have a process that must run off a logic-derived clock (NCO) that is called ...
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33 views

CocoTB: VHDL Assert

I have code that checks all kind of input parameters with VHDL Assert statments like the following: ...
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1answer
79 views

VHDL Clock Divider Problem

I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code: ...
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1answer
73 views

Vivado “resize” simulation error

I write code that the sums of the squares of two numbers. If I write code that is shown in code 1 and run simulation according the this, I get like this blue arrow shown in picture 1 (for code 1). I ...
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18 views

Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...
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44 views

X values for signal

im having problems figuring the problem for this The LinkDataRAM receives data and is tested, (we='0' AND re='1') condition is matched and the RAM should read from ...
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43 views

Is there a difference between nested if statements and exhaustive?

Is there a difference between the two? I would expect maybe the first has delayed evaluation of conditions? ...
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1answer
83 views

Toggling the Output in VHDL

so I've been trying to solve some questions in the book Free Range VHDL. The question I have problems with is: Provide a VHDL behavioral model of the D flip-flop. The S and R inputs are an active low ...
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1answer
69 views

Not condition in if statement

say if i have a signal1, and i want to apply a condition on it how do i use the not conditions in VHDL? if(signal1 != "111") then end if; I dont want ...
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69 views

Concatenating a range from a signal

Say i had 2 signals and i wanted to concatenate a range from both signals how can i do it? Thanks ...
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45 views

Sensitivity list in process

i am currently having trouble with this code. The error detection unit outputs '0' to EDSOut to the EDSIn port of the controller unit The controller unit checks the value on the EDSIn port, if the ...
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1answer
44 views

Odd FSM behavior with counter signals

I am attempting to use a state machine to route AXI4-Stream signals and encapsulate them in network layer headers. I am using discrete states for each header to be appended, the payload, and then the ...
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1answer
51 views

How to use the newest version of VHDL in Vivado?

The below code gives me an error hat i cant read from out object Q Im sure newer version of VHDL supports it, how do i enable in Vivado does anyone know? Before i used GHDL compiler with a flag option ...
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47 views

Printing the value of a signal

Is there a way to print the value of a signal using REPORT? I've seen report "" integer'image(a) for integers. Is ...
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61 views

VHDL code which flip flop is this?

I have some doubts with the following code,is this a flip flop JK or SR latch? ...
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37 views

Generic mapping to a signal

i have this RAM below, i would like to be able to configured it during instantiation I want to configure the sensitivity list to process(clk) or process(addr) Is there a way to do this? My thoughts ...
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57 views

Clock cycle delays

im having some problems understanding why there is a half clock cycle delay between LinkDataI_S and the output port TransferOut which LinkDataI_S is connected to. Looking at ...
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33 views

Condition logic on local signals

Is it possible to both change and apply conditional logic on a local signals? I used internal signal to drive an output tried the below but got X1X1 for the output. Does anyone have any ideas? Thanks! ...
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46 views

Shifting a vector by a variable amount

Let's say I have a n level tree, where n starts from 0. Each level of the tree has 2^n elements. For the sake of an example, let's say n=4. Since we have 4 levels, we need 4 bits to hold the index of ...
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1answer
48 views

How to implement an interconnection matrix in VHDL?

I was reading through the documentation of the AXI standard when I came across the interconnection matrix shown below. In short, the interconnection matrix provides a path for several masters to ...
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1answer
37 views

Multiple processes value of signal

If i have 2 separate processes in 2 different components One with: address_regIM <= address_regIM + 1 And another with: y <= address_regIM If address_regIM has an initial value, what will be the ...

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