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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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50 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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1answer
30 views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
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Help to translate verilog code lines to vhdl

I tell you that I am new to this forum, I have limited knowledge of vhdl, but I am a novice in verilog. A couple of days ago I'm trying to translate a module from a verilog project to vhdl, but this ...
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28 views

Building a Regiser File - Instances of a Register [duplicate]

The Question asks me to build a register file. I'm aware a decoder, and two multiplexers are integrated in the circuit, and I've generated the VHDL code for it. I also know VHDL code has to be ...
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2answers
72 views

VHDL clock divider

I dont really understand the below code, for rising edge of the clock a divider of 4 bits will be incremented, so: 0000 -> 0001 -> 0010 -> 0011 For each rising edge of the clock? What is div(2)?
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46 views

Create a unique file name inside an entity instantiated multiple times

I have a design instantiating a component many times in different situations. I want to trace some internal behaviours it has using text file output. Here is a snippet example I use in a component ...
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43 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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1answer
88 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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47 views

Structural architecture

How does the compile know that the VHDL for component ND2 is a NAND gate? Its just a name ND2....
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108 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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50 views

Elaborating a VHDL design with Generics

So this query is related to DC synthesis compiler for digital design. I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters ...
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59 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...
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39 views

Error 3566 in vhdl

I get the following error message: ERROR:HDLParsers:3566 - xst/work/hdpdeps.ref line 20 Invalid date/time (".vhd") found. When I press on ERROR I get to the Xilinx site and it can't find ...
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405 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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1answer
31 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
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1answer
43 views

std_logic_vector to integer give always 0

I can't assign std_logic_vector to integer. What do I wrong? signal data_out: std_logic_vector(20 downto 0); signal d_value : integer; and in process ...
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1answer
64 views

VHDL Editor with lint and intellisense

Is there a freeware VHDL editor out there that supports intellisense and lint? There are plenty for other programming languages but seems like none for HDL.
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62 views

UART Transmit issue in VHDL

I'm working on a UART transmit process (uart_transmit) in VHDL (115200 baud, 8 data bits, 1 stop bit and no parity). I need the transmit line ...
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45 views

Strange SDRAM Behaviour

i try to use the SDRAM on my DE0 Board. This is the chip: http://zentel-europe.com/datasheets/A3V64S40GTP_v1.3_Zentel.pdf Basically my driver works. i save the value of an upcounted signal in the ...
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27 views

Difference between quantity and signal in VHDL-AMS

What is the most important difference between quantity and signal in VHDL-AMS? Can a signal takes a type of "real"?
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24 views

have real data types in vhdl and want to convert std_logic_vector; [duplicate]

I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL. I want the code below to be synthesized such that it ...
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92 views

UART RX in VHDL

I have to set up a UART transmitter and receiver using a Spartan 3 board. I've got the transmitter set up already and verified it with the arduino terminal using this FTDI breakout.The receiver is ...
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0answers
70 views

VHDL With Feedback and also JK Flip Flop

I have a circuit as shown below. And i have done its truth table and the state diagram. When i give "1001" as an input, i get "1" at the output. In order to simulate this i build the circuit in ...
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94 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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34 views

Exporting RAM content to text file in ISim

I'm trying to learn about Xilinx IP cores and FFT implementation on FPGA-s. For that I've created a simple project where I instantiate LogiCore FFT 8.0 core, ROM core and a RAM core. The ROM core ...
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1answer
64 views

Modelsim: resume simulation future

I have long running simulation in Modelsim for VHDL/Verilog designs. I want to know are there any way to save current simulation progress and resume it somehow in later time?
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1answer
118 views

UART receiver VHDL

VHDL FPGA UART receiver which receives 10 bits via Bluetooth interface. With 8 7-segment displays. Now my problem is the following In the requirements it is stated that I have to write the solution ...
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1answer
145 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
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53 views

What is the procedure to use ISCAS-85 benchmark Circuits for testing? [duplicate]

Could you please explain the detailed procedure about using ISCAS-85 benchmark Circuits for testing available at the below link http://web.eecs.umich.edu/~jhayes/iscas.restore/ How do we start, could ...
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1answer
127 views

Fixed-point arithmetic

I want to give two input data of my testbench from a file contains bits(std_logic_victor(15 downto 0) to some arithmetic operartion between fixed point and the files but when it starts I see below ...
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1answer
58 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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0answers
53 views

How to cascade frequency dividers

I'm implementing some modules using VHDL and for some of them I need the FPGA's global clock signal, and for some others I need to update to two different frequencies. A common solution to this is ...
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2answers
74 views

issue with booth multiplier VHDL code

I'm trying to build a 4-bit booth multiplier using VHDL. I don't know why but the process block is executed just once. The state does change from idle to busy then it doesn't work. ...
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2answers
81 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
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20 views

Creating a simple program on a specific MPSoC [duplicate]

I want to write a program in VHDL that takes two inputs and outputs their sum. I want to upload that program to my MPSoC- Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. I want to be able to ...
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1answer
61 views

One-hot fsm in vhdl

I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state ...
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1answer
60 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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61 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
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101 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
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2answers
75 views

Error implementing IIR filter on FPGA

I want to implement several IIR filters on an FPGA, using VHDL. The filters is for audio. I start out by implementing a single filter with the following transfer function: $$H_1(z)=\frac{304 -304z^{-...
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2answers
85 views

Is there anything macro-like, in VHDL?

I have a little piece of code, that applies again and again, in different places. The places are too irregular, the code is too small, and the input and varies too much to be able to use an entity. ...
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VHDL: Setting upper bits of variable to zero during assignment with shorter variable

When one has something like variable a : unsigned (3 downto 0); variable b : unsigned (1 downto 0); and one wants to assign the lower ...
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2answers
72 views

VHDL ieee.numeric_std: Division by zero defined?

As the title says, I'd like to know if the behavior of a zero division in ieee.numeric_std is somehow defined. If one does ...
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1answer
78 views

How to generate signal with glitches in VHDL?

I am working on an assignment in which I have to report the number of glitches in a signal. For the testing purpose I was wondering how can I generate a signal with glitches in VHDL?
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1answer
81 views

New to FPGA and need help doing a calculator

So I have a task on my hands to program an FPGA which can calculate a certain funtion value when given X and Y between 1 and 10. The function in question is 3*X^2+300*Y. I have written some sort of ...
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1answer
40 views

Using connected PC keyboard input for VHDL Simulation

I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
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1answer
62 views

Error when trying to use Verilog from VHDL in Lattice Radiant

I'm trying to use an IP generated with the IP Catalog in Radiant, which was only available as Verilog, from my VHDL top level entity. I use it like this: ...
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0answers
40 views

ROM initialization in VHDL for waveform generator

I have to create a waveform generator and i used matlab to generate the sine wave. Now my TA told me to store the points from the wave in a ".mem" file then initialize the ROM by i guess importing ...
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1answer
28 views

Creating DNF with variable in output column

I am trying to model an Arbiter in VHDL. For this I've created a Moore automaton and am currently mapping the output. The output should be when mapping from the state: ...
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3answers
60 views

How can I convert the number of DSP48/BRAM to the number of LUTs and FFs in FGPA

I have a trouble with estimation of logic utilization. I am Ph.D student who research the efficient implementation of signal processing algorithms. So, I have to compare the logic utilization of ...