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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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46 views

How can a processing delay be explicitly declared in VHDL?

Taking as an example the following simple multiplication: ...
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1answer
26 views

VHDL 2 segments coding style sensitivity list issue - std_logic_vector at X value

I'm having trouble with a counter update in my FSM. I have a counter being incremented inside a state: the state must change when the counter hits a constant value N. I try to slim down the code to a ...
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1answer
87 views

Is there a free tool for finding the observability of signals in a Verilog or VHDL code? [on hold]

I want a free tool for finding the observability of signals in a VHDL or verilog code. Which tool do you know for this?
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28 views

Random access memory design in vhdl [on hold]

ram is random access memory in its block I understand that it has address and data lines My quistion to you guys What is single port RAM ? What is dual port RAM ? What is means to have synchronous ...
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1answer
98 views

UART receiver in VHDL for nexys 4 ddr board

I'm trying to program my nexys 4 ddr board to receive 1 or 0 as ASCII charachters via UART and display it on one of its 7segment display ,the LED that shows when its getting data is flashing but it ...
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0answers
24 views

INTERNAL_ERROR:Xst:hdltool.c:4862:1.209 - Signal lookup_b.address, 0 ones:XX

I'm getting the above error message, and I don't understand what I'm doing wrong. I've only found one reference to that message, and it led me down this rabbit hole of trying to apply the ...
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2answers
77 views

Vending Machine - VHDL

I have been trying to implement a Vending Machine where the user selects P(2to0) P(2) : 3.5 Currency_X P(1) : 3 Currency_X P(0) : 2.5 Currency_X C(3 to 0) as coins 5 Currency_X / 2 Currency_X / 1 ...
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1answer
62 views

Signed Integer Division Optimization

I've implemented a division algorithm on an FPGA using the long division algorithm. My implementation does not use pipelining, but works iteratively and requires very few logic elements since the ...
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1answer
40 views

Xilinx Line <read_line> has not enough elements for target <input_b> for the file with more than one line

I have a file each line of which includes two 9 bits inputs. Here is an example of this file: input_vectors.txt: ...
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1answer
91 views

Removing Noise From an Image [closed]

Can anyone please help me with designing a verilog code for removing salt and pepper noise from an image.
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2answers
79 views

VHDL Wait until statement not behaving as expected

I'm studying VHDL and trying to simulate a UART design I took from this great book. I'm using vivado 2018.3. Here's the conceptual block diagram of the RX block: At this moment I removed from the top ...
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0answers
61 views

VHDL - How to add several numbers parallel

i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a ...
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1answer
91 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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1answer
29 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
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1answer
59 views

Finite State Machine Reset Signal FPGA

I've already done the datapath for my system using a synchronous reset and now I have to control everything using state machines. What I'm confused about right now is whether or not the reset signal ...
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1answer
66 views

GSM Modem Transmission Issue

I'm having a problem getting this GSM modem to work with an FPGA (Spartan 3). I've already implemented UART transmission on the FPGA side,the MAX232 to convert TTL->RS232, and 3.3V->5V logic level ...
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1answer
184 views

Moving brute-force search to FPGA

I am currently working on a scientific hobby project about computing the error detection capabilities of CRCs. Unfortunately the C++ code used for such computations has up to years of run time on ...
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1answer
114 views

VHDL Delimiter Character

I'm trying to define a string in VHDL with a pair of double quotes in the string itself. However I am unable to do so because the IDE (Xilinx ISE 14.7) only recognizes what's in-between the first pair ...
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1answer
80 views

Mimic object constructor in VHDL

I am writing IPbus Transaction Verification Model for UVVM and I have encountered some problem. I know potential solution, but I don't like it and I am not sure if it can be handled better in some ...
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1answer
37 views

VHDL: Getting U's for values after behavioral simulation

Now, bear with me I am not very familiar with VHDL and I am only a beginner but I am having a problem figuring out why the values of outputs remain uninitialized and I have been stuck with this ...
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1answer
47 views

VHDL SLV dynamic width slice assignment

I have some code that takes in 2^X samples and outputs 2^Y samples, where X and Y are integers and Y is less than X. So for example X=6,Y=4, I ingest 64 samples and output 16 samples. As of right ...
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0answers
45 views

Register readback for ADC WM8253

I am trying to read the contents of register written in serial mode of WM8253 using SPI in Basys 3 FPGA. Link to Datasheet. I'm reading from register '011100' but the result that is read is always "...
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0answers
42 views

HDL implementation of Numerical Analysis Techniques

I am looking for open-source implementations of Numerical analysis techniques (specifically root-finding techniques like the secant method) on FPGA using any HDL. Would also appreciate if anyone could ...
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1answer
44 views

VHDL - testbench hangs due to a problem with nested for loop

I encountered a problem when trying to simulate a D flip-flop design. Here's a snippet of my testbench code: ...
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1answer
75 views

How are Vivado's projects directories structured?

I'm working with Vivado to program FPGA's in VHDL. Can someone explain me what are the various directories that are created under the project's directory? In my projects, the following folders are ...
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1answer
171 views

Implementing a 4-bit ripple carry adder/subtractor using structural VHDL

I have to create a 4-bit ripple carry adder/subtractor. The circuit will have two 4-bit data inputs (A and B), a control line (Add/Sub), a 4-bit data outputs (S) and a carry out bit (Cout). I have ...
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1answer
48 views

VHDL initialize vector using readable integers not long binary string

So I am only starting out my VHDL journey. One thing I am finding a bit of a nuisance is the following format: signal sig_A : unsigned (3 downto 0) := "0101"; ...
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1answer
69 views

Feedback signal consumed in VHDL

Hello I'm new with VHDL and I'm trying to implement a JK latch in VHDL using this RTL schema: Where the "latch_rs" is written as follow: ...
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1answer
132 views

Unknown Formal Identifier in VHDL

I am facing an error with my VHDL code. I am new in it. After putting so much of my time I am even unable to resolve this error. I am using ModelSim software for it. Here is my code: ...
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0answers
56 views

Help to translate verilog code lines to vhdl

I tell you that I am new to this forum, I have limited knowledge of vhdl, but I am a novice in verilog. A couple of days ago I'm trying to translate a module from a verilog project to vhdl, but this ...
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2answers
140 views

VHDL clock divider

I dont really understand the below code, for rising edge of the clock a divider of 4 bits will be incremented, so: 0000 -> 0001 -> 0010 -> 0011 For each rising edge of the clock? What is div(2)?
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0answers
48 views

Create a unique file name inside an entity instantiated multiple times

I have a design instantiating a component many times in different situations. I want to trace some internal behaviours it has using text file output. Here is a snippet example I use in a component ...
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1answer
87 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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1answer
108 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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1answer
47 views

Structural architecture

How does the compile know that the VHDL for component ND2 is a NAND gate? Its just a name ND2....
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1answer
132 views

Why is there no latch in this circuit?

So I have come across this code and when I synthesize it I was surprised that there is no latch. ...
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0answers
56 views

Elaborating a VHDL design with Generics

So this query is related to DC synthesis compiler for digital design. I have a hierarchical VHDL design, with each entity having "Generics". When elaborating the design, should I add the -parameters ...
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2answers
82 views

Passing VHDL string generic with spaces via Modelsim command line

Given the following code: entity foo is generic ( VAL : string ); end entity foo; architecture behav of foo is begin end architecture behav; How can I ...
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1answer
446 views

Can I program a platform independent PLL in VHDL?

Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom ...
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1answer
47 views

Can I use custom data types to exchange data between modules in VHDL?

I'm new to VHDL and currently try to get more complex data types working, so that code becomes more readable... However, it seems that I cannot define a type in VHDL before the ...
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1answer
70 views

std_logic_vector to integer give always 0

I can't assign std_logic_vector to integer. What do I wrong? signal data_out: std_logic_vector(20 downto 0); signal d_value : integer; and in process ...
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1answer
87 views

VHDL Editor with lint and intellisense

Is there a freeware VHDL editor out there that supports intellisense and lint? There are plenty for other programming languages but seems like none for HDL.
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1answer
77 views

UART Transmit issue in VHDL

I'm working on a UART transmit process (uart_transmit) in VHDL (115200 baud, 8 data bits, 1 stop bit and no parity). I need the transmit line ...
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0answers
47 views

Strange SDRAM Behaviour

i try to use the SDRAM on my DE0 Board. This is the chip: http://zentel-europe.com/datasheets/A3V64S40GTP_v1.3_Zentel.pdf Basically my driver works. i save the value of an upcounted signal in the ...
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0answers
29 views

Difference between quantity and signal in VHDL-AMS

What is the most important difference between quantity and signal in VHDL-AMS? Can a signal takes a type of "real"?
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0answers
26 views

have real data types in vhdl and want to convert std_logic_vector; [duplicate]

I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL. I want the code below to be synthesized such that it ...
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1answer
121 views

UART RX in VHDL

I have to set up a UART transmitter and receiver using a Spartan 3 board. I've got the transmitter set up already and verified it with the arduino terminal using this FTDI breakout.The receiver is ...
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0answers
86 views

VHDL With Feedback and also JK Flip Flop

I have a circuit as shown below. And i have done its truth table and the state diagram. When i give "1001" as an input, i get "1" at the output. In order to simulate this i build the circuit in ...
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0answers
118 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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0answers
38 views

Exporting RAM content to text file in ISim

I'm trying to learn about Xilinx IP cores and FFT implementation on FPGA-s. For that I've created a simple project where I instantiate LogiCore FFT 8.0 core, ROM core and a RAM core. The ROM core ...