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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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15 views

SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL: ...
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0answers
22 views

Readout logic for semiconductor matrix [on hold]

There is a 8x8 pixel semiconductor matrix with built in serial shift register to readout the full array at clock period of 50ns and setup time of 20 ns. But the last row comes with an undesired ...
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1answer
30 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...
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50 views

FPGA/VHDL: Branching Input Signals

I was curious if it's possible, or if there is any harm, might be a better question, in branching an input signal within an FPGA design for multiple uses? What I was looking to do in my design is this:...
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31 views

In VHDL, what does the RHS of generic map assignment refer to? [on hold]

Based on my understanding of VHDL, a port map statement looks like: signal reset_n : std_logic; ... port map ( ... reset_n => reset_n ); ... where ...
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0answers
19 views

Signal in unit data is connected to following multiple drivers

I have attached an archived file in the link below. When I tried to generate a file, these are the error messages: ...
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1answer
60 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...
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0answers
35 views

vhdl testbench data type confusion

I am trying to simulate the XADC in vivado I have my testbench code here ...
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2answers
42 views

how do I implement a start timer in a digital circuit

In vhdl, I know how to code a start timer behavorially. However, if I have to implement such a counter to start based on a trigger, how could I implement such a counter? My trigger is another signal ...
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6answers
116 views

VHDL — When is a process block too long? [closed]

There is a great free (gratis and libre) VHDL book called Free-Range VHDL which is quick starter. As a neophyte, I am having difficulties judging the relative rules of thumb when it comes to process ...
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2answers
61 views

How do you cast an integer as a time in VHDL?

For the purposes of simplifying a test bench, I would like to set various delays by changing numerical values at the top of the file. I'd like to do something like: ...
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2answers
52 views

VHDL: ADC to USB Buffering using Fifo

I am trying to understand what is the correct way of doing such application, so please do not ask for complete code because each component is working fine on its own. I am struggling in the way of ...
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1answer
52 views

How do I override generic values in a VHDL testbench?

I am new to VHDL, and I'm working with an off-the-shelf UART block. I'm trying to create a test bench and override the data width, but I get errors saying that my signals are undeclared: ERROR - C:/...
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2answers
100 views

VHDL: Metastability check for hold time fails

I'm trying to model an SN74HC573 D-type latch in VHDL to get back into it. Here's what I got so far: ...
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1answer
44 views

How are processes evaluated in VHDL if a signal appears/does not appear in a sensitivity list and a nested IF statement?

In VHDL, are conditional IF statements evaluated when any signal in the process sensitivity list changes, or only if the signals are in the sensitivity list and appear as IF statement arguments? I ...
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1answer
47 views

Activating components one after another

I'm new with vhdl code. I have three (and) components and one (voter) component. I don't want to active those (and) components in one time, I want to active the first then, when I have the answer of ...
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1answer
56 views

Bus arbiter that can handle multiple concurrent requests vhdl

I am working through a weird problem. We are pin constrained on our FPGA and need to control a common bus. This was all fine and good as all the software was sequential, but now some requests will be ...
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0answers
47 views

Verilog localparam as string in vhdl?

I found the following statement in a verilog modul: localparam str2=" Display Demo ", str2len=16; Seems to me that str2 is a string value but I wonder how this ...
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1answer
54 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
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2answers
100 views

VHDL integer to unsigned cast cost

The code snippet below shows a two-step variable manipulation: 1) Convert an integer to an unsigned number 2) Cast an unsigned number to a std_logic_vector and extract a certain number of uppermost ...
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1answer
46 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
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1answer
76 views

Error (suppressible): (vsim-3601) Iteration limit Quartus

I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (...
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1answer
58 views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
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1answer
112 views

vhdl “wait until” in a loop

I get an error message "Error (10398): VHDL Process Statement error: Process Statement must contain only one Wait Statement" for this code ...
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1answer
50 views

Pass a signal in low-level entities and update it back in top-level entity in VHDL

I have tried a lot to pass a signal that is in a top-level entity, to a low-level entity as an in-port and do some operations on that signal and let the changes happen to the main signal. Here i just ...
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1answer
32 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
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1answer
61 views
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1answer
48 views

Possible test patterns produced by ATPG Software like Tetramax

I am developing a pattern generator in VHDL for testing ICs. The problem is I need to make it as universal as possible and need to consider a few factors such as output rate, binary or tristate etc. I ...
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1answer
171 views

In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?

I have an input device that can write in either serial, 8-bit parallel, or 16-bit parallel. I know the input frequency and max write speed of those data formats. I am given a requirement of a "64 ...
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2answers
59 views

Beginner VHDL doubt

constant <clock>_period : time := 10 ns; What is the error with this code ? it says syntax error near "<".
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2answers
99 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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2answers
69 views

vhdl generate multiple range

I have 2 checks which are similar, except by the range of the generate: All works OK, it looks like this: ...
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1answer
87 views

Modelsim simulation doesn't work Pleas help

I can't for the life of me figure out why I don't get an output from this testbench and entity that i've created. I've tried it several different ways with the OUTPUT y never making it out. I know ...
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2answers
114 views

Discrepancy between RTL schematic and Behavioral simulation in Vivado

I'm having a strange issue with a simple Vivado (2015.3) VHDL simulation. This code: ...
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1answer
69 views

Problem FIFO in the implementation (VHDL)

I was working in that for the past five days and I don't know what happened. I must implement a FIFO to send some information, I attach the FIFO that I use. As you can see in the code, this FIFO using ...
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0answers
60 views

VHDL File IO, write to specific line number

Is there a VHDL function that can write data to a specific line of a text file, without modifying the other lines? This is for simulation needs, of course.
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1answer
113 views

VHDL Error 10481 : no primary unit

I'm designing a circuit using Simulink to VHDL generator to be burned into a FPGA. Simulink model works fine on Simulink, however, when I try to compile the VHDL code using Quartus II I get the ...
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0answers
40 views

Vivado HLS pipeline with inconsistent interval

I have a function that I want to pipeline and sometimes the next inputs will be ready four clocks later, but sometimes 6 or more. I set the pragma to ...
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1answer
87 views

In VHDL 2008, can a type from a package with generics be used for a port signal?

So I can define a package with a generic - in this case, the package takes a size as a generic and defines a vector type of that size: ...
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2answers
97 views

VHDL constant intermediate calculation

Does VHDL specify how intermediate calculations are handled? For example, I have the following constant defined in one of my entities. ...
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1answer
46 views

2^4 finite field multiplication in VHDL

I am currently trying to optimize a 4-bit finite field multiplication modulo X^4 + X^3 + 1 that I've made in VHDL. I did a 16x16 array containing all the results of ...
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1answer
57 views

Producing a VHDL design unit from a State Diagram

I need help understanding a stateflow diagram. I'm supposed to design it in VHDL as a beginner's exercise. I've gone through the VHDL tutorials on nandland.com, and could say I understand the basics ...
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2answers
139 views

FPGA double buffer strategy

I am working on a FPGA project where a host CPU writes a 10,240 x 16-bit look up table into FPGA logic. To implement this, I've utilized on-chip memory to store the values and read them out when ready....
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0answers
41 views

VHDL Xilinx IP Core Divisor problem for signed fixed point

I hope you can help me since I believe this is a very specific error and I do not know how to solve. I want to divide 2 numbers represented like: 4bits : integer part 4bits : fractionary part So I ...
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1answer
66 views

VHDL to RTL/schematic, not what I expect to see

I'm teaching myself VHDL (using Altera Quartus Prime Web Edition) so we can incoroprate a CPLD into a design. I've only been doing it a few days but so far the VHDL itself seems reasonably ...
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0answers
61 views

vhdl oneline pulse simulation

I wolud like to use simple oneline code snippet for generating single clock cycle positive pulse pulse <= '1', '0' after CLK_PERIOD; However, it is not ...
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2answers
53 views

question about Vivado synthesis and implementation

I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and ...
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0answers
103 views

Conditional generate statements in vhdl

I have a generic parameter H. I would like to make a sigmoid function(f) calculator which computes f(x) for H number of inputs concurrently. I am using H number of MAC units which gives ...
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1answer
95 views

128-bit data UART

I have made a UART controller in VHDL (transmitter, receiver and a FIFO for each component) and I'd like to send/receive 128 bits of data. Is there anything that prevent me from implementing a 128-...