Questions tagged [vhdl]
VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.
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VHDL Uninitialized Output Active-HDL [closed]
I am trying to simulate an OR gate component in VHDL using Active-HDL. I have coded up the component and a corresponding test bench. I am unable to get the output pin to show up as either '1' or '0'. ...
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Why does my DSP block not utilize output register? [closed]
I have compiled design in Quartus 18.1. Here is a screenshot of the HTML report for "dsp block details".
The code I have written registers the inputs into the multiplier and also the output ...
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Correct SPI interface timing constraints
I'm struggling setting up timing constraints for an ADC SPI interface.
The design is a simple ADC Master interface working at 25 Mhz, same frequency of the system.
First of all I gated the output SCLK ...
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VHDL: is this RAM design over-complicated?
I am trying to design in VHDL a RAM model. The idea is to being able to implement the different load instructions (lb, lh and lw) present in the RISCV ISA (the overall project is to design a complete ...
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Vivado Behavioral Simulation Incorrect Signal Values
I am trying to test out a module I made in VHDL using Vivado. I am having some issues with my test bench though, as in I don't even see the clock signal changing.
The snippet of code below shows me ...
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Making memory in FPGA and how to use the SDRAM on De1-Soc board
Im working in a project with A FPGA board (De1-Soc - Cyclone V) and in project there is supposed to be an internal memory to make connection with rest of the system and read or write some data in it.
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Latches Due to Asynchronous Load of a PISO Shift Register
What appears to be a simple problem raises a few questions regarding latches.
In trying to replicate a TI SN74HC165 PISO shift register within an iCE40UP FPGA, I've come up against a situation where a ...
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32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA
I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
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Weird FSM behavior on the start only
I am a vhdl beginner working on this entity that goes through 256 12bits inputs alternating with even index inputs in "a_s" and odd ones in "b_s" and this 16 inputs at a time (8 in ...
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Finding the largest std_logic_vector in an array (VHDL)
I am trying to create an output layer classifier for a neural network that is implemented on FPGA (in VHDL). The classifier should simply return the array index that contains the largest ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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VHDL: Assert generic range and produce error with full instance path if it fails
In my VHDL entity there is a generic that has integer value. I have written an assert statement to check its range. I believe that the assert statement will execute when the module is simulated and ...
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MachXO2 VHDL Internal Oscillator - "ERROR: formal nom_freq is not declared"
I am trying to run the code below, but I get an error on line generic map(NOM_FREQ => "2.56"); and I am very confused why. The error says "ERROR - ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Why does the white space get included while reading a string from a file in VHDL?
I am trying to read data from a text file in VHDL which includes two vectors and single character.
While reading, white spaces are not detected for the numbers but are detected for the character.
Why ...
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Whats the error?
I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct.
Someone can tell if I'm missing something, please.
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How to correctly write and read to/from SRAM on FPGA with VHDL?
I want to write 512KByte data on SRAM(IS61/64WV512).I'm using spartan6 lx9 FPGA. In the program routine, the initial step involves writing all the data. Subsequently, upon completion of the writing ...
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Output Variable stays unintialised in my VHDL testbench
I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop.
Following is the VHDL code that I have written:
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VHDL: Keep multiple files open until end of simulation [closed]
In my testbench I write to several outputs files as the test proceeds. These files are later processed by a Python script to generate meaningful data. The testbench writes 100,000s of lines of data in ...
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I'm trying to build a FSM in VHDL but the Mealy state machine won't change states
I'm trying to build a Mealy Finite State Machine in VHDL. each time a button 'btn' is pressed, the FSM should go to the next state. There are 4 states, s0, s1, s2 & s3. s0 is the state at which ...
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VHDL: textio variants of the write function for real data type
Here are the two variants of the write function that can be used to write the "real" data type into file or stdout.
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Difficulty understanding the need for multiple-register pipelines for signals [closed]
When I studied the GPIO demo code for Basys3 to create my own VGA controller, I noticed that multiple registers are used for a single signal, like h_cntr, H_sync, V_sync, VGA_R, VGA_G, VGA_B, etc. I ...
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D latch module in VHDL using NAND structure [closed]
What is the difference between a positive-level D latch and a negative-level D latch?
How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
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A NAND gate with propagation delay in VHDL
I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL.
\$t_{PLH}\$ = Propagation delay low to high
\$t_{PHL}\$ = Propagation delay high to low
This is first code.
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How do I implement a simple axistream by my self bus in VHDL?
I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
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Generating an 80 MHz clock from a 100 MHz clock with VHDL in Spartan-7
I am new to VHDL and am targeting a Spartan-7 FPGA, using VHDL. For technical reasons I have to develop outside the Vivado or other environments. It seems like there are several posts that have ...
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Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&'
It may be a simple fix, but I do not understand the error:
Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&'
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Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL
I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
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Encryption of Verilog/VHDL module
I don't have encryption licenses for Vivado or Quartus to encrypt my Verilog/VHDL modules and so I cannot give my RTL to any user. I don't want to give out synthesized netlists but only encrypted RTL.
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Packaging synthesized design as netlist for use in future designs
I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
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Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado
I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL ...
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Use VHDL to create a simulated EEPROM component for testbench
I have created a component for a simulated, serial EEPROM to use in a testbench. The logic for performing the SPI communications is straightforward. In addition, I have created a byte array, with ...
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PSL usage in Formal Verification, assertion problem
I am investigating the usability of formal verification in FPGA designs using VHDL, PSL, SymbiYosys, and GHDL. I've watched several webinars, read a PSL book, and gone through tutorials. Currently, I ...
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(vcom-1136) Unknown identifier "std_logic" & "std_logic_vector"
I am relatively new to VHDL, and I am getting the errors below although I used the same procedure before:
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Formal HDL verification with PSL
I am trying to learn Formal Verification for VHDL design (using Property Specification Language). My module has an active-low reset input. I would like to drive tool to set the reset input to '0' for ...
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ICM-42688-P read from address not given in Datasheet
I am currently working on software for a project that involves an ICM-42688-P sensor IC.
The FPGA uses a 16-bit SPI interface and needs to read this data block of 16 bytes:
Datasheet Page 60, 13.1
So ...
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Does SystemVerilog have (others=>'0') expression like VHDL?
In VHDL, we can set all bits of something a value by using (others=>'0'). It is also possible to use slice index e.g., ...
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VHDL modular multiplication always resulting 0 in simulation
I'm trying to implement a modular multiplication algorithm in VHDL, but the result "r" is set to 0 on every simulation. I would like to know how to fix it.
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Drawing a Visual Hardware Representation for VHDL Code
The following code is given. My task involves drawing a visual hardware representation that outlines the modules, their associated ports, and the interconnecting signals. Check out my solution below. ...
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Select bit in std_logic_vector based on unsigned with multiplication
Is the following allowed in VHDL(2008)?
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When I try to simulate VHDL code, the signals do not work, losses, show a orange color
I'm using a Nexys 3 Spartan 6 Lower Power XC6SLX16L.
The idea of the program is with a timer counter with specific conditions with the bottoms.
Here is my code:
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Why do I still have latches even though I include everything in sensitivity list?
The following is the code snippet which generates the inferred latch warning.
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Is there any way to know how real discrete components are being connected to each other using logical gates?
Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each ...
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VHDL schematic without connections [closed]
I'm learning VHDL and I tried to replicate a circuit that I found surfing in internet. The problem is that the schematic shows without connections in the input ports.
The program is a frequency ...
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How to model a 4-way inout crosspoint switch in VHDL?
I want to model a crosspoint switch with 4 inout ports that can route a signal coming from any of the inout ports to any other ...
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Choose the right strategy to divide two values [closed]
Info:
After getting some comments and already one answer, I decided to rewrite this question to better fit into this site.
I had a problem where I needed to downsize a 12 bit value to an 8 bit value. ...
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VDHL - Using multiple I2C devices with single IP
I need help with a design that I am currently working on. I am using a Spartan 3 that is on a custom board that checks 6 devices using I2C and these devices all have the same address so I am trying to ...
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Using Atomminer AM01's fpga for purposes other than mining [closed]
I was thinking about Using Atomminer AM01's fpga for purposes other than mining, maybe using vhdl or verilog, I wanted to ascend if it is possible?
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