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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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111 views

Fixed-point arithmetic

I want to give two input data of my testbench from a file contains bits(std_logic_victor(15 downto 0) to some arithmetic operartion between fixed point and the files but when it starts I see below ...
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62 views

Fixed point error in vhdl

i need two do some arithmetique operation .so my all programme is two fifo and the top module .My probleme is when i want to read data that sending by fifo .i write a test bench for reading a text ...
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50 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
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46 views

How to cascade frequency dividers

I'm implementing some modules using VHDL and for some of them I need the FPGA's global clock signal, and for some others I need to update to two different frequencies. A common solution to this is ...
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2answers
57 views

issue with booth multiplier VHDL code

I'm trying to build a 4-bit booth multiplier using VHDL. I don't know why but the process block is executed just once. The state does change from idle to busy then it doesn't work. ...
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31 views

Constraints file for Peripherals

I am trying to connect a PIR motion sensor to my Elbert V2 Spartan 3A FPGA board and then have that activate an LED when the PIR activates. The PIR is connected to GPIO 1. Although the code compiles (...
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2answers
71 views

Strange behavior in VHDL design (randomly incrementing values)

I have a fairly simple VHDL design that looks like the following: ...
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19 views

Creating a simple program on a specific MPSoC [duplicate]

I want to write a program in VHDL that takes two inputs and outputs their sum. I want to upload that program to my MPSoC- Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. I want to be able to ...
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1answer
38 views

One-hot fsm in vhdl

I'd like to code a one-hot fsm in vhdl. I've done many in verilog but my current employer prefers vhdl. In verilog I'd use the "inverse case statement" (case 1'b1) to compare each bit in the state ...
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1answer
51 views

Is it possible to infer a floating-pt multiplier in hdl coding without instantiating the IP?

My architecture details FPGA Implementation Floating-pt format (IEEE 754) At least 17 to 18 arithmetic operations (adders and multipliers) involved. Currently instantiating the floating-pt IPs of ...
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45 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
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91 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
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56 views

VHDL Clock signal not working correctly when used outside of main file it is defined in

I am coding a VHDL frequency meter that needs several clock signals to get the job done. When taking these signals from my frequency meter the ones that I port map directly to another component that ...
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2answers
57 views

Error implementing IIR filter on FPGA

I want to implement several IIR filters on an FPGA, using VHDL. The filters is for audio. I start out by implementing a single filter with the following transfer function: $$H_1(z)=\frac{304 -304z^{-...
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2answers
70 views

Is there anything macro-like, in VHDL?

I have a little piece of code, that applies again and again, in different places. The places are too irregular, the code is too small, and the input and varies too much to be able to use an entity. ...
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34 views

Created a 16 bit word - 2kB memory element in vhdl, are inferred latches bad here?

Here is my code that I used to create a 2kB 16 bit word memory element in vhdl ...
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0answers
44 views

VHDL: Setting upper bits of variable to zero during assignment with shorter variable

When one has something like variable a : unsigned (3 downto 0); variable b : unsigned (1 downto 0); and one wants to assign the lower ...
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2answers
54 views

VHDL ieee.numeric_std: Division by zero defined?

As the title says, I'd like to know if the behavior of a zero division in ieee.numeric_std is somehow defined. If one does ...
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1answer
56 views

How to generate signal with glitches in VHDL?

I am working on an assignment in which I have to report the number of glitches in a signal. For the testing purpose I was wondering how can I generate a signal with glitches in VHDL?
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42 views

Need help to develop two timers that takes input from keypad and timer can change on the fly in my project Traffic light Controller in VHDL

Here Pmodout is Output that is coming from keypad decoder. I am trying to figure it how to apply two inputs from keypad for different timers TS and TL while running my traffic light controller project....
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1answer
72 views

New to FPGA and need help doing a calculator

So I have a task on my hands to program an FPGA which can calculate a certain funtion value when given X and Y between 1 and 10. The function in question is 3*X^2+300*Y. I have written some sort of ...
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1answer
33 views

Using connected PC keyboard input for VHDL Simulation

I am working on a project for school that will involve an input from a push button or related device. We have only a few Spartan boards available, but we have access to Xlinx Vivado to simulate an ...
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1answer
53 views

Error when trying to use Verilog from VHDL in Lattice Radiant

I'm trying to use an IP generated with the IP Catalog in Radiant, which was only available as Verilog, from my VHDL top level entity. I use it like this: ...
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28 views

ROM initialization in VHDL for waveform generator

I have to create a waveform generator and i used matlab to generate the sine wave. Now my TA told me to store the points from the wave in a ".mem" file then initialize the ROM by i guess importing ...
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1answer
25 views

Creating DNF with variable in output column

I am trying to model an Arbiter in VHDL. For this I've created a Moore automaton and am currently mapping the output. The output should be when mapping from the state: ...
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3answers
47 views

How can I convert the number of DSP48/BRAM to the number of LUTs and FFs in FGPA

I have a trouble with estimation of logic utilization. I am Ph.D student who research the efficient implementation of signal processing algorithms. So, I have to compare the logic utilization of ...
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0answers
44 views

Dual slope ADC converter VHDL

Hi I'm trying to write a code for dual slope ADC. And I"m not sure if my logic is wrong or if there's something else that's wrong. ...
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32 views

ANDing a vector with bit

i am writing a vhdl code for a multiplier which multiplies a 4 bit vector (a) with a 4 bit vector (b) using a 4 bit full adders so in one stage i want to multiply each bit of a by b(0) so can this ...
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1answer
54 views

Implementing a simple counter using VHDL

Hi I'm trying to implement a counter with external control. I'm kinda new to VHDL and I keep getting syntax error for the following code. Can someone help me understand why there's an error here? <...
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1answer
38 views

Using VHDL with the Mojo V3 FPGA

I was just wondering if there's any way for me to write VHDL code, that I can then upload to the Mojo V3 board? The Mojo V3 IDE is Verilog/Lucid friendly, both languages that I'm unfamiliar with. ...
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1answer
67 views

How to display Numbers on the VGA display in VHDL?

I have a code to display block on the VGA display but I want to display numbers on it. I have a slight idea how to design it but Programmatically, I am having a hard time. I can define it as a ...
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76 views

Illegal concurrent statement

i really don't have a clue why this code is wrong. ...
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1answer
40 views

VHDL Error “ Integer literal is not of type ieee.std_logic_1164.STD_LOGIC_VECTOR.”

I'm new to VHDL and I'm getting the following error when I try to compile my code: ...
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1answer
39 views

Addition of 2 unsigned values in VHDL IEEE numeric_std : why this choice?

In VHDL, the IEEE numeric_std package does not behave as one could expect. The addition of two unsigned values coded on 8 bits is not given on 9 bits, but on 8 bits. What are the reasons of this ...
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42 views

Add 1 bit number to larger number

I have written vhdl code for Brent Kung 8 bit adder. It works fine and adds two 8 bit numbers a and b. Unfortunately Carry-in value when it is 1 ,Brent kung method does not tackle this.I have to ...
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1answer
54 views

Code parts encapsulation method

I have a prototype of a simple monostable multivibrator components like this: ...
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2answers
50 views

Is there a preferred order VHDL case/when and rising/falling_edge statements in processes?

What pitfalls are there in putting my rising_edge check within a case/when block? I have VHDL that uses code similar to the first example below and simulates correctly and is synthesizable. However, ...
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1answer
39 views

how many low observable signals in iscas benchmarks do we have?

How many low observable signals in ISCAS benchmarks do we have? For example in c17, c432, .... I mean in a circuit there are some signals we don't see them for example 99% of times in output, and we ...
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1answer
54 views

VHDL unranged integer input ports bad practice?

I'm designing a customizeable interpolation filter and I'm looking for the best way to pass the coefficients (rather supporting points) to the filter. Below you see the current implementation. ...
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1answer
74 views

VHDL multiplication for std_logic_vector

When simulating I get a run time error, so I'm trying to run a RTL analysis in Vivado to see if the schematic of the component can be created at least. The code is the following ...
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2answers
119 views

Package detection in datastream on FPGA

Hardware: I have an asic-"sensor" which sends me 32-bit packages (serial). I need to detect this packages with an FPGA. When I start the readout, the sensor is sending me data-packages until I stop ...
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52 views

VHDL test bench doesn't output/print warnings for timing violations

Here is my situation: I want to simulate a presettable 11-bit counter made up of three binary counter CD74AC161 chips. I also want the simulation to detect timing violations (setup time, hold time, ...
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1answer
71 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
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1answer
145 views

Vivado simulation stuck at 0 fs

I am trying to simulate a D flip flop using Vivado 2018.2.2. But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is ...
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1answer
100 views

Undefined signal in simulation

I am trying to verify a design written in VHDL using SystemVerilog's assertions. however I got a problem when I have a non defined signal'X' Just for example here is a code of a Comparator: ...
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1answer
38 views

SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL: ...
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1answer
36 views

VHDL Output is Unitiliazed or Zero when simulated

I am new to VHDL and implementing a test bench. I am trying to write code for a simple 2:1 MUX where the output of the MUX enters an active high synchronous LOAD register. Inputs and outputs are 8 ...
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0answers
65 views

FPGA/VHDL: Branching Input Signals

I was curious if it's possible, or if there is any harm, might be a better question, in branching an input signal within an FPGA design for multiple uses? What I was looking to do in my design is this:...
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1answer
84 views

I2S output in VHDL

I am making an I2S output in VHDL for a project. This is my first project using VHDL and the problem may be my basic VHDL understanding. This is my code: ...
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44 views

vhdl testbench data type confusion

I am trying to simulate the XADC in vivado I have my testbench code here ...