Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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26 views

How to output a determined number of characters in VHDL regardless of the input

I´m working on a code VHDL with a RAM memory which purpose is show me the output data in the TeraTerm software. I enter the data via the Arduino COM window (The Arduino MEGA 2560 is connected to an ...
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1answer
56 views

How many multiplexers is too much?

This is a general question. I have a specific task that I am working on. For this task, my solution requires around 300 multiplexers with all of them 16 inputs and 16 bits per input, and a single ...
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19 views

Test Bench Model for an EightBit Universal Shift Register

Hi I'm having trouble running the code simulation. I need to know where this is the error because the program doesn't show me anything. ...
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1answer
25 views

Synchronous Incomplete Assignment or How is Register Retention achieved

I just realised that Latch creation upon incomplemete assignments only happen in a non clocked enviroment. So far I have written all my synchronous code unnecessary avoiding incomplete assignments ...
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EC SIMULATION vs Static Timing Analysis

What is the difference between simulation of the code after deployment into the FPGA board and doing Static Timing Analysis of the model while the model was already deployed into the FPGA board?
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UNABLE to get waveforms in my model sim [closed]

Hi guys, i installed model sim and it was working fine till yesterday but dont know why itstarted working cray from last night and not giving me waveforms i though the issue is due to .wlf (vsim) file ...
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23 views

Interface VGA monitor with DE2-115 board and NIOSII processor

Currently, I'm working on a VGA part of my project. It's pretty simple, I want to interface with single pixels on the screen. I found a pdf, I will leave a link below, where it is explained step by ...
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2answers
55 views

Does the form of digital circuit representation matter and why? [closed]

Do hardware engineers really care if digital circuits were designed at the gate level, boolean expressions or behaviorally, assuming these circuits can be generated automatically. Does the form of ...
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24 views

VHDL testbench for shift register 7495

I`m new to VHDL and i don't know how to write the testbench code for a 7495 register. I need to do this for a college project. Any help is greatly appreciated. This is the Design Source code i`ve ...
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37 views

My VHDL doesn't detect all transitions of a signal

After a few tutorials, I'm writing my first VHDL entity of my own. Given an input signal and a 50MHz clock, it's supposed to emit a 6-clock-pulse strobe (120μs) when the time between two transitions ...
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47 views

Which method to use for BCD division in VHDL

I'm required to build a system (prime number checker) for my advanced digital electronics class that makes use of a 16-bit BCD division module. The module has been specified according to the following ...
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1answer
25 views

multiple source error

I keep on getting an error of multiple source. Here is my code for the testbench I am making. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ...
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23 views

error loading design

I am trying to simulate a testbench. I have compiled the testbench and the file it is testing and everything compiles without errors. When I try to simulate the testbench it says "error loading design"...
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1answer
36 views

How can I troubleshoot an 'unknown identifier' error in my VHDL project?

I'm trying to connect between two components: my TOP_LEVEL component's outputs two my BIN2BCD component which converts binary to BCD. the problem is that the BIN2BCD uses std_logic_vector, and my ...
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38 views

How to use VHDL Entity in logisim evolution?

I'm new in Logisim and VHDL. I'm trying to use VHDL entity-component but the output always is "x". Then I read a document ( this link ) that said Logisim requires ModelSim to use this feature. So I ...
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Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...
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39 views

Vivado is not properly gating my registers?

I have a register which holds 12 bits written in VHDL within Vivado which is not being gated properly. The code is very simple, and is as follows: ...
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29 views

VS Code with Lattice Diamond (FPGA)

a little diffrent question, Have here someone who using Lattice Diamond software together with VS Code or maybe its relevant to any external text editor. I changed the default text editor to VS ...
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1answer
117 views

VHDL - big difference in schematics between integer with and without range

I just discovered something that I would like some expert to comment on. CODE EXAMPLE A: ...
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27 views

Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...
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1answer
21 views

Cannot Find the Syntax Error Near Process

I'm very new to VHDL and this one must be a really easy question. The code gives me the error that there is a syntax error near the last process, please take a look: library IEEE; use IEEE....
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2answers
54 views

VHDL: Kan sequence of if/else be optimized?

I am new to VHDL and I try to find all places where I can replace if/else statements with cases of inlined OR/AND operations to get more things executed in parallel instead of sequence. Now I have ...
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1answer
23 views

VHDL Test Bench Help - How to get testbench to output values instead of “unknown”

I have the following two files, and I'm trying to test the first file. The first file is a simple ALU which handles a variety of functions depending on the value of a selection input. I've played with ...
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1answer
35 views

VHDL IF statement not behaving as expected

The code is implementing an ALU. I've tested individual bits, but as I try to do the if-statement at the end, which is implementing a specific conditional function, it does not work. I'm using xilinx ...
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19 views

Process does not work as it should (VHDL)

As far as I know, in order to change the output, one of the inputs in the sensitivity list should be changed too. If one of the inputs is left out of the sensitivity list, then the FPGA board should ...
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3answers
44 views

Why to use signal in this VHDL code?

Here is my code for 4 to 1 mux: ...
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1answer
58 views

How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
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2answers
80 views

Access elements randomly in RAM based FIFO VHDL FPGA

The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...
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30 views

VHDL: how to take a character out of a string

I have an array of strings. A state machine is supposed to take one at a time, then push it to a FIFO character by character. The fifo is of an std_logic_vector(7 downto 0) type. What is the syntax to ...
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49 views

Unexpected behavior when dividing clock multiple times in VHDL

I am playing around with some example code for a clock divider. When I try to chain multiple dividers together to further divide the frequency, I get unexpected and unpredictable behavior. Depending ...
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1answer
55 views

Frequency Measurement using FPGA and VHDL [closed]

I am not very experienced at VHDL coding. I want to measure the frequency of my input signal. It varies between 1 Hz to 150 kHz. And my clock frequency is 250 MHz. I wrote some code but it is not ...
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51 views

Why am I getting weird behavior when building 4-bit down counter?

I'm attempting to build a 4-bit modulo-10 down-counter (i.e 9,8,7...,1,0,9,8,7...0). Here is my code so far: ...
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1answer
67 views

How To extend bits in a VHDL code

I'm trying to do the following let's say bit extension in a generic way. First Considering B signal with an even number of bits (NBITS). here is an example: B = 10100011 Second, adding a zero bit ...
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27 views

How do I write a requirement of an asynchronous input signal, when the sampling clock has a certain resolution?

Let's say I have an asynchronous input (let's call it enable_h). This signal is supposed to be active high for 100us. My 2mhz clock is double-registering this async input. So once it is in my clock ...
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1answer
30 views

Assign record to different type without conversion function in VHDL

Brief introduction to the issue I am trying to solve. I have type, which is a subtype of std_logic_vector, representing generic frame. I have also few record types, ...
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75 views

AXI STREAM FIFO VHDL Implementation

Is this a right implementation of an axi stream fifo? ...
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33 views

Is it possible to assert that particular formal port is associated in the instantiation in the VHDL?

Is it possible to assert that particular formal port is associated in the instantiation in the VHDL? I have some entity with generic. Based on the generic value one of the input ports must be ...
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1answer
74 views

Error (10500): VHDL syntax error at ZAD1.vhd(7) near text “;”; expecting “:”, or “,”

So basically I am doing the 7-input NAND gate and the syntax error keeps showing up (Error (10500): VHDL syntax error at Router.vhd(39) near text "port"; expecting "(", or "'", or "."). ...
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1answer
42 views

Problem with Octal to Binary in VHDL

it,s me... Again. I tried almost everything but i can't make it work properly. This is my code: ...
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1answer
56 views

Problems with hexadecimal table in VHDL

I want to convert from binary to hexadecimal but I found a few problems with VHDL in Quartus II. ...
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1answer
61 views

Should I really prefer to use std_logic type to write sythesizable VHDL?

Recently while reading a Xilinx's "Synthesis and Simulation Design Guide", I came over a passage (p. 40) where they recommended the usage of the std_logic data type....
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2answers
81 views

When developing an algorithm for FPGA, should I be aware of amount of logic blocks (and other FPGA-specific properties)?

I want to see how certain algorithm would fit FPGA architecture and plan to implement it with HLS tool like CλaSH which produces VHDL/Verilog. All I know about FPGAs so far is it's an array of ...
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82 views
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67 views

How to reduce Worst Negative Slack and Total Negative Slack in my design?

I have an I2S transmitter with an AXI-Stream interface. AXIS_I2S ...
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2answers
54 views

Inferred latch warning on out port in VHDL

Disclaimer: this is beginner question. I can't figure out why o_address gives an inferred latch warning in post-synthesis and how to fix it. When I try to assign it it gives another warning: design ...
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30 views

Loop Filter in an ADPLL

I am implementing an ADPLL in an FPGA with VHDL, and I am encountering a problem in correctly implementing the loop filter. The code that I currently have for the loop filter is the following : ...
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2answers
87 views

How to manage PoR (Power-on Reset) on FPGA

How can the state of the registers upon PoR can be managed? My first idea was to detect the reset and manage the state inside a state machine, but I suspect the solution is not optimal. Are there any ...
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47 views

Increasing Locking range of ADPLL in VHDL on FPGA for FM Demodulation?

I am trying to implement an all digital PLL so as to demodulate an FM signal from the input. The centre frequency of the test signal is that of 140kHz. The system works fine upto a deviation of +-...
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1answer
60 views

How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?

I have a design on an iCE40 FPGA, I use iCEcube2 to compile the VHDL code and in my design I try to infer two small RAM buffers. The type of the buffers is as follow : ...
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1answer
68 views

VHDL: Output is always U

I'm very new to VHDL, please excuse my question. My output values are always U. I cannot figure out why. This is my code: ...

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