Questions tagged [vhdl]
VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.
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Help using DSP48E and adding it into code
I'm trying to work on a school project, and we have to use DSP48E and I'm having some trouble using it. I've decided to use the MACC_MACRO inst: MACC_MACRO example given in VHDL.
My questions are:
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Signal Tap in vhdl error problem "sld_hub" [closed]
when im trying to run a signaltap on my vhdl code its showing me the same error every time even in different codes
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Questasim Unable to find VHDL package not compiled into work
I'm currently trying to simulate a VHDL module with a SV testbench.
The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the ...
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is this signal command_signal in sensitivity list ignored in synthesis?
the following process is part of my vhdl code. But I am not sure whether this works after synthesis.
Are counter_sdin and command_signal ignored during synthesis?
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Initial value for index[3:0] is ignored for synthesis
My code works perfectly under Windows quartus. But when I am using hdl designer (Siemens) under Centos, I have the following problem.
There is no info about this "compile_initial_values" ...
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How to write tests for a clock signal
I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests ...
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Parsing variable-sized data in 32-bit datastream
I have a 32-bit datastream coming from a sensor. The data is encoded as a Type-Length-Value encoding. This means the first byte indicates what kind of data there is and the second byte contains the ...
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Intel DCFIFO IP crashing when using a clock with decimal place
I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock.
The data are read from an SDRAM and are fed into the VGA output.
To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
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Error: (vsim-3544) TEXTIO procedure READ(BIT_VECTOR) : Cannot get value from "9"
The code is from How to Read Image in VHDL
The author said it's synthesizable, but it's not like what he or she said.
When I am simulating the code, ModelSim gives me the following message:
"...
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How to Place Connections Between Microblaze and Custom RTL Modules in Vivado
I am very confused with this particular issue and would appreciate any help.
So I am using the Vivado block design to place a Microblaze with 128kB local memory modules, an AXI GPIO and UartLite ...
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VHDL my FFT design doesn't work at larger N-point
I built an FFT module for an 128-point FFT in VHDL. When I use the same principle for 8-point fft or 16-point fft (ofcourse then the file must be altered for less stages and different twiddle factors),...
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GENERATE statements in VHDL
I am investigating using GENERATE statements in VHDL to make duplicating the same logic tidier and more efficient. Take a basic example I found online below:
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Why isn't my counter reseting in VHDL?
For a project, I need to write a binary counter in VHDL that starts at zero, counts to nine, and then resets to start at 0 again.
I wrote the file below, which seems like it should function correctly.
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VHDL FSM not working as expected
I am not that experienced in VHDL. I am trying to implement a simple state machine that goes through 3 states - from idle, to DUT_run for 10 clock cycles, then remains at the done state. However the ...
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FSM to divider numbers in VHDL
I am trying to implement an FSM which divides two numbers which are assumed to be sane (no division over zero). In my specs, the machine is clocked, and at each clock edge, it checks the current state....
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Using MMCM/PLL source clock pin elsewhere in design breaks timing
TL;DR: New to Vivado Clocking Wizard, using the clock pin from the FPGA for anything other than the input to MMCM/PLL IP fails timing.
I'm working with Vivado ML 2022 in VHDL targeting an Artix-7 FPGA ...
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How to write clock process triggering hold and reset pulses in VHDL?
I am attempting to write VHDL for generating control signals to operate a switched integrator circuit. I'd like to create a 20us 50% duty cycle hold signal and a 5us reset signal when the hold signal ...
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Bad default binding, component port not on entity
I am trying to write a testbench for a basic component, but I am getting an error saying:
bad default binding for component instance (component port not on
entity)
I have tried recompiling multiple ...
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VHDL adder tree using recursion on Vivado
I am trying to implement an adder tree for 8 bit signed numbers using VHDL and recursion. The code works well if there is not overflow or underflow. The problem starts when I am trying to write logic ...
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How do you add unsigned numbers in VHDL within one clock cycle? [closed]
Here is the code snippet:
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FSM derivation for a digital Manchester encoder
I am looking at an FSM example in a digital design literature book where the idea is to create a simple FSM using a Moore machine for a Manchester encoder.
The FSM takes two inputs. ...
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VHDL Multiplication
I am trying to multiply x by 5/7 in this VHDL code. After some tweaking, as to understand how the process in VHDL works, as seen in the simulation diagram, I could not get the output y to go to "...
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Multiplication in VHDL by a fraction
I am trying to multiply a 8-bit number with 5/7 in VHDL language. I wrote 5/7 as a 20-bit binary and stored the multiplication in a 10-bit variable by only taking first 10-bit numbers of the result. ...
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Detecting stuck logic in testbench
I have a testbench that exercises an AXI component by reading and writing registers, waiting for state changes in the middle.
It is somewhat easy to define timeouts for the entire testbench
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How to minimize slack for mod in numerical package?
Here is the snippet of the code in VHDL.
I mean this IEEE.numeric_std.all
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VHDL: Testbench for ASK modulator
I've been trying to learn VHDL recently and came across the following tutorial for an ASK modulator: https://surf-vhdl.com/implement-digital-ask-modulator-vhdl/
I tried writing a testbench for this ...
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VHDL: Counter occasionally does not reset
I'm using ISE Project Navigator 14.7 with a Xilinx XC95144XL-5TQ100C CPLD in conjunction with a LM1881 video sync separator. I've also got a 14.3 MHz clock. I'm trying to generate VSYNC pulses in ...
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VHDL button debounce issue and display issue
I am back with probably a very simple fix which I cannot wrap my head around.
I've added a debounce to my button but it seems to not be working correctly.
Here are my issues:
When the button is ...
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How can I hold the value of counter in testbench of VHDL?
The counter only last for one clock cycle but I want the test_counter remain unchanged until next button_case.
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How to drive a counter with clock in testbench
I wan to drive the counter in testbench.
The counter (test_counter) doesn't increment as expected. Could you explain why?
What I expected is The ...
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Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?
If, for example, I implement a multiplexer in VHDL using logic gates, it may produce hazards, but if I use a higher level of abstraction describing the circuit in code, the simulation will not produce ...
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How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
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Why does RAM VHDL simulation output unexpectedly always shows zero?
I wrote VHDL to instantiate some RAM (256 bytes) using BRAM on a Digilent BASYS 3 FPGA development board using Vivado design tools. It takes 8 bits as the data input and outputs 8 bits on the output. ...
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What is the purpose of groups in VHDL?
The VHDL standard defines groups, for example:
group Variable_group is ( variable, variable );
What are these groups used for? ...
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Adder subtractor VHDL issue
I currently have this code, but it is not properly working; I'll put the example in the next image. IT has to be an adder subtractor 4 bits support, and it should use complement of 2.
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Multiple syntax error in VHDL file
I wrote a VHDL code to Build an array multiplier (no booth encoding, no tree structure). The output multiplier should be able to multiply two unsigned 8-bit numbers. The multiplier can either ...
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** Error: (vlog-13069) D:/CCSIT/DMSD/traffic_light_controller.v(2): near "traffic_light_controller": syntax error, unexpected IDENTIFIER [duplicate]
There is some problem with my code, but I can't find it.
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350
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VHDL signals with initialized values
This is my code:
And this is the testbench:
I am a VHDL beginner, and now I am trying to understand how 'Process' works.
I know that signals get the value only in the end of the process.
At t=0, the ...
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Why doesn't shared variable drive output port in VHDL when using concurrent assignment of shared variable to signal?
Here is the test case, a shared variable x_i drives and output port o_x.
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Syxtax error on component declaration
The following code is throwing Error: /home/project/path/dual_mux.vhd(11): near "component": syntax error:
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Simulation only code and Synthesis only code in QuestaSim
Pragma exist to tell the synthesis tool to ignore lines or blocks of code, using this:
-- synthesis translate_off
... code to ignore
-- synthesis translate on
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VHDL: Variables depending on other variables
If I'm in a process and I have a variable (A) changing and a different variable (B) changing based on the original variable (A), does other variable (B) change based on the new value or the initial ...
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VHDL: Booth's multiplication algorithm process block not working as intended?
I am trying to implement Booth's multiplication algorithm using this flowchart in VHDL. So far, I have written the code below:
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Performance metrics for a VHDL/Verilog RTL design
Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
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My test bench in VHDL is always showing U for all values
I am learning VHDL for a University course.
My code:
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Unexpected behavior in waveforms
Question:
I was trying to make a counter that counts from 0 to 255 with different steps. For example this counter based on a control input could start counting from 0 with a step of +5. So we will ...
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VHDL rising_edge on 1Hz GPS input
The FPGA project I am working on requires events within an FPGA to be triggered off a 1Hz PPS coming from a GPS module. I have sampled this pps and then tried implemented logic triggered by this ...
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GHDL bug with infinite process loop
When I tested the code below with GHDL it didn't assign the value. I assumed it was a design issue, but in the Vivado simulator the value changed.
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VHDL: Assigning type to specific value
In VHDL, if I take create a type like this
type example is (
ex_0,
ex_1,
ex_2,
ex_3
);
signal example_signal : example
Then ex_0 would synthesize ...
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