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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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41 views

System on Chip (SoC) ARM + FPGA (ZynQ-7xxx) - code design methodology

So far I've only been working with either ARM processor or FPGA/CPLD device separately. I.e. either I used a dedicated toolchain to generate binaries for a processor system from a C code, or I used a ...
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How do I get started with my Cyclone IV EP4CE FPGA development board? (Assignment file)

I have bought a Cyclone IV FPGA development board on AliExpress. I have installed Quartus II 14.01 and I have a sample VHDL file but I do not know how to do the pin assignment without an assignment ...
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53 views

Shared bus in FPGA (arbiter + perypherial bus) [VHDL]

I am trying to implement shared bus in my fpga design. I am thinking about something similar to the microcontroller bus. I see two possibilies: Second option is easier to implement but if bus is ...
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68 views

Do unintended latches only happen for signals in the process sensitivity list?

I read in one book that an unintended latch requires you to have a process section where there is a signal in the process sensitivity list but don't assign to in every path. But that doesn't make ...
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38 views

VHDL Value of integer signal increase twice instead of once

I just created this project to get a clearer understanding of why the values of check1 and check2 to increase once we enter the state assigned but for some reason, it increases again the moment we go ...
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108 views

Less than vs. less than or equal to

I wrote this code for a simple PWM generator, that has a very weird bug related to "<" vs "<=". It works perfectly when I use "<" but not when I use "<=". As a test, I set freq_new to ...
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73 views

How to generate signal who have value less then one clk in vhdl? [closed]

How to generate signal who have value less then one clk in vhdl? Signal req is generate base on input signal dat1 and dat2. If they are equals, signal req have value of 1 less then one clk. On ...
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42 views

How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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83 views

Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?

I'm learning VHDL, and there are a lot of exercises where they give you an entity and you have to write the architecture, where a lot of the inputs are separate: ...
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55 views

VHDL error in simulation

I'm facing a error when I tried to simulate a circuit. It's a parallel-to-serial converter. With the first word, the circuit works well, i.e, the conversions occur. But with the second word the ...
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42 views

VHDL “can't match slice type array type”

I'm new to VHDL and I'm trying to use code off a teacher's slide that doesn't seem to work as is, and I can't tell what's wrong: ...
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26 views

Quartus Prime Syntax Check Only

I have a variable in my code where I can change "modes". Some (timer and counter) values are reduced and I can run in Modelsim and enjoy the fast error checking. Currently, I need Signal Tap for real ...
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52 views

What is the diference between concurrent 2 “when-then”, sequential 2 “if-then” and “if-elsif” statements in VHDL?

I want to create an 8 bit counter with reset button on a FPGA board. I have two signals: btn_up which is debounced and btn_center which isn't. R is an output signal which represents 8 bit counter. I ...
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60 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
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79 views

Lowpass Audio Filter on FPGA

I am trying to establish a low-pass filter to Audio Demo code of Nexys A7 board. I have implemented a filter however I hear just a noise. If you share your time, I will be happy. I have added the ...
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64 views

vhdl output pulse

I have another question regarding some VHDL, I am trying to create a pulse of 5ms output for (in my code a_full) however I am struggling to find any information on how to generate this, basically I ...
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45 views

VHDL TB - cannot generate my clock

I am hoping some of you may help, I am currently answering an assignment question for uni and as such I have to write a code for an egg counter/ sorting using VHDL. there are 4 sizes of eggs that ...
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69 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
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223 views

How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
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116 views

Xilinx FPGA “X” state in simulation and didn't find the bug

I wrote an ASRAM in VHDL and simulate it. I get many "X" if I try to read. I know that this problem is caused by too many drivers on one net but I didn't find the problem nor solved it. Appreciate ...
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87 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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90 views

VHDL using 'if' to compare a 'variable'

Using Xilinx, I need to compare a 'variable' called 'row', defined as: variable row : std_logic_vector(2 * n - 1 downto 0); This line was given to me, now I ...
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80 views

Attach output to a state in Finite State Machine in VHDL

In my digital electronics class we are currently dealing with Finite-State-Machines and VHDL. I have written a VHDL-code for finite state machine and I've run into trouble. I want to attach the ...
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86 views

How do you implement this when else statement in VHDL?

I have the following example from an answer on a previous post on Stackexchange Electrical Engineering: ...
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84 views

VHDL: I have a lot of inferring latches due to my case statement

I have coded a project for an FPGA and in one of my files which is a mux, I have a lot of inferring latches, which I think is due to my case statement. The code looks like this: ...
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47 views

VHDL: Can't give a std_logic type a value of 0 or 1 (on or off)

I have the following code from one of the files in a project: ...
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68 views

Why does VHDL not allow to alias slice of an array in this way?

This code does not compile: ...
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50 views

Problems with Memory Initialization in Quartus

I have the following code snippet in my VHDL code to initialize a ROM block: ...
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2answers
60 views

How I can resolve the problem of conversion (to_integer(unsigned(variable))

I want to solve a problem in VHDL with Quartus II. I made a model of VGA protocol 640/480. When I made the part of displaying I made one two signal in integer. Error (10621): VHDL Use Clause ...
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69 views

Shifting a result in 16-bit register

I have a result in a 16-bit register which I have created. And after getting my result in this register, I am trying to shift it by two bits to the left. I am using the function for SLL to do the ...
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35 views

VHDL: Port mapping to physical pins when you have “subcomponents” inside a component

Let's say you have a project in VHDL that looks something like this: Generally it's pretty easy to map the ports together between Component 1 and Component 2. However, what if Component 1 is code ...
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42 views

Two port mapping files in one VHDL project

I am currently working on a project for a Cyclone II FPGA board where I am coding a guess game in VHDL. The overall design looks like this: I have made a port mapping file for the overall design ...
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62 views

VHDL - Inferred Latch With Reset - FSM

I have an issue with this process where if I include a reset statement, I get an inferred latch. However, if I do not include the reset statement, I do not get an inferred latch on duty_cycle_triangle....
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64 views

VHDL: Writing a character on a seven-segment display with VHDL

Normally when making a decoder from binary to hexadecimal, the only characters available are those in the hexadecimal system, which means A to F. However, if I for instance want to show an H on a ...
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54 views

Understanding this IBD to make a Guess Game in VHDL

I am given an assignment of making a guessing game for a Cyclone II FPGA in VHDL. I have the following IBD diagram about the game: The purpose of the game is to guess a secret number that the ...
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28 views

Ripple carry adder using Half adder and 2 Full adder

I'm creating a ripple carry adder using the following Diagram. I have the following code writte, but when I run the simulation it's all over the place and I'm banging my head as to why this is ...
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103 views

found '0' definitions of operator “*”

I have this error when trying to compile my VHDL code. The purpose of the code is to multiply a 2 bit constant K by some 4-bit number in memory. There are some similar posts here with the same error, ...
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67 views

VHDL - signed vs unsigned adder

I have made a four bit adder with carry-in & -out that contains an unsigned and signed architecture: ...
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53 views

VHDL - need to understand output of simple math

Im new to VHDL, so my apologies if this question doesnt fit this forum. Here goes: I have the following variables: ...
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83 views

Write received character from PS/2 keyboard to LCD1602

I am trying to read a pressed key from a PS/2 keyboard and display it on a LCD1602 display. I wrote one entity and architecture which detects a pressed key. If it received the 11 bits (1 start bit, 8 ...
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224 views

VHDL: Convert std_logic to std_logic_vector

I'm trying to make a 4 bit adder with carry in & out, but I am having trouble converting Cin (Carry-in) to the type std_logic_vector when summing Sum and Cin together below in the architecture. ...
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58 views

Making a simple 4 bit adder into a 4 bit adder with carry in & out

I have coded a simple signed 4 bit adder. It doesn't have any carry in or carry out so it easily overflows. Below you can see my code. ...
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70 views

FSM in Logisim Evolution Using VHDL

I have been trying to make a state machine work in Logisim Evolution using VHLD. All the environment in Logisim has been set up and it's working for simple VHDL examples, so I can rule that out. The ...
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118 views

Is there a compact way to connect these two ports?

I've been learning VHDL for five days and I've got stuck. Currently I'm trying to implement a combinatorial cross-point switch between Port A (input 8-bit) and Port B (output 8-bit), depending on what'...
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64 views

Trying to differentiate between two simple clock divider circuits - VHDL

I'm very new to VHDL and I'm trying to design a simple clock divider process, but I'm running into a strange disparity between two forms of a process that I can't tell apart logically. I'd really ...
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69 views

What's the practical difference of a wait process and a sense process?

All the VHDL-tutorials I've read mentions that one can use a sense process and a wait process, but I have been unable to grasp the difference. That is: ...
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66 views

What is need of transmission modes in Serial Peripheral Interface

I am going through SPI transmission for implementing in FPGA, While researching, In few articles such as https://en.wikipedia.org/wiki/Serial_Peripheral_Interface and this https://web.archive.org/...
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54 views

VHDL: Use a type, dependent on entity generics, for other entity ports/generics

I'm trying to design a memory emulation entity for simulation. To make it as versatile as possible, it uses generics to define data and address widths. Additionally, one should be able to supply an ...
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47 views

Using an internal signal in a testbench

I am using HDL Designer and have a pretty large design I need to test. I have created a test bench by using HDL Designer itself and did not do it standalone. Like the title states, I want to know how ...
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116 views

VHDL: difference between using “+” or writing our own adder

I would like to know what would be the difference between between using "+" or writing an adder for adding two numbers: ...