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Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Vivado: How to setup clocks according to constraint file?

I am beginning to experiment with an Arty A7 development board and I am fighting Vivado. According to the constraint files given for the board, I have the following ...
0 votes
0 answers
66 views

Implementation of recent STM32MP1 processors on an FPGA [closed]

As part of a hardware team at a fairly new startup, we are exploring the use of Field-Programmable Gate Arrays (FPGAs) and the availability of IP blocks for STM32MP1 processors from STMicroelectronics ...
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1 answer
39 views

Alignment characters in the JESD204B standard

I have a question regarding the alignment characters in the JESD204B data converter interface protocol. To anyone who is familiar with this protocol. There are certain alignment that are used during ...
1 vote
2 answers
2k views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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2 answers
98 views

Why does the white space get included while reading a string from a file in VHDL?

I am trying to read data from a text file in VHDL which includes two vectors and single character. While reading, white spaces are not detected for the numbers but are detected for the character. Why ...
0 votes
2 answers
188 views

Problem with conditional signal assignment

I'm really desperate right now. I have written a VHDL code that gets an input of type std_logic_vector(0 downto 0) [in__con1_dio4_rs485_rs] which it should collect in 8-bit blocks. For this I use an 8 ...
0 votes
1 answer
184 views

VHDL Multiplication

I am trying to multiply x by 5/7 in this VHDL code. After some tweaking, as to understand how the process in VHDL works, as seen in the simulation diagram, I could not get the output y to go to "...
-2 votes
0 answers
33 views

How to implement a signal with an early falling edge dependent on another signal? [closed]

I have two signals, an enabled signal and a delayed enable signal. The enabled signal is an input, and the delayed enable signal goes high a few microseconds after the enable signal input goes high. I ...
-3 votes
1 answer
104 views

Whats the error?

I'm trying to make a counter but Vivado display an error, and I cannot see what's the problem. As far as I know the design is correct. Someone can tell if I'm missing something, please.
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1 answer
99 views

How to correctly write and read to/from SRAM on FPGA with VHDL?

I want to write 512KByte data on SRAM(IS61/64WV512).I'm using spartan6 lx9 FPGA. In the program routine, the initial step involves writing all the data. Subsequently, upon completion of the writing ...
-1 votes
0 answers
48 views

Why does "i_spi_clock_divider - 1" not update if i_spi_clock_divider has a given value?

I'm currently facing a puzzling issue with my SystemVerilog SPI controller design and would greatly appreciate some guidance and insights from the community. Problem Description: I have implemented a ...
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1 answer
65 views

VHDL: Keep multiple files open until end of simulation [closed]

In my testbench I write to several outputs files as the test proceeds. These files are later processed by a Python script to generate meaningful data. The testbench writes 100,000s of lines of data in ...
1 vote
3 answers
65 views

Output Variable stays unintialised in my VHDL testbench

I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop. Following is the VHDL code that I have written: ...
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1 answer
40 views

VHDL: textio variants of the write function for real data type

Here are the two variants of the write function that can be used to write the "real" data type into file or stdout. ...
21 votes
4 answers
36k views

VHDL IDE for a GNU/linux environment

I have to study VHDL from 0 and i'd like to have an option that runs under a linux kernel instead of NT/Windows: any tips? I can also really appreciate some good links to good VHDL resources for a ...
0 votes
1 answer
483 views

VHDL test bench for input port assignment

I am trying to depict port 3 of microcontroller which acts a I/O and as special functions like timers interrupts in VHDL. The code is as follows: ...
1 vote
1 answer
867 views

How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
0 votes
1 answer
60 views

I'm trying to build a FSM in VHDL but the Mealy state machine won't change states

I'm trying to build a Mealy Finite State Machine in VHDL. each time a button 'btn' is pressed, the FSM should go to the next state. There are 4 states, s0, s1, s2 & s3. s0 is the state at which ...
1 vote
2 answers
483 views

Undefined(U) values in Vivado sim

I am designing a nanoprocessor and below is my instruction decoder code. As you can see I have used case statements for specific operations based on the input signal. Because of this, as you can see, ...
1 vote
2 answers
2k views

AXI master bus functional model in VHDL

I am a Verilog user trying to make sense of VHDL code of AXI4 master bus functional model (BFM). AXI bus master VHDL code I have a few questions from the above code: What would the block diagram of ...
0 votes
1 answer
295 views

What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a ...
2 votes
1 answer
68 views

D latch module in VHDL using NAND structure [closed]

What is the difference between a positive-level D latch and a negative-level D latch? How to create positive and negative D latch in VHDL using NAND structure? Can you share some example codes for ...
0 votes
1 answer
58 views

Difficulty understanding the need for multiple-register pipelines for signals [closed]

When I studied the GPIO demo code for Basys3 to create my own VGA controller, I noticed that multiple registers are used for a single signal, like h_cntr, H_sync, V_sync, VGA_R, VGA_G, VGA_B, etc. I ...
1 vote
1 answer
59 views

A NAND gate with propagation delay in VHDL

I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL. \$t_{PLH}\$ = Propagation delay low to high \$t_{PHL}\$ = Propagation delay high to low This is first code. ...
107 votes
11 answers
116k views

VHDL vs. Verilog [closed]

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?
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1 answer
46 views

Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL

I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
0 votes
1 answer
40 views

How do I implement a simple axistream by my self bus in VHDL?

I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
0 votes
2 answers
868 views

Issue with Booth multiplier VHDL code

I'm trying to build a 4-bit Booth multiplier using VHDL. I don't know why, but the process block is executed just once. The state does change from idle to busy then it doesn't work. ...
2 votes
1 answer
1k views

VHDL: Detecting key pressed on PS/2 keyboard in FPGA

Is it possible to detect a keypress on a PS/2 keyboard connected to an FPGA, using VHDL, with only PS/2 clock signal? ...
1 vote
0 answers
106 views

Generating an 80 MHz clock from a 100 MHz clock with VHDL in Spartan-7

I am new to VHDL and am targeting a Spartan-7 FPGA, using VHDL. For technical reasons I have to develop outside the Vivado or other environments. It seems like there are several posts that have ...
1 vote
1 answer
39 views

Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&'

It may be a simple fix, but I do not understand the error: Error: near "end": (vcom-1576) expecting == or '+' or '-' or '&' ...
2 votes
2 answers
902 views

VHDL: How to avoid writing to and reading from 2D array at the same time?

For something I work on, I must use an 2D array but I find it dangerous to write to and read from a certain memory location in the array at the same time. How can I control this situation? When both ...
0 votes
2 answers
729 views

Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?

Assume I have the following constraints file which specifies only one single input: ...
0 votes
1 answer
366 views

Efinity FPGA suite error EFX-0101

When trying to synthesize an FPGA design in the Efinity FPGA Suite, I keep getting the following error that I can't figure out how to resolve: ...
0 votes
2 answers
240 views

VHDL button debounce issue and display issue

I am back with probably a very simple fix which I cannot wrap my head around. I've added a debounce to my button but it seems to not be working correctly. Here are my issues: When the button is ...
1 vote
1 answer
814 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
1 vote
2 answers
5k views

What is backdoor memory access?

There is a term in HDL simulation/verification called "backdoor memory access". I've heard this a lot of times though I'm not sure how is this implemented. Also, there are a few references for this ...
0 votes
2 answers
116 views

Assert 'must be power of 2' in VHDL?

I'd like: ...
0 votes
1 answer
473 views

'Nonresolved signal has multiple sources' error

I keep on getting an error of multiple source. Here is my code for the testbench I am making. ...
0 votes
1 answer
493 views

How to implement derivative, and create a delay of dozens of clock cycles?

I have uart entity which have the following signals (I write only the relevant - for tx) ...
1 vote
2 answers
8k views

Divide by integer in VHDL

I need to divide an integer by an integer in one clock cycle. How should I do this? I have a function for it I found on the internet but it always returns one. ...
1 vote
1 answer
1k views

How to interface UART with BRAM in xilinx virtex 5

I am trying to design a simple loop of communication system between pc and FPGA virtex 5, for this purpose I interfaced a BRAM with uart module, I am using VHDL as the hardware description language, ...
6 votes
2 answers
3k views

How to simulate VHDL program without FPGA

I want to learn VHDL, and I wonder if I can find any tool that allow me simulate a VHDL program without having an FPGA. I do some search in internet, and I found this list of HDL simulators, but I ...
-1 votes
1 answer
232 views

Xilinx Line <read_line> has not enough elements for target <input_b> for the file with more than one line

I have a file each line of which includes two 9 bits inputs. Here is an example of this file: input_vectors.txt: ...
2 votes
1 answer
3k views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
0 votes
2 answers
426 views

(7,4) cyclic code encoder in VHDL

I am trying to write code for a cyclic code encoder in VHDL, but I am not able to visualize how to approach the problem. Right now all I have is an entity and a few diagrams showing my approach as to ...
0 votes
1 answer
163 views

Encryption of Verilog/VHDL module

I don't have encryption licenses for Vivado or Quartus to encrypt my Verilog/VHDL modules and so I cannot give my RTL to any user. I don't want to give out synthesized netlists but only encrypted RTL. ...
-1 votes
1 answer
259 views

VHDL: Select module architecture using parametric name

I am aware that I can instantiate one architecture or another with Module_inst : entity work.Module(rtl_1) where rtl_1 is the ...
0 votes
1 answer
42 views

Packaging synthesized design as netlist for use in future designs

I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
0 votes
1 answer
92 views

Adding VHDL DDR Memory Interface IP to block design in XIlinx Vivado

I am using a Nexys A750T FPGA dev board and I would like to use the onboard DDR2 SDRAM. When I attempt to generate the MIG 7 series IP via the IP catalog, the IP wizard forces the design to be in VHDL ...

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