Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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12
votes
7answers
9k views

Cheap FPGA dev board [closed]

I want to begin with FPGA, but I've never worked with once before. I want a cheap kit, but I don't know where to start. I can find cheap boards, but then I can't get no information about the ...
9
votes
3answers
9k views

How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
32
votes
7answers
275k views

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

I built a mod-16 counter, and the output result is a INTEGER (all the examples I saw used INTEGER). I built a hex-to-7-segment-display decoder, and its input is a STD_LOGIC_VECTOR (wrote it that way ...
26
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4answers
34k views

VHDL: Component vs Entity

I am wondering what is the difference between component an entity. I would like to know in which cases is better to use components instead of entities. Thank you so much.
9
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2answers
9k views

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable ...
4
votes
3answers
5k views

Design practice crossing clock domains and async signals

I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a ...
0
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1answer
1k views

vhdl port declaration with different sizes

I'm writing a vhdl model and I'm stuck with a problem about port declaration. Let's say that I have an entity entityA that instantiates N ...
9
votes
2answers
1k views

VHDL: receive module randomly fails when counting bits

Background This is a personal project; it regards connecting an FPGA to a N64, the byte values that the FPGA receives are then sent through UART to my computer. It actually functions pretty well! At ...
99
votes
11answers
101k views

VHDL vs. Verilog [closed]

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?
30
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10answers
61k views

Free IDE for VHDL and Verilog [closed]

I am interested in learning VHDL and Verilog. I was wondering if there is any free IDE for those?
27
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17answers
69k views

Most affordable FPGA dev kit for learning VHDL and FPGA theory?

I'm looking for something that I can play around with but not spend too much on. I'm not eligible for an academic discount so take that into account when making suggestions.
43
votes
2answers
13k views

How is ASIC design different from FPGA HDL synthesis?

I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA. I've ...
24
votes
11answers
8k views

VHDL interview question - detecting if a number can be divided by 5 without remainder

I saw a nice interview question for VHDL - build a system that receives a number and detects if it can be divided by 5 without remainder. I tried to solve that with a state machine (I suppose they ...
24
votes
7answers
6k views

How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
19
votes
4answers
34k views

VHDL IDE for a GNU/linux environment

I have to study VHDL from 0 and i'd like to have an option that runs under a linux kernel instead of NT/Windows: any tips? I can also really appreciate some good links to good VHDL resources for a ...
13
votes
5answers
91k views

How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA

I have a Xilinx FPGA board, with a 50MHz crystal. I need to divide that down to 2Hz in VHDL. How do I do this?
12
votes
4answers
35k views

When to use STD_LOGIC over BIT in VHDL

Whats the difference between using: ENTITY MyDemo is PORT(X: IN STD_LOGIC; F: OUT STD_LOGIC ); END MyDemo; and ...
11
votes
2answers
30k views

Difference between If-else and Case statement in VHDL

I want to understand how different constructs in VHDL code are synthesized in RTL. Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in ...
4
votes
2answers
37k views

n bit shift register (Serial Out) in VHDL

I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. I've put a for loop to ...
4
votes
2answers
1k views

cross clock domain databus

I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals. One of the "rules" is to never synchronize multi-bit signal bit-by-bit, ...
3
votes
1answer
8k views

Serial Adder vhdl design

I've a design problem in VHDL with a serial adder. The block diagram is taken from a book. Since i'm not skilled enough in design with clock (except some silly flip flop i've found on the web, and ...
1
vote
1answer
4k views

How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
0
votes
2answers
8k views

real to std_logic_vector in VHDL

I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL. I want the code below to be synthesized such that it ...
4
votes
2answers
2k views

VHDL - converting types and integer substraction

I am preparing a program in VHDL and I got stuck in type-conversion. I tryed google-search and also here at stack exchange, but I am quite confused since one answer contradicts other and neither one I ...
2
votes
1answer
4k views

How to break multi digit number into separate digits in VHDL?

I found the method for c language.But I do not know how to perform this in VHDL. Let a fixed point number (12 downto -19) like 3456.478396 I need break this number entirely into separate numbers 3456....
2
votes
3answers
11k views

Using VHDL code to design a JK Flip Flop

I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it? Intended design circuit: VHDL code: ...
1
vote
1answer
6k views

Storing values on variable fpga vhdl

I want to develop an application that is able to get and store two input values and then output the two stored values. E.g.: The input string is "John". The application should get "J" from ...
1
vote
1answer
2k views

generating 40 mhz clock from 50 MHz

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think it'...
-3
votes
1answer
2k views

Reading from ROM and Generate a VGA Signal in FPGA [closed]

I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would ...
12
votes
6answers
5k views

book recommendations on FPGA [closed]

what book titles would you recommend to get started with FPGAs and VHDL? edit I noticed that a few of the recommended books date back from 1996. I can imagine that the devices referred to will be ...
24
votes
4answers
5k views

VHDL that can damage FPGA

I read somewhere that bad VHDL code can lead to FPGA damage. Is it even possible to damage a FPGA with VHDL code? What kind of conditions would cause this and what are the worst case scenarios?
10
votes
2answers
7k views

Can you interface a Modelsim testbench with an external stimuli

I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I ...
25
votes
4answers
27k views

std_logic or std_ulogic?

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The ...
13
votes
4answers
25k views

How to bring out internal signals of a lower module to a top module in VHDL?

How can I bring out the internal signals of my VHDL source code to my testbench so that I can view them as waveforms? I use Active HDL. I would like to know if there is any tool independent method of ...
13
votes
4answers
5k views

SystemC vs other HDLs [closed]

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and ...
11
votes
5answers
7k views

VHDL: Using '*' operator when implementing multipliers in design

Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units. It is possible to create DSP entity/module using a GUI after selecting the ...
5
votes
3answers
4k views

Meaning of strong and weak drive in VHDL?

What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?
6
votes
1answer
2k views

Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)

Hello this will be an experts questions :) You should be familiar with the following topics Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) ...
11
votes
4answers
3k views

When is it neater to use VECTOR representations vs INTEGERs?

In the comment thread on an answer to this question: Wrong outputs in VHDL entity it was stated: "With integers you don't have control or access to the internal logic representation in the FPGA, ...
6
votes
1answer
10k views

How to create an n-bit multiplexer?

I'm needing to create a 4 bit, 16 input multiplexer. I know I could describe this as a long list of S => when "0000" etc.. but I think that's not very clean, and ...
10
votes
4answers
19k views

Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
6
votes
7answers
8k views

How to configure my favorite editor in ModelSim?

I want to set up my favorite editor in ModelSim. The default behavior is that ModelSim uses its own internal editor, which I don't like. I've Googled and I've searched the ModelSim User Manual. I ...
5
votes
4answers
6k views

How is this simple counter implemented on an FPGA without a clock?

As part of an assignment, I must create these blocks that tie in to a larger top level module. (there are more blocks not pictured). I have everything working fine, except this UP/DOWN counter ...
3
votes
2answers
6k views

Syncing Signals with Global Clocks in FPGAs/CPLDs and Edge Detection

I am a newbie in digital logic design and I'm trying to get my head around syncing external signals to the global clock in an FPGA. For example, the SCK signal/clock fed to an FPGA by the SPI Master. ...
2
votes
1answer
6k views

VESA CVT Standard - How to calculate video timings?

Most video resolutions like VGA (640x480), UXGA (1600x1200) or HD720 (1280x720) are defined by VESAs Coordinated Video Timing (CVT) standard. (It can be freely downloaded from VESA.org). The download ...
9
votes
3answers
2k views

Pressing same key rows at the same time

I am designing a keypad in VHDL. Everything works fine when only a single key is pressed. I'm scanning each column for a key press in a state machine and when no key is pressed, which is the condition ...
5
votes
2answers
2k views

Unexpected results when multiplying in VHDL

I'm trying to make a simple BCD --> binary conversion operation work in an ALU I'm coding. All the other operations work perfectly fine, just this last operation doesn't work for some reason. I've ...
4
votes
2answers
2k views

How is debugging build implemented in VHDL?

I come from C background and am being introduced to VHDL. I read about the syntax and the concurrency/consecutiveness of actions. Now I am getting to wonder how are development-only features ...
4
votes
1answer
2k views

Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it ...
4
votes
1answer
1k views

VHDL “compile time” math?

I have a generic VHDL entity and I have this code: ...