Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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Undefined signal in simulation

I am trying to verify a design written in VHDL using SystemVerilog's assertions. however I got a problem when I have a non defined signal'X' Just for example here is a code of a Comparator: ...
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239 views

Creating big MUXes and shift registers on FPGA

I'm working on a guitar tuner project on FPGA. For this I have to pass the sound signal (16bit/1024Hz sampling) from the ADC to a FFT block but I want the FFT block to be clocked with much higher ...
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133 views

No output with for loop

I have been working on this issue for a couple days and still cannot figure it out. I wonder if someone can help me with this. You can just focus on the video process at the bottom of the code below. ...
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1answer
560 views

What is the correct way to implement left shift operations using multipliers?

I require a left shift operation to be done in VHDL. Input is 24 bit and shift amount is by 16 bits maximum. Left shift operations by n are synonymous with multiplication with 2^n which is to say ...
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0answers
170 views

Ling adder vs classic CLA adder what's the difference?

I'm practicing in designing vhdl unit with some "complex" computer arithmetic algorithm. I've just implemented the following CLA unit below. I'm reading through this book, page section 6.3 page 97, I ...
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339 views

Exclude certain module from optimization in Xilinx ISE 14.4

I'm synthesizing a quite large design in Xilinx ISE 14.4 and would like to exclude certain modules from optimization. Is that possible? The design I'm synthesizing is the LEON3 microprocessor. I have ...
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183 views

Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
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0answers
278 views

Troubleshooting audio output on Nexys 2 (FPGA)

I've recently purchased the PMOD AMP1 module from digilent for use with my Nexys 2. When I program the demo project and plug headphones or speakers on the headphone output I can hear a barely audible,...
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2answers
4k views

VHDL JK Flip-Flop with logic gates

I am trying to make a JK flip-flop in ActiveHDL environment. I want to make it with logic gates. It should look like this: This is my code: ...
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0answers
42 views

VHDL Event vs. Transaction

I can't figure out this issue. In my test bench I am checking timing to make sure I have adequate separation of data/addr setup to the enable pulse edges in terms of clock delays, not logic delays. ...
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0answers
29 views

Building a better staged 1's complement adder tree?

I'm trying to calculate the checksum of IPv4 and UDP messages coming out of my Ethernet controller module. The checksum calculation for both IPv4 and UDP is defined as 1's complement addition, which ...
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0answers
33 views

VHDL Integer Range Output Bus Width

I'm currently working on writing a simple counter in VHDL, trying to genericize it as much as possible. Ideally I end up with a counter that can pause, count up/down, and take just two integer (min, ...
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1answer
100 views

Toggling the Output in VHDL

so I've been trying to solve some questions in the book Free Range VHDL. The question I have problems with is: Provide a VHDL behavioral model of the D flip-flop. The S and R inputs are an active low ...
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41 views

Vivado is not properly gating my registers?

I have a register which holds 12 bits written in VHDL within Vivado which is not being gated properly. The code is very simple, and is as follows: ...
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1answer
83 views

How to generate fast clock signal with MAX10 and PLL?

I'm using 10M50 FPGA to read data from a camera via MIPI-CSI2, but the clock I have on the board can't operate fast enough. So right now i'm trying to use the PLL to generate faster clock signal. I'm ...
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0answers
65 views

How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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2answers
65 views

Sequential logic in VHDL

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements? I am building an 8 bit word splitter that will then pass a 4 bit nibble to ...
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1answer
86 views

vhdl output pulse

I have another question regarding some VHDL, I am trying to create a pulse of 5ms output for (in my code a_full) however I am struggling to find any information on how to generate this, basically I ...
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1answer
145 views

Xilinx FPGA “X” state in simulation and didn't find the bug

I wrote an ASRAM in VHDL and simulate it. I get many "X" if I try to read. I know that this problem is caused by too many drivers on one net but I didn't find the problem nor solved it. Appreciate ...
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0answers
95 views

Write received character from PS/2 keyboard to LCD1602

I am trying to read a pressed key from a PS/2 keyboard and display it on a LCD1602 display. I wrote one entity and architecture which detects a pressed key. If it received the 11 bits (1 start bit, 8 ...
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0answers
104 views

Using an internal signal in a testbench

I am using HDL Designer and have a pretty large design I need to test. I have created a test bench by using HDL Designer itself and did not do it standalone. Like the title states, I want to know how ...
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0answers
100 views

Massive power usage for a simple VHDL design

I'm trying to implement Gaussian elimination to calculate Matrix rank, The following code uses lots of power like 60 watts for 2x2 matrix which looks weird ...
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1answer
153 views

VHDL : Not understanding Hierarchical or External Naming or how to use them

Note: I using quartus ii v13 with vhdl 2008 I am trying to access the current state of my state machine from inside my test bench file. From my understanding I should be able to do this with External ...
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1answer
59 views

VHDL how to code a Mealy NSTT

Noob here, I remember back in school learning how to code a Mealy next state transition table and deriving this equation using k-maps and then coding the actually equations for all the outputs rather ...
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1answer
137 views

How does one pass signals through instances in VHDL using hierarchical names possibly

I have some VHDL code written for synthesis with three instances in the top level and the three subs so I can pass inputs and outputs. Call them top, sub1, sub2, sub3. I now want to add a signal and ...
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0answers
250 views

VHDL - rand*real(2**32-1) : can this cause an overflow issue?

I'm studying VHDL implementations of multipliers: I found this one and i'm trying to modify it. Default word size is 8 bit and the design is working (both simulation and synthesis) for any size up to ...
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1answer
151 views

Signed Integer Division Optimization

I've implemented a division algorithm on an FPGA using the long division algorithm. My implementation does not use pipelining, but works iteratively and requires very few logic elements since the ...
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1answer
87 views

Xilinx Line <read_line> has not enough elements for target <input_b> for the file with more than one line

I have a file each line of which includes two 9 bits inputs. Here is an example of this file: input_vectors.txt: ...
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1answer
621 views

VHDL nested generate statements: how to refer to label?

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine: ...
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0answers
277 views

VHDL: Setting upper bits of variable to zero during assignment with shorter variable

When one has something like variable a : unsigned (3 downto 0); variable b : unsigned (1 downto 0); and one wants to assign the lower ...
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158 views

ROM initialization in VHDL for waveform generator

I have to create a waveform generator and i used matlab to generate the sine wave. Now my TA told me to store the points from the wave in a ".mem" file then initialize the ROM by i guess importing ...
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1answer
67 views

Code parts encapsulation method

I have a prototype of a simple monostable multivibrator components like this: ...
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1answer
1k views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
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0answers
380 views

VHDL File IO, write to specific line number

Is there a VHDL function that can write data to a specific line of a text file, without modifying the other lines? This is for simulation needs, of course.
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188 views

vhdl oneline pulse simulation

I wolud like to use simple oneline code snippet for generating single clock cycle positive pulse pulse <= '1', '0' after CLK_PERIOD; However, it is not ...
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2answers
426 views

How to avoid writing to and reading from 2D array at the same time vhdl

Hi for something I work on, I must use an 2D array but I find it dangerious to write to and read from a certain memory location in the array at the same time. How can I control this situation? When ...
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0answers
64 views

Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should ...
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0answers
65 views

user data generator and user data partner receiver for gtp transceiver

I want to use gtp transceiver of Artix7 xc7a200t to send and receive Ethernet data, so the transceiver is in full duplex and framed. The reference clock of the transceiver is 200 MHtz. I want to send ...
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1answer
83 views

In a constraints.ucf, how do I tell it to that an unconnected pin is ok?

I'm new FPGAs, and working through the "IntroToSpartanFPGABook" PDF. I'm looking at the "constraints.ucf" file, and (because I'm lazy), it occurred to me that I could create one "constraints.ucf" ...
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0answers
1k views

Clock Frequency for 4 digit 7 segment display in VHDL

I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider ...
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0answers
868 views

Generating Bitstream takes very long in Vivado

This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it ...
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1answer
612 views

Range of unsigned fixed point division in VHDL

I was thinking about the range a result signal should have to acommodate an unsigned fixed point division. Suppose we have: SIGNAL a : UFIXED (3 DOWNTO -3); SIGNAL b : UFIXED (4 DOWNTO -2); am I ...
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1answer
59 views

Problems with dividing a clock with 2 command bits

I am trying to make a clock divider commanded by 2 bits :DTPS. For instance if DTPS is: "00" we get the clock as output(2^0) "01" we divide the clock by 2 (2^1) "10" we divide the clock by 4 (2^2) "...
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0answers
672 views

VHDL : Uninitialized inout port has no driver

I'm new to VHDL and i'm trying to design a really basic microprocessor but i'm facing this error during the simulation : ...
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0answers
530 views

How can a transpose buffer be realized in an FPGA

As far as I understand a transpose buffer is where we write data of a nxn matrix as rows and then can read it out as columns of the same matrix. There does not seem to be an IP block to create such an ...
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0answers
430 views

When is VHDL code considdered compile time

EDIT: I am working with a lookup table which is generated in compile time. Is this compile time code: because sinus_table is a constant or because any ...
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0answers
352 views

VHDL: how do you perform asynchronous data transfer between entities?

How do you implement the following sort of functionality in VHDL that is synthesizable? ...
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0answers
1k views

VHDL Multidimensional arrays with different internal size

I'm wondering if it is possible or not to create bi-dimensional arrays having different inner sizes. For example I can create ...
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0answers
1k views

Serializing and Deserializing data

I am trying to develop a data link on FPGA. The transmitter combines 8 channel input to single output. The Rx has to de multiplex the single channel to 8 bit parallel output. presently the system is ...
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1answer
555 views

Index into std_logic_vector using signal

I need to modify a certain portion of a register, but the upper and lower bound of the modified part depend on the input. Can the following code: (1) be synthesised? (2) if so, what circuit do the ...

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