Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

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1answer
97 views

purpose of driver

Why do we need to use driver ? ...
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2answers
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representation of keywords

Here are some representations of simple VHDL statements. Synthesizing Y <= A and B ; results in Synthesizing ...
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4answers
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How to avoid latches during synthesis

I want to design a block of combinational logic using VHDL, but occasionally the synthesized result contains an unintentional latch. What coding guidelines do I need to follow in order to avoid the ...
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3answers
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process and signal assignment

I have the above code segment. I am a bit confused, so can one help me ? ...
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9answers
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Newbie projects on an FPGA?

I'm two weeks away from completing my first college digital logic design course, and apparently there isn't going to be a final project--just a tedious final exam. So as any curious student would do,...
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4answers
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std_logic or std_ulogic?

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The ...
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6answers
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How to configure my favorite editor in ModelSim?

I want to set up my favorite editor in ModelSim. The default behavior is that ModelSim uses its own internal editor, which I don't like. I've Googled and I've searched the ModelSim User Manual. I ...
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11answers
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VHDL vs. Verilog [closed]

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?
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4answers
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VHDL: Component vs Entity

I am wondering what is the difference between component an entity. I would like to know in which cases is better to use components instead of entities. Thank you so much.
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1answer
152 views

VHDL: Instantation question

I have to do a instantation of several components I suppose the code for this instantation would be something like this: ...
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3answers
2k views

SFF SDR: How to implement a simply program in the FPGA

Although this a very specific question, I think someone of this site could give interesting information. I am using a SFF SDR of Lyrtech I am trying to generate a .bit file using a .vhd file and a ....
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2answers
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verilog to schematic block

Is there any tool in linux that converts vhdl/verilog code to an equivalent schematic block. I know the available tools * Synplicity * Synopsys Design Compiler * Altera Quartus II * ...
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1answer
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Is it possible to have STD_LOGIC_VECTOR range constraint applied bottom-up?

I know that entities can use unconstrained array types (such as STD_LOGIC_VECTOR) in their port list, which will be automatically sized to match the signal ...
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6answers
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Code example for FIR/IIR filters in VHDL?

I'm trying to get started with DSP in my Spartan-3 board. I made a AC97 board with a chip from an old motherboard, and so far I got it to do ADC, multiply the samples for a number <1 (decrease ...
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3answers
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Which synthesis tools support VHDL libraries?

On various places across the net, I read that (some) synthesis tools do not respect VHDL libraries. These tools just throw all entities and packages into a single namespace, so that you cannot have <...
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3answers
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Is there a “Design Patterns” for synthesizable RTL?

For software, the book Design Patterns is a set of patterns for doing common things in software and it gives software practitioners common terminology to describe some of the components they need to ...
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3answers
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How can I generate a schematic block diagram image file from verilog?

I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a ...
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3answers
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FIFO : doubt in process(clk)

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1answer
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FIFO(vhdl) : Delete Operation

Suppose I have a FIFO code written in vhdl for FIFO. I want to delete an element from the FIFO. Here would the FIFO be acting the same as a linked list where I check each and every element of the FIFO ...
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2answers
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FIFO implementation in VHDL: is read function deleting the element of the FIFO?

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1answer
646 views

How does Xilinx ISE determine compilation order?

I’m working on a VHDL project which is a small SDRAM test. I have these entities: top sdramwrapper sdram <– generated IP core sdrampkg <– contains a package containing constants used several ...
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1answer
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How to create an n-bit multiplexer?

I'm needing to create a 4 bit, 16 input multiplexer. I know I could describe this as a long list of S => when "0000" etc.. but I think that's not very clean, and ...
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5answers
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Is there a more optimized way of making an incrementer than a full adder?

I'm designing a very simplistic microprocessor as a project to help learn VHDL. So I'm needing something to increment the 8 bit program counter. I will need to increment it by two. Is there a better (...
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4answers
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Can I use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E?

I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator. Is it possible to use something ...
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3answers
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VHDL: integers for synthesis?

I'm a bit confused on if I should be using integers in VHDL for synthesis signals and ports, etc. I use std_logic at top level ports, but internally I was using ranged integers all over the place. ...
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3answers
2k views

Which are the the valid VHDL compiler pragmas?

I know you can stop VHDL code from being compiled by the synthesizer: -- pragma translate_off assert thisDoesNotGetSynthesized(); -- pragma translate_on BUT, ...
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3answers
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How to convert a floating point number to integer, using VHDL?

I want to convert a floating point number to a integer number. Basically I have a floating point number between 1 and 0, with three decimal places, and I want to pass it to a integer number as if ...
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2answers
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Visual logic designer + simulation

in university we had our internal program called HLCCAD - it was very nice, and now I need to do design & debug some digital circuit and wondering what is current state of art software for that ...
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4answers
7k views

Xilinx ISE - VHDL: Code template to make a ROM

I am looking for a implementation of ROM using VHDL code. I´m looking for a piece of code to make this easy example in order to make a generalization afterwards. I want to put in the ROM these values:...
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1answer
490 views

Choosing a tool for development: System Generator vs Xilinx ISE

I am trying to make a an implementation of a vhdl design. It´s an application for signal processing. Does anyone know what is the fastest development tool Xilinx System Generator or Xilinx ISE. Thank ...
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1answer
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What is the file extension of the file that is loaded in a Xilinx FPGA?

I wonder what is the file extension that described the functionality of my design and is the file that is loaded in a Virtex 4 FPGA to get the behavior of my VHDL design. Thank you.
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4answers
905 views

Any good reference for digital architecture implementations of floating point arithmetic operations? [closed]

I am doing a thesis project. I need to make a FPGA implementation of a neural network. I want to implement some mathematical functions such as an exponential function. Does anyone know of any good ...
6
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2answers
808 views

Is there a free cross-platform tool for pure digital gate-level schematic design and simulation?

I'm searching a software tool for teaching purpose in order to teach students digital hardware (starting from logic gates level). Do you have something in mind that will allow making simple graphical ...
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6answers
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book recommendations on FPGA [closed]

what book titles would you recommend to get started with FPGAs and VHDL? edit I noticed that a few of the recommended books date back from 1996. I can imagine that the devices referred to will be ...
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5answers
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Exercise based book to learn Verilog/vhdl?

I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I ...
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3answers
25k views

Any native Mac OS X environments for getting started with VHDL / FPGAs?

The title pretty much sums up my question: Are there any native Mac OS X environments for getting started with VHDL / FPGAs?
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17answers
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Most affordable FPGA dev kit for learning VHDL and FPGA theory?

I'm looking for something that I can play around with but not spend too much on. I'm not eligible for an academic discount so take that into account when making suggestions.
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3answers
620 views

Resources to learn and test VHDL

Good Morning, I am a scripting programmer (PHP) and do a lot of backend development with web servers. I am very interested in learning VHDL, but the tutorials I have tried seem very antiquated and ...
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7answers
271k views

VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

I built a mod-16 counter, and the output result is a INTEGER (all the examples I saw used INTEGER). I built a hex-to-7-segment-display decoder, and its input is a STD_LOGIC_VECTOR (wrote it that way ...
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7answers
6k views

How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
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7answers
3k views

Readable and educational implementations of a CPU in a HDL

Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented. P.S. I know I can look at opencores, ...
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2answers
2k views

“Logic Design” vs. “Digital Circuit Design”

I'm aware that different companies have different definitions for job titles, but in general, is "logic design" the same thing as "digital circuit design"?
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8answers
4k views

Project to learn VHDL

I am an EE student and can write [at least simple] programs in more languages than I have fingers. I have just started learning VHDL and I was wondering what a good project would be to really get to ...

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